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[/] [openrisc/] [trunk/] [gnu-src/] [newlib-1.18.0/] [libgloss/] [mips/] [vr4300.S] - Blame information for rev 207

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1 207 jeremybenn
/*
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 * vr4300.S -- CPU specific support routines
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 *
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 * Copyright (c) 1995,1996 Cygnus Support
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 *
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 * The authors hereby grant permission to use, copy, modify, distribute,
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 * and license this software and its documentation for any purpose, provided
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 * that existing copyright notices are retained in all copies and that this
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 * notice is included verbatim in any distributions. No written agreement,
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 * license, or royalty fee is required for any of the authorized uses.
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 * Modifications to this software may be copyrighted by their authors
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 * and need not follow the licensing terms described here, provided that
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 * the new terms are clearly indicated on the first page of each file where
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 * they apply.
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 */
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#ifndef __mips64
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        .set mips3
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#endif
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#ifdef __mips16
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/* This file contains 32 bit assembly code.  */
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        .set nomips16
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#endif
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#include "regs.S"
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        .text
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        .align  2
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        # Taken from "R4300 Preliminary RISC Processor Specification
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        # Revision 2.0 January 1995" page 39: "The Count
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        # register... increments at a constant rate... at one-half the
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        # PClock speed."
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        # We can use this fact to provide small polled delays.
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        .globl  __cpu_timer_poll
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        .ent    __cpu_timer_poll
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__cpu_timer_poll:
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        .set    noreorder
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        # in:   a0 = (unsigned int) number of PClock ticks to wait for
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        # out:  void
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        # The Vr4300 counter updates at half PClock, so divide by 2 to
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        # get counter delta:
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        bnezl   a0, 1f          # continue if delta non-zero
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        srl     a0, a0, 1       # divide ticks by 2             {DELAY SLOT}
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        # perform a quick return to the caller:
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        j       ra
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        nop                     #                               {DELAY SLOT}
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1:
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        mfc0    v0, C0_COUNT    # get current counter value
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        nop
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        nop
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        # We cannot just do the simple test, of adding our delta onto
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        # the current value (ignoring overflow) and then checking for
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        # equality. The counter is incrementing every two PClocks,
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        # which means the counter value can change between
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        # instructions, making it hard to sample at the exact value
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        # desired.
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        # However, we do know that our entry delta value is less than
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        # half the number space (since we divide by 2 on entry). This
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        # means we can use a difference in signs to indicate timer
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        # overflow.
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        addu    a0, v0, a0      # unsigned add (ignore overflow)
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        # We know have our end value (which will have been
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        # sign-extended to fill the 64bit register value).
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2:
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        # get current counter value:
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        mfc0    v0, C0_COUNT
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        nop
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        nop
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        # This is an unsigned 32bit subtraction:
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        subu    v0, a0, v0      # delta = (end - now)           {DELAY SLOT}
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        bgtzl   v0, 2b          # looping back is most likely
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        nop
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        # We have now been delayed (in the foreground) for AT LEAST
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        # the required number of counter ticks.
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        j       ra              # return to caller
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        nop                     #                               {DELAY SLOT}
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        .set    reorder
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        .end    __cpu_timer_poll
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        # Flush the processor caches to memory:
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        .globl  __cpu_flush
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        .ent    __cpu_flush
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__cpu_flush:
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        .set    noreorder
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        # NOTE: The Vr4300 *CANNOT* have any secondary cache (bit 17
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        # of the CONFIG registered is hard-wired to 1). We just
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        # provide code to flush the Data and Instruction caches.
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        # Even though the Vr4300 has hard-wired cache and cache line
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        # sizes, we still interpret the relevant Config register
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        # bits. This allows this code to be used for other conforming
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        # MIPS architectures if desired.
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        # Get the config register
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        mfc0    a0, C0_CONFIG
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        nop
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        nop
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        li      a1, 1           # a useful constant
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        #
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        srl     a2, a0, 9       # bits 11..9 for instruction cache size
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        andi    a2, a2, 0x7     # 3bits of information
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        add     a2, a2, 12      # get full power-of-2 value
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        sllv    a2, a1, a2      # instruction cache size
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        #
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        srl     a3, a0, 6       # bits 8..6 for data cache size
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        andi    a3, a3, 0x7     # 3bits of information
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        add     a3, a3, 12      # get full power-of-2 value
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        sllv    a3, a1, a3      # data cache size
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        #
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        li      a1, (1 << 5)    # check IB (instruction cache line size)
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        and     a1, a0, a1      # mask against the CONFIG register value
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        beqz    a1, 1f          # branch on result of delay slot operation
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        nop
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        li      a1, 32          # non-zero, then 32bytes
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        j       2f              # continue
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        nop
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1:
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        li      a1, 16          # 16bytes
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2:
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        #
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        li      t0, (1 << 4)    # check DB (data cache line size)
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        and     a0, a0, t0      # mask against the CONFIG register value
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        beqz    a0, 3f          # branch on result of delay slot operation
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        nop
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        li      a0, 32          # non-zero, then 32bytes
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        j       4f              # continue
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        nop
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3:
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        li      a0, 16          # 16bytes
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4:
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        #
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        # a0 = data cache line size
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        # a1 = instruction cache line size
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        # a2 = instruction cache size
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        # a3 = data cache size
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        #
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        lui     t0, ((K0BASE >> 16) & 0xFFFF)
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        ori     t0, t0, (K0BASE & 0xFFFF)
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        addu    t1, t0, a2      # end cache address
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        subu    t2, a1, 1       # line size mask
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        not     t2              # invert the mask
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        and     t3, t0, t2      # get start address
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        addu    t1, -1
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        and     t1, t2          # get end address
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5:
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        cache   INDEX_INVALIDATE_I,0(t3)
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        bne     t3, t1, 5b
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        addu    t3, a1
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        #
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        addu    t1, t0, a3      # end cache address
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        subu    t2, a0, 1       # line size mask
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        not     t2              # invert the mask
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        and     t3, t0, t2      # get start address
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        addu    t1, -1
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        and     t1, t2          # get end address
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6:
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        cache   INDEX_WRITEBACK_INVALIDATE_D,0(t3)
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        bne     t3, t1, 6b
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        addu    t3, a0
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        #
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        j       ra      # return to the caller
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        nop
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        .set    reorder
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        .end    __cpu_flush
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        # NOTE: This variable should *NOT* be addressed relative to
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        # the $gp register since this code is executed before $gp is
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        # initialised... hence we leave it in the text area. This will
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        # cause problems if this routine is ever ROMmed:
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175
        .globl  __buserr_cnt
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__buserr_cnt:
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        .word   0
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        .align  3
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__k1_save:
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        .word   0
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        .word   0
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        .align  2
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        .ent __buserr
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        .globl __buserr
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__buserr:
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        .set noat
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        .set noreorder
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        # k0 and k1 available for use:
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        mfc0    k0,C0_CAUSE
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        nop
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        nop
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        andi    k0,k0,0x7c
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        sub     k0,k0,7 << 2
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        beq     k0,$0,__buserr_do
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        nop
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        # call the previous handler
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        la      k0,__previous
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        jr      k0
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        nop
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        #
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__buserr_do:
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        # TODO: check that the cause is indeed a bus error
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        # - if not then just jump to the previous handler
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        la      k0,__k1_save
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        sd      k1,0(k0)
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        #
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        la      k1,__buserr_cnt
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        lw      k0,0(k1)        # increment counter
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        addu    k0,1
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        sw      k0,0(k1)
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        #
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        la      k0,__k1_save
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        ld      k1,0(k0)
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        #
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        mfc0    k0,C0_EPC
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        nop
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        nop
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        addu    k0,k0,4         # skip offending instruction
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        mtc0    k0,C0_EPC       # update EPC
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        nop
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        nop
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        eret
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#        j       k0
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#        rfe
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        .set reorder
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        .set at
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        .end __buserr
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__exception_code:
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        .set noreorder
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        lui     k0,%hi(__buserr)
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        daddiu  k0,k0,%lo(__buserr)
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        jr      k0
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        nop
236
        .set reorder
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__exception_code_end:
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239
        .data
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__previous:
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        .space  (__exception_code_end - __exception_code)
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        # This subtracting two addresses is working
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        # but is not garenteed to continue working.
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        # The assemble reserves the right to put these
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        # two labels into different frags, and then
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        # cant take their difference.
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248
        .text
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250
        .ent    __default_buserr_handler
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        .globl  __default_buserr_handler
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__default_buserr_handler:
253
        .set noreorder
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        # attach our simple bus error handler:
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        # in:  void
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        # out: void
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        mfc0    a0,C0_SR
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        nop
259
        li      a1,SR_BEV
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        and     a1,a1,a0
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        beq     a1,$0,baseaddr
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        lui     a0,0x8000       # delay slot
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        lui     a0,0xbfc0
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        daddiu  a0,a0,0x0200
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baseaddr:
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        daddiu  a0,a0,0x0180
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        # a0 = base vector table address
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        la      a1,__exception_code_end
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        la      a2,__exception_code
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        subu    a1,a1,a2
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        la      a3,__previous
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        # there must be a better way of doing this????
273
copyloop:
274
        lw      v0,0(a0)
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        sw      v0,0(a3)
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        lw      v0,0(a2)
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        sw      v0,0(a0)
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        daddiu  a0,a0,4
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        daddiu  a2,a2,4
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        daddiu  a3,a3,4
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        subu    a1,a1,4
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        bne     a1,$0,copyloop
283
        nop
284
        la      a0,__buserr_cnt
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        sw      $0,0(a0)
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        j       ra
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        nop
288
        .set reorder
289
        .end    __default_buserr_handler
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291
        .ent    __restore_buserr_handler
292
        .globl  __restore_buserr_handler
293
__restore_buserr_handler:
294
        .set noreorder
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        # restore original (monitor) bus error handler
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        # in:  void
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        # out: void
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        mfc0    a0,C0_SR
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        nop
300
        li      a1,SR_BEV
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        and     a1,a1,a0
302
        beq     a1,$0,res_baseaddr
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        lui     a0,0x8000       # delay slot
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        lui     a0,0xbfc0
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        daddiu  a0,a0,0x0200
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res_baseaddr:
307
        daddiu  a0,a0,0x0180
308
        # a0 = base vector table address
309
        la      a1,__exception_code_end
310
        la      a3,__exception_code
311
        subu    a1,a1,a3
312
        la      a3,__previous
313
        # there must be a better way of doing this????
314
res_copyloop:
315
        lw      v0,0(a3)
316
        sw      v0,0(a0)
317
        daddiu  a0,a0,4
318
        daddiu  a3,a3,4
319
        subu    a1,a1,4
320
        bne     a1,$0,res_copyloop
321
        nop
322
        j       ra
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        nop
324
        .set reorder
325
        .end    __restore_buserr_handler
326
 
327
        .ent    __buserr_count
328
        .globl  __buserr_count
329
__buserr_count:
330
        .set noreorder
331
        # restore original (monitor) bus error handler
332
        # in:  void
333
        # out: unsigned int __buserr_cnt
334
        la      v0,__buserr_cnt
335
        lw      v0,0(v0)
336
        j       ra
337
        nop
338
        .set reorder
339
        .end    __buserr_count
340
 
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/* EOF vr4300.S */

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