OpenCores
URL https://opencores.org/ocsvn/openrisc_me/openrisc_me/trunk

Subversion Repositories openrisc_me

[/] [openrisc/] [trunk/] [gnu-src/] [newlib-1.18.0/] [libgloss/] [pa/] [w89k.h] - Blame information for rev 326

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 207 jeremybenn
/* Copyright (c) 1995 Cygnus Support
2
 *
3
 * The authors hereby grant permission to use, copy, modify, distribute,
4
 * and license this software and its documentation for any purpose, provided
5
 * that existing copyright notices are retained in all copies and that this
6
 * notice is included verbatim in any distributions. No written agreement,
7
 * license, or royalty fee is required for any of the authorized uses.
8
 * Modifications to this software may be copyrighted by their authors
9
 * and need not follow the licensing terms described here, provided that
10
 * the new terms are clearly indicated on the first page of each file where
11
 * they apply.
12
 *
13
 * The w89k uses a memory mapped I/O scheme as well as a PC style ISA bus.
14
 * All I/O accesses are via a port.
15
 */
16
#define IOSPACE         0xf0000000
17
#define outp(port,val)  *((volatile unsigned char*)(IOSPACE+port))=val
18
#define inp(port)       *((volatile unsigned char*)(IOSPACE+port))
19
#define RS232PORT       0x3f8
20
#define COM1_LSR        (0x3f8 + 5)
21
#define COM1_DATA       (0x3f8 + 0)
22
 
23
#define RS232REG        0x3fd
24
#define TRANSMIT        0x20
25
#define RECEIVE         0x01

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.