OpenCores
URL https://opencores.org/ocsvn/openrisc_me/openrisc_me/trunk

Subversion Repositories openrisc_me

[/] [openrisc/] [trunk/] [gnu-src/] [newlib-1.18.0/] [libgloss/] [sparc/] [erc32-io.c] - Blame information for rev 258

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 207 jeremybenn
#define USE_PORT_A
2
 
3
#define RXADATA (int *) 0x01F800E0
4
#define RXBDATA (int *) 0x01F800E4
5
#define RXSTAT (int *) 0x01F800E8
6
 
7
void
8
outbyte (int c)
9
{
10
  volatile int *rxstat;
11
  volatile int *rxadata;
12
  int rxmask;
13
 
14
  rxstat = RXSTAT;
15
#ifdef USE_PORT_A
16
  rxadata = RXADATA;
17
  rxmask = 6;
18
#else
19
  rxadata = RXBDATA;
20
  rxmask = 0x60000;
21
#endif
22
 
23
  while ((*rxstat & rxmask) == 0);
24
 
25
  *rxadata = c;
26
}
27
 
28
int
29
inbyte (void)
30
{
31
  volatile int *rxstat;
32
  volatile int *rxadata;
33
  int rxmask;
34
 
35
  rxstat = RXSTAT;
36
#ifdef USE_PORT_A
37
  rxadata = RXADATA;
38
  rxmask = 1;
39
#else
40
  rxadata = RXBDATA;
41
  rxmask = 0x10000;
42
#endif
43
 
44
  while ((*rxstat & rxmask) == 0);
45
 
46
  return *rxadata;
47
}

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.