OpenCores
URL https://opencores.org/ocsvn/openrisc_me/openrisc_me/trunk

Subversion Repositories openrisc_me

[/] [openrisc/] [trunk/] [gnu-src/] [newlib-1.18.0/] [newlib/] [libc/] [machine/] [arm/] [strlen.c] - Blame information for rev 207

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 207 jeremybenn
/*
2
 * Copyright (c) 2008 ARM Ltd
3
 * All rights reserved.
4
 *
5
 * Redistribution and use in source and binary forms, with or without
6
 * modification, are permitted provided that the following conditions
7
 * are met:
8
 * 1. Redistributions of source code must retain the above copyright
9
 *    notice, this list of conditions and the following disclaimer.
10
 * 2. Redistributions in binary form must reproduce the above copyright
11
 *    notice, this list of conditions and the following disclaimer in the
12
 *    documentation and/or other materials provided with the distribution.
13
 * 3. The name of the company may not be used to endorse or promote
14
 *    products derived from this software without specific prior written
15
 *    permission.
16
 *
17
 * THIS SOFTWARE IS PROVIDED BY ARM LTD ``AS IS'' AND ANY EXPRESS OR IMPLIED
18
 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
19
 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20
 * IN NO EVENT SHALL ARM LTD BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21
 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
22
 * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
23
 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
24
 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
25
 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
26
 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27
 */
28
 
29
#include "arm_asm.h"
30
#include <_ansi.h>
31
#include <string.h>
32
#include <limits.h>
33
 
34
#if defined (__OPTIMIZE_SIZE__) || defined (PREFER_SIZE_OVER_SPEED) || \
35
  (defined (__thumb__) && !defined (__thumb2__))
36
 
37
size_t
38
strlen (const char* str)
39
{
40
  int scratch;
41
#if defined (__thumb__) && !defined (__thumb2__)
42
  size_t len;
43
  asm ("mov     %0, #0\n"
44
       "1:\n\t"
45
       "ldrb    %1, [%2, %0]\n\t"
46
       "add     %0, %0, #1\n\t"
47
       "cmp     %1, #0\n\t"
48
       "bne     1b"
49
       : "=&r" (len), "=&r" (scratch) : "r" (str) : "memory", "cc");
50
  return len - 1;
51
#else
52
  const char* end;
53
  asm ("1:\n\t"
54
       "ldrb    %1, [%0], #1\n\t"
55
       "cmp     %1, #0\n\t"
56
       "bne     1b"
57
       : "=&r" (end), "=&r" (scratch) : "0" (str) : "memory", "cc");
58
  return end - str - 1;
59
#endif
60
}
61
#else
62
 
63
size_t __attribute__((naked))
64
strlen (const char* str)
65
{
66
  asm ("len .req r0\n\t"
67
       "data .req r3\n\t"
68
       "addr .req r1\n\t"
69
 
70
       "optpld r0\n\t"
71
       /* Word-align address */
72
       "bic     addr, r0, #3\n\t"
73
       /* Get adjustment for start ... */
74
       "ands    len, r0, #3\n\t"
75
       "neg     len, len\n\t"
76
       /* First word of data */
77
       "ldr     data, [addr], #4\n\t"
78
       /* Ensure bytes preceeding start ... */
79
       "add     ip, len, #4\n\t"
80
       "mov     ip, ip, asl #3\n\t"
81
       "mvn     r2, #0\n\t"
82
       /* ... are masked out */
83
#ifdef __thumb__
84
       "itt     ne\n\t"
85
# ifdef __ARMEB__
86
       "lslne   r2, ip\n\t"
87
# else
88
       "lsrne   r2, ip\n\t"
89
# endif
90
       "orrne   data, data, r2\n\t"
91
#else
92
       "it      ne\n\t"
93
# ifdef __ARMEB__
94
       "orrne   data, data, r2, lsl ip\n\t"
95
# else
96
       "orrne   data, data, r2, lsr ip\n\t"
97
# endif
98
#endif
99
       /* Magic const 0x01010101 */
100
#ifdef _ISA_ARM_7
101
       "movw    ip, #0x101\n\t"
102
#else
103
       "mov     ip, #0x1\n\t"
104
       "orr     ip, ip, ip, lsl #8\n\t"
105
#endif
106
       "orr     ip, ip, ip, lsl #16\n"
107
 
108
        /* This is the main loop.  We subtract one from each byte in
109
           the word: the sign bit changes iff the byte was zero or
110
           0x80 -- we eliminate the latter case by anding the result
111
           with the 1-s complement of the data.  */
112
       "1:\n\t"
113
       /* test (data - 0x01010101)  */
114
       "sub     r2, data, ip\n\t"
115
       /* ... & ~data */
116
       "bic     r2, r2, data\n\t"
117
       /* ... & 0x80808080 == 0? */
118
       "ands    r2, r2, ip, lsl #7\n\t"
119
#ifdef _ISA_ARM_7
120
       /* yes, get more data... */
121
       "itt     eq\n\t"
122
       "ldreq   data, [addr], #4\n\t"
123
       /* and 4 more bytes  */
124
       "addeq   len, len, #4\n\t"
125
        /* If we have PLD, then unroll the loop a bit.  */
126
       "optpld addr, #8\n\t"
127
       /*  test (data - 0x01010101)  */
128
       "ittt    eq\n\t"
129
       "subeq   r2, data, ip\n\t"
130
       /* ... & ~data */
131
       "biceq   r2, r2, data\n\t"
132
       /* ... & 0x80808080 == 0? */
133
       "andeqs  r2, r2, ip, lsl #7\n\t"
134
#endif
135
       "itt     eq\n\t"
136
       /* yes, get more data... */
137
       "ldreq   data, [addr], #4\n\t"
138
       /* and 4 more bytes  */
139
       "addeq   len, len, #4\n\t"
140
       "beq     1b\n\t"
141
#ifdef __ARMEB__
142
       "tst     data, #0xff000000\n\t"
143
       "itttt   ne\n\t"
144
       "addne   len, len, #1\n\t"
145
       "tstne   data, #0xff0000\n\t"
146
       "addne   len, len, #1\n\t"
147
       "tstne   data, #0xff00\n\t"
148
       "it      ne\n\t"
149
       "addne   len, len, #1\n\t"
150
#else
151
# ifdef _ISA_ARM_5
152
        /* R2 is the residual sign bits from the above test.  All we
153
        need to do now is establish the position of the first zero
154
        byte... */
155
        /* Little-endian is harder, we need the number of trailing
156
        zeros / 8 */
157
#  ifdef _ISA_ARM_7
158
       "rbit    r2, r2\n\t"
159
       "clz     r2, r2\n\t"
160
#  else
161
       "rsb     r1, r2, #0\n\t"
162
       "and     r2, r2, r1\n\t"
163
       "clz     r2, r2\n\t"
164
       "rsb     r2, r2, #31\n\t"
165
#  endif
166
       "add     len, len, r2, lsr #3\n\t"
167
# else  /* No CLZ instruction */
168
       "tst     data, #0xff\n\t"
169
       "itttt   ne\n\t"
170
       "addne   len, len, #1\n\t"
171
       "tstne   data, #0xff00\n\t"
172
       "addne   len, len, #1\n\t"
173
       "tstne   data, #0xff0000\n\t"
174
       "it      ne\n\t"
175
       "addne   len, len, #1\n\t"
176
# endif
177
#endif
178
       "RETURN");
179
}
180
#endif

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.