OpenCores
URL https://opencores.org/ocsvn/openrisc_me/openrisc_me/trunk

Subversion Repositories openrisc_me

[/] [openrisc/] [trunk/] [gnu-src/] [newlib-1.18.0/] [newlib/] [libc/] [machine/] [tic4x/] [setjmp.S] - Blame information for rev 437

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 207 jeremybenn
/* setjmp/longjmp routines.
2
 *
3
 * Written by Michael Hayes .
4
 *
5
 * The author hereby grant permission to use, copy, modify, distribute,
6
 * and license this software and its documentation for any purpose, provided
7
 * that existing copyright notices are retained in all copies and that this
8
 * notice is included verbatim in any distributions. No written agreement,
9
 * license, or royalty fee is required for any of the authorized uses.
10
 * Modifications to this software may be copyrighted by their authors
11
 * and need not follow the licensing terms described here, provided that
12
 * the new terms are clearly indicated on the first page of each file where
13
 * they apply.
14
 */
15
 
16
        .sect .text
17
        .global setjmp
18
        .global longjmp
19
 
20
setjmp:
21
        pop     r1
22
        ldi     sp, ar0
23
#ifndef _REGPARM
24
        ldi     *ar0, ar2
25
#endif
26
 
27
        sti     r4, *ar2++
28
        sti     r5, *ar2++
29
        stf     r6, *ar2++
30
        stf     r7, *ar2++
31
#ifdef _TMS320C4x
32
        sti     r8, *ar2++
33
#endif
34
        sti     ar3, *ar2++
35
        sti     ar4, *ar2++
36
        sti     ar5, *ar2++
37
        sti     ar6, *ar2++
38
        sti     ar7, *ar2++
39
        bd      r1
40
        sti     r1, *ar2++
41
        sti     ar0, *ar2
42
        ldi     0, r0
43
 
44
 
45
longjmp:
46
#ifndef _REGPARM
47
        ldi     sp, ar0
48
        ldi     *-ar0(1), ar2
49
        ldi     *-ar0(2), r0
50
        ldiz    1, r0
51
#else
52
        ldi     r2, r0
53
        ldiz    1, r0
54
#endif
55
 
56
        ldi     *ar2++, r4
57
        ldi     *ar2++, r5
58
        ldf     *ar2++, r6
59
        ldf     *ar2++, r7
60
#ifdef _TMS320C4x
61
        ldi     *ar2++, r8
62
#endif
63
        ldi     *ar2++, ar3
64
        ldi     *ar2++, ar4
65
        ldi     *ar2++, ar5
66
        ldi     *ar2++, ar6
67
        ldi     *ar2++, ar7
68
        ldi     *ar2++, r1
69
        ldi     *ar2, sp
70
 
71
        b        r1
72
        .end
73
 
74
 
75
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.