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jeremybenn |
; @(#)cpudef.h 2.3 90/10/14 20:55:56, Copyright 1989, 1990 AMD
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;-----------------------------------------------------------------------
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; Useful equates
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;-----------------------------------------------------------------------
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;
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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; Copyright 1989, 1990 Advanced Micro Devices, Inc.
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;
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; This software is the property of Advanced Micro Devices, Inc (AMD) which
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; specifically grants the user the right to modify, use and distribute this
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; software provided this notice is not removed or altered. All other rights
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; are reserved by AMD.
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;
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; AMD MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS
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; SOFTWARE. IN NO EVENT SHALL AMD BE LIABLE FOR INCIDENTAL OR CONSEQUENTIAL
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; DAMAGES IN CONNECTION WITH OR ARISING FROM THE FURNISHING, PERFORMANCE, OR
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; USE OF THIS SOFTWARE.
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;
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; So that all may benefit from your experience, please report any problems
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; or suggestions about this software to the 29K Technical Support Center at
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; 800-29-29-AMD (800-292-9263) in the USA, or 0800-89-1131 in the UK, or
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; 0031-11-1129 in Japan, toll free. The direct dial number is 512-462-4118.
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;
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; Advanced Micro Devices, Inc.
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; 29K Support Products
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; Mail Stop 573
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; 5900 E. Ben White Blvd.
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; Austin, TX 78741
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; 800-292-9263
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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; Processor status registers OPS (sr1) and CPS (sr2)
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.equ CA,0x8000 ; Coprocessor active
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.equ IP,0x4000 ; Interrupt pending
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.equ TE,0x2000 ; Trace enable
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.equ TP,0x1000 ; Trace pending
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.equ TU,0x0800 ; Trap unaligned access
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.equ FZ,0x0400 ; Freeze
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.equ LK,0x0200 ; Lock
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.equ RE,0x0100 ; ROM enable
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.equ WM,0x0080 ; Wait mode
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.equ PD,0x0040 ; No translation for Data
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.equ PI,0x0020 ; No translation for Instr
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.equ SM,0x0010 ; Supervisor mode
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.equ IM,0x000C ; Interrupt mask
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.equ IM1,0x0100 ; enable INTR0-1
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.equ IM2,0x1000 ; enable INTR0-2
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.equ IM3,0x1100 ; enable INTR0-3
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.equ DI,0x0002 ; Disable ints
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.equ DA,0x0001 ; Disable ints and traps
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; Configuration register CFG (sr3)
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.equ PRL,0xFF000000 ; Processor release level
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.equ VF,0x10 ; Vector fetch
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.equ RV,0x08 ; ROM Vector area
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.equ BO,0x04 ; Byte order
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.equ CP,0x02 ; Coprocessor present
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.equ CD,0x01 ; BTC disable
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; Channel control register CHC (sr6)
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.equ LS,0x8000 ; Load store
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.equ ML,0x4000 ; Multiple operation
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.equ ST,0x2000 ; Set
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.equ LA,0x1000 ; Lock active
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.equ TF,0x0400 ; Transaction faulted
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.equ TR,0x03FC ; Target register
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.equ NN,0x0002 ; Not needed
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.equ CV,0x0001 ; Contents valid
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; Timer reload register TMR (sr9)
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.equ IE,0x01000000 ; timer int enable
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.equ IN,0x02000000 ; timer int pending
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.equ OV,0x04000000 ; timer Overflow
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; MMU configuration register MMU (sr13)
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.equ PS,0x300 ; Page size
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.equ PID,0xFF ; Process identifier
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; ALU status register ALU (sr132)
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.equ DF,0x800 ; Divide flag
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.equ V,0x400 ; Overflow
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.equ N,0x200 ; Negative
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.equ Z,0x100 ; Zero
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.equ C,0x080 ; Carry
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; TLB entry
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.equ VTAG,0xFFFF8000 ; Virtual tag
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.equ VE,0x4000 ; Valid entry
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.equ SR,0x2000 ; Supervisor read
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.equ SW,0x1000 ; Supervisor write
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.equ SE,0x0800 ; Supervisor execute
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.equ UR,0x0400 ; User read
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.equ UW,0x0200 ; User write
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.equ UE,0x0100 ; User execute
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.equ TID,0x00FF ; Task identifier
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.equ RPN,0xFFFFFC00 ; Real page number
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.equ PGM,0x00C0 ; User programmable
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.equ U,0x0002 ; Usage
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.equ F,0x0001 ; Flag
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;-----------------------------------------------------------------------
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;Global registers
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;-----------------------------------------------------------------------
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.reg rsp, gr1 ; local register stack pointer
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; System-wide statics
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.reg s0, gr64
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.reg spillreg, s0 ; pointer to user spill handler
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.reg s1, gr65
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.reg fillreg, s1 ; pointer to user fill handler
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.reg s2, gr66
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.reg heapptr, s2 ; pointer to heap area
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.reg s3, gr67
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.reg s4, gr68
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.reg s5, gr69
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.reg s6, gr70
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.reg s7, gr71
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.reg s8, gr72
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.reg s9, gr73
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.reg s10, gr74
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.reg s11, gr75
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.reg s12, gr76
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.reg s13, gr77
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.reg s14, gr78
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.reg s15, gr79
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; Interrupt handler temporaries
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.reg i0, gr80
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.reg i1, gr81
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.reg i2, gr82
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.reg i3, gr83
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.reg i4, gr84
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.reg i5, gr85
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.reg i6, gr86
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.reg i7, gr87
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.reg i8, gr88
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.reg i9, gr89
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.reg i10, gr90
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.reg i11, gr91
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.reg i12, gr92
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.reg i13, gr93
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.reg i14, gr94
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.reg i15, gr95
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; Subroutine/function temporaries
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; also used for function return values
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.reg t0, gr96
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.reg rtn, t0
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.reg t1, gr97
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.reg t2, gr98
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.reg t3, gr99
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.reg t4, gr100
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.reg t5, gr101
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.reg t6, gr102
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.reg t7, gr103
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.reg t8, gr104
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.reg t9, gr105
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.reg t10, gr106
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.reg t11, gr107
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.reg t12, gr108
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.reg t13, gr109
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.reg t14, gr110
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.reg t15, gr111
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; User process statics
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.reg u0, gr112
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.reg u1, gr113
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.reg u2, gr114
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.reg u3, gr115
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; More subroutine/function temporaries
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.reg t16, gr116
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.reg t17, gr117
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.reg t18, gr118
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.reg t19, gr119
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.reg t20, gr120
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; Older names for the same registers
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.reg tmp0, gr116
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.reg tmp1, gr117
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.reg tmp2, gr118
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.reg tmp3, gr119
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.reg tmp4, gr120
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; Trap handler temporaries
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.reg tav, gr121 ; arg/temp
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.reg tpc, gr122 ; rtn/temp
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; Linkage pointers
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.reg lrp, gr123 ; large rtn ptr
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.reg slp, gr124 ; static link ptr
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.reg msp, gr125 ; memory stack ptr
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.reg rab, gr126 ; register allocate bound
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.reg rfb, gr127 ; register free bound
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;-----------------------------------------------------------------------
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;Local compiler registers
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; (only valid if frame has been established)
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;-----------------------------------------------------------------------
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.reg p15, lr17 ; outgoing arg 16
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.reg p14, lr16 ; outgoing arg 15
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.reg p13, lr15 ; outgoing arg 14
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.reg p12, lr14 ; outgoing arg 13
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.reg p11, lr13 ; outgoing arg 12
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.reg p10, lr12 ; outgoing arg 11
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.reg p9, lr11 ; outgoing arg 10
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.reg p8, lr10 ; outgoing arg 9
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.reg p7, lr9 ; outgoing arg 8
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.reg p6, lr8 ; outgoing arg 7
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.reg p5, lr7 ; outgoing arg 6
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.reg p4, lr6 ; outgoing arg 5
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.reg p3, lr5 ; outgoing arg 4
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.reg p2, lr4 ; outgoing arg 3
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.reg p1, lr3 ; outgoing arg 2
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.reg p0, lr2 ; outgoing arg 1
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.reg fp, lr1 ; frame pointer
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.reg raddr, lr0 ; return address
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;-----------------------------------------------------------------------
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; Vectors
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;-----------------------------------------------------------------------
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.equ V_ILLEG, 0 ; Illegal opcode
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.equ V_ALIGN, 1 ; Unaligned access
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.equ V_RANGE, 2 ; Out of range
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.equ V_COPRE, 3 ; Coprocessor not present
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.equ V_COEXC, 4 ; Coprocessor exception
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.equ V_PROT, 5 ; Protection violation
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.equ V_INSTR, 6 ; Instruction access exception
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.equ V_DATA, 7 ; Data access exception
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.equ V_UITLB, 8 ; User-mode instruction TLB miss
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.equ V_UDTLB, 9 ; User-mode data TLB miss
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.equ V_SITLB, 10 ; Supervisor-mode instr TLB miss
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.equ V_SDTLB, 11 ; Supervisor-mode data TLB miss
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.equ V_ITLB, 12 ; Instruction TLB violation
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.equ V_DTLB, 13 ; Data TLB violation
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.equ V_TIMER, 14 ; Timer
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.equ V_TRACE, 15 ; Trace
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.equ V_INTR0, 16 ; Interrupt 0
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.equ V_INTR1, 17 ; Interrupt 1
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.equ V_INTR2, 18 ; Interrupt 2
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.equ V_INTR3, 19 ; Interrupt 3
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.equ V_TRAP0, 20 ; Trap 0
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.equ V_TRAP1, 21 ; Trap 1
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;-----------------------------------------------------------------------
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;constants for LOAD and STORE operations
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;-----------------------------------------------------------------------
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; CE operand values
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.equ CE, 0b1 ;coprocessor enable
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.equ ME, 0b0 ; memory enable
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; CNTL operand values
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.equ IO, 0b1000000 ;set for I/O
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.equ PA, 0b0100000 ;force physical addr
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.equ SB, 0b0010000 ;set for set BP
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.equ UA, 0b0001000 ;force user mode access
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.equ ROM, 0b0000100 ;ROM access
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.equ HWORD, 0b0000010 ;Half word access
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.equ BYTE, 0b0000001 ;Byte access
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.equ WORD, 0b0000000 ;Word access
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;-----------------------------------------------------------------------
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; stack alignment value
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;-----------------------------------------------------------------------
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.equ STKALIGN, 8 ; double word align
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