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[/] [openrisc/] [trunk/] [gnu-src/] [newlib-1.18.0/] [newlib/] [libm/] [machine/] [spu/] [headers/] [divf4.h] - Blame information for rev 207

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1 207 jeremybenn
/* --------------------------------------------------------------  */
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/* (C)Copyright 2001,2008,                                         */
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/* International Business Machines Corporation,                    */
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/* Sony Computer Entertainment, Incorporated,                      */
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/* Toshiba Corporation,                                            */
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/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.              */
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/* --------------------------------------------------------------  */
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/* PROLOG END TAG zYx                                              */
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#ifdef __SPU__
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#ifndef _DIVF4_H_
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#define _DIVF4_H_       1
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#include <spu_intrinsics.h>
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/*
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 * FUNCTION
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 *      vector float _divf4(vector float dividend, vector float divisor)
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 *
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 * DESCRIPTION
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 *      The _divf4 function divides the vector dividend by the vector divisor
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 *      and returns the resulting vector quotient.
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 *
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 */
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static __inline vector float _divf4(vector float a, vector float b)
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{
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  /* This function has been designed to provide a
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   * full function operation that presisely computes
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   * the quotient for the entire range of extended
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   * single precision inputs <a> and <b>. This includes:
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   *
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   * 1) Computing the quotient to full single precision
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   *    floating point accuracy.
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   * 2) Round the result consistently with the rounding
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   *    mode of the processor - truncated toward zero.
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   * 3) Underflow and overflow results are clamped to
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   *    Smin and Smax and flagged with the appropriate
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   *    UNF or OVF exception in the FPSCR.
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   * 4) Divide By Zero (DBZ) exception is produced when
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   *    the divisor <b> has a zero exponent. A quotient
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   *    of correctly signed Smax is produced.
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   * 5) Denorm/zero divided by a denorm/zero generates
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   *    a DBZ with the results undefined.
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   * 6) Resulting denorm quotients will be coerced to +0.
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   * 7) If a non-compliant IEEE result is produced, the
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   *    a DIFF exception is generated.
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   */
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  vector float inv_b, err, q0, q1, q2;
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  vector float mult;
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  vector float mant_a, mant_b;
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  vector float one = spu_splats(1.0f);
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  vector unsigned int exp, exp_a, exp_b, overflow;
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  vector unsigned int exp_mask = (vec_uint4)spu_splats(0x7F800000);
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  /* If b has a zero exponent, then set the divide by zero
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   * (DBZ) exception flag. The estimate result is discarded.
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   * Note: This must be implemented as inline assembly. Otherwise
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   * the optimizer removes it.
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   */
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  (void)si_frest((qword)(b));
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  /* For computing the quotient, force the divisor and
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   * dividend into the range (1.0 <= 0 < 2.0).
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   */
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  mant_a = spu_sel(a, one, exp_mask);
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  mant_b = spu_sel(b, one, exp_mask);
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  /* Compute the quotient using reciprocal estimate
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   * followed by one iteration of the Newton-Raphson.
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   */
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  inv_b = spu_re(mant_b);
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  q0 = spu_mul(mant_a, inv_b);
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  q1 = spu_nmsub(mant_b, q0, mant_a);
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  q1 = spu_madd(inv_b, q1, q0);
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  /* Due to truncation error, the quotient result
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   * may be low by 1 ulp (unit of least position),
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   * Conditionally add one if the estimate is too
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   * small.
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   */
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  q2 = (vector float)spu_add((vector unsigned int)(q1), 1);
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  err = spu_nmsub(mant_b, q2, mant_a);
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  q2 = spu_sel(q1, q2, spu_cmpgt((vector signed int)err, -1));
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  /* Compute the quotient's expected exponent. If the exponent
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   * is out of range, then force the resulting exponent to 0.
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   * (127 with the bias). We correct for the out of range
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   * values by computing a multiplier (mult) that will force the
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   * result to the correct out of range value and set the
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   * correct exception flag (UNF, OVF, or neither). The multiplier
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   * is also conditioned to generate correctly signed Smax if the
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   * divisor b is a denorm or zero.
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   */
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  exp_a = spu_and((vector unsigned int)a, exp_mask);
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  exp_b = spu_and((vector unsigned int)b, exp_mask);
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  exp   = spu_add(spu_sub(spu_add(exp_a, (vector unsigned int)one), exp_b), spu_cmpabsgt(mant_b, mant_a));
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  /* The default multiplier is 1.0. If an underflow is detected (ie,
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   * either the dividend <a> is a denorm/zero, or the computed exponent is
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   * less than or equal to a biased 0), force the multiplier to 0.0.
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   */
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  mult = spu_and(one, (vector float)spu_cmpgt((vector signed int)exp, 0));
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  /* Force the multiplier to positive Smax (0x7FFFFFFF) and the biased exponent
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   * to 127, if the divisor is denorm/zero or the computed biased exponent is
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   * greater than 255.
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   */
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  overflow = spu_or(spu_cmpeq(exp_b, 0), spu_cmpeq(spu_rlmask(exp, -30), 2));
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  exp = spu_sel(exp, (vector unsigned int)one, overflow);
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  mult = spu_or(mult, (vector float)spu_rlmask(overflow, -1));
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  mult = spu_andc(mult, (vector float)spu_cmpeq(exp_a, 0));
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  /* Insert the exponent into the result and perform the
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   * final multiplication.
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   */
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  q2    = spu_sel(q2, (vector float)exp, exp_mask);
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  q2    = spu_mul(q2, mult);
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  return (q2);
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}
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#endif /* _DIVF4_H_ */
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#endif /* __SPU__ */

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