OpenCores
URL https://opencores.org/ocsvn/openrisc_2011-10-31/openrisc_2011-10-31/trunk

Subversion Repositories openrisc_2011-10-31

[/] [openrisc/] [trunk/] [gnu-src/] [newlib-1.18.0/] [newlib/] [libm/] [machine/] [spu/] [headers/] [nextafterd2.h] - Blame information for rev 207

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 207 jeremybenn
/* --------------------------------------------------------------  */
2
/* (C)Copyright 2007,2008,                                         */
3
/* International Business Machines Corporation                     */
4
/* All Rights Reserved.                                            */
5
/*                                                                 */
6
/* Redistribution and use in source and binary forms, with or      */
7
/* without modification, are permitted provided that the           */
8
/* following conditions are met:                                   */
9
/*                                                                 */
10
/* - Redistributions of source code must retain the above copyright*/
11
/*   notice, this list of conditions and the following disclaimer. */
12
/*                                                                 */
13
/* - Redistributions in binary form must reproduce the above       */
14
/*   copyright notice, this list of conditions and the following   */
15
/*   disclaimer in the documentation and/or other materials        */
16
/*   provided with the distribution.                               */
17
/*                                                                 */
18
/* - Neither the name of IBM Corporation nor the names of its      */
19
/*   contributors may be used to endorse or promote products       */
20
/*   derived from this software without specific prior written     */
21
/*   permission.                                                   */
22
/*                                                                 */
23
/* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND          */
24
/* CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,     */
25
/* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF        */
26
/* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE        */
27
/* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR            */
28
/* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,    */
29
/* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT    */
30
/* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;    */
31
/* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)        */
32
/* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN       */
33
/* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR    */
34
/* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,  */
35
/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.              */
36
/* --------------------------------------------------------------  */
37
/* PROLOG END TAG zYx                                              */
38
#ifdef __SPU__
39
#ifndef _NEXTAFTERD2_H_
40
#define _NEXTAFTERD2_H_ 1
41
 
42
#include <spu_intrinsics.h>
43
 
44
/*
45
 * FUNCTION
46
 *  vector double _nextafterd2(vector double x, vector double y)
47
 *
48
 * DESCRIPTION
49
 *  The nextafterf4 function returns a vector containing the next representable
50
 *  floating-point number after the element of x, in the direction of the
51
 *  corresponding element y.
52
 *
53
 *  Special Cases:
54
 *      - nextafter(NaN, y) = NaN
55
 *      - nextafter(x, NaN) = NaN
56
 *      - x = largest finite value, y = infinity, result is undefined
57
 *      - x = largest finite negative value, y = -infinity, result is undefined
58
 *      - x != y, and result = 0, considered an underflow
59
 *
60
 */
61
 
62
static __inline vector double _nextafterd2(vector double x, vector double y)
63
{
64
    vec_double2 n1ulp = (vec_double2)spu_splats(0x8000000000000001ull);
65
    vector unsigned char mov_carry = {0x80,0x80,0x80, 7, 0x80,0x80,0x80,0x80,
66
                                      0x80,0x80,0x80,15, 0x80,0x80,0x80,0x80};
67
    vec_double2 zerod = spu_splats(0.0);
68
    vec_llong2  one   = spu_splats(1ll);
69
    vec_ullong2 xlt0, xgty, xeqy, xeq0;
70
    vec_llong2  xllong;
71
    vec_int4    carry;
72
    vec_llong2  delta, deltap1;
73
    vec_double2 result;
74
 
75
    /* Compiler Bug. Replace xtmp/ytmp with x/y when spu_cmpgt(x,y) doesn't change x/y!*/
76
    volatile vec_double2 xtmp = x;
77
    volatile vec_double2 ytmp = y;
78
 
79
    /*
80
     * The idea here is to treat x as a signed long long value, which allows us to
81
     * add or subtact one to/from it to get the next representable value.
82
     */
83
 
84
    xeq0 = spu_cmpeq(xtmp, zerod);
85
    xlt0 = spu_cmpgt(zerod, xtmp);
86
    xeqy = spu_cmpeq(xtmp, ytmp);
87
    xgty = spu_cmpgt(xtmp, ytmp);
88
 
89
    /* If x = -0.0, set x = 0.0 */
90
    x = spu_andc(x, (vec_double2)xeq0);
91
 
92
    xllong = (vec_llong2)x;
93
 
94
    /* Determine value to add to x */
95
    delta = (vec_llong2)spu_xor(xgty, xlt0);
96
 
97
    //deltap1 = delta + one;
98
    carry = spu_genc((vec_int4)delta, (vec_int4)one);
99
    carry = spu_shuffle(carry, carry, mov_carry);
100
    deltap1 = (vec_llong2)spu_addx((vec_int4)delta, (vec_int4)one, (vec_int4)carry);
101
 
102
    delta = spu_sel(deltap1, delta, (vec_ullong2)delta);
103
 
104
    //xllong = xllong + delta;
105
    carry = spu_genc((vec_int4)xllong, (vec_int4)delta);
106
    carry = spu_shuffle(carry, carry, mov_carry);
107
    xllong = (vec_llong2)spu_addx((vec_int4)xllong, (vec_int4)delta, (vec_int4)carry);
108
 
109
    /* Fix the case of x = 0, and answer should be -1 ulp */
110
    result = spu_sel((vec_double2)xllong, n1ulp, spu_and((vec_ullong2)delta, xeq0));
111
 
112
    /*
113
     * Special Cases
114
     */
115
 
116
    /* x = y */
117
    result = spu_sel(result, y, xeqy);
118
 
119
    return result;
120
}
121
 
122
#endif /* _NEXTAFTERD2_H_ */
123
#endif /* __SPU__ */

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.