OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [gnu-stable/] [binutils-2.20.1/] [gas/] [testsuite/] [gas/] [arm/] [neon-cond.d] - Blame information for rev 818

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 205 julius
# name: Conditional Neon instructions
2
# as: -mfpu=neon
3
# objdump: -dr --prefix-addresses --show-raw-insn
4
 
5
.*: +file format .*arm.*
6
 
7
Disassembly of section \.text:
8
0[0-9a-f]+ <[^>]+> 0d943b00         vldreq  d3, \[r4\]
9
0[0-9a-f]+ <[^>]+> be035b70         vmovlt\.16      d3\[1\], r5
10
0[0-9a-f]+ <[^>]+> ac474b13         vmovge  d3, r4, r7
11
0[0-9a-f]+ <[^>]+> 3c543b3e         vmovcc  r3, r4, d30
12
0[0-9a-f]+ <[^>]+> 1e223b10         vmovne\.32      d2\[1\], r3
13
0[0-9a-f]+ <[^>]+> 2c521b13         vmovcs  r1, r2, d3
14
0[0-9a-f]+ <[^>]+> 3c421b14         vmovcc  d4, r1, r2

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.