OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [gnu-stable/] [binutils-2.20.1/] [gas/] [testsuite/] [gas/] [arm/] [wince.d] - Blame information for rev 818

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 205 julius
#objdump: -dr --prefix-addresses --show-raw-insn
2
#name: ARM WinCE basic tests
3
#as: -mcpu=arm7m -EL
4
#source: wince.s
5
#not-skip: *-wince-*
6
 
7
# Some WinCE specific tests.
8
 
9
.*: +file format .*arm.*
10
 
11
Disassembly of section .text:
12
0+000  00000007         andeq   r0, r0, r7
13
                        0: ARM_32       global_data
14
0+004  e1a00000         nop                     ; \(mov r0, r0\)
15
0+008  e1a00000         nop                     ; \(mov r0, r0\)
16
0+000c  e1a00000        nop                     ; \(mov r0, r0\)
17
0+010  eafffffb         b       f+ff8 
18
                        10: ARM_26D     global_sym\+0xf+ffc
19
0+018  ebfffffa         bl      f+ff4 
20
                        14: ARM_26D     global_sym\+0xf+ffc
21
0+01c  0afffff9         beq     f+ff0 
22
                        18: ARM_26D     global_sym\+0xf+ffc
23
0+020  eafffff8         b       0+008 
24
0+024  ebfffff7         bl      0+008 
25
0+028  0afffff6         beq     0+008 
26
0+02c  eafffff5         b       0+008 
27
0+030  ebfffff4         bl      0+008 
28
0+034  e51f0034         ldr     r0, \[pc, #-52\]        ; 0+008 
29
0+038  e51f0038         ldr     r0, \[pc, #-56\]        ; 0+008 
30
0+03c  e51f003c         ldr     r0, \[pc, #-60\]        ; 0+008 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.