OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [gnu-stable/] [binutils-2.20.1/] [gas/] [testsuite/] [gas/] [i386/] [x86-64-crc32.d] - Blame information for rev 818

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 205 julius
#objdump: -dw
2
#name: x86-64 crc32
3
 
4
.*:     file format .*
5
 
6
Disassembly of section .text:
7
 
8
0+ :
9
[       ]*[a-f0-9]+:    f2 0f 38 f0 06          crc32b \(%rsi\),%eax
10
[       ]*[a-f0-9]+:    f2 48 0f 38 f0 06       crc32b \(%rsi\),%rax
11
[       ]*[a-f0-9]+:    66 f2 0f 38 f1 06       crc32w \(%rsi\),%eax
12
[       ]*[a-f0-9]+:    f2 0f 38 f1 06          crc32l \(%rsi\),%eax
13
[       ]*[a-f0-9]+:    f2 48 0f 38 f1 06       crc32q \(%rsi\),%rax
14
[       ]*[a-f0-9]+:    f2 0f 38 f0 c0          crc32b %al,%eax
15
[       ]*[a-f0-9]+:    f2 0f 38 f0 c0          crc32b %al,%eax
16
[       ]*[a-f0-9]+:    f2 48 0f 38 f0 c0       crc32b %al,%rax
17
[       ]*[a-f0-9]+:    f2 48 0f 38 f0 c0       crc32b %al,%rax
18
[       ]*[a-f0-9]+:    66 f2 0f 38 f1 c0       crc32w %ax,%eax
19
[       ]*[a-f0-9]+:    66 f2 0f 38 f1 c0       crc32w %ax,%eax
20
[       ]*[a-f0-9]+:    f2 0f 38 f1 c0          crc32l %eax,%eax
21
[       ]*[a-f0-9]+:    f2 0f 38 f1 c0          crc32l %eax,%eax
22
[       ]*[a-f0-9]+:    f2 48 0f 38 f1 c0       crc32q %rax,%rax
23
[       ]*[a-f0-9]+:    f2 48 0f 38 f1 c0       crc32q %rax,%rax
24
[       ]*[a-f0-9]+:    f2 48 0f 38 f0 06       crc32b \(%rsi\),%rax
25
[       ]*[a-f0-9]+:    f2 0f 38 f0 06          crc32b \(%rsi\),%eax
26
[       ]*[a-f0-9]+:    66 f2 0f 38 f1 06       crc32w \(%rsi\),%eax
27
[       ]*[a-f0-9]+:    f2 0f 38 f1 06          crc32l \(%rsi\),%eax
28
[       ]*[a-f0-9]+:    f2 48 0f 38 f1 06       crc32q \(%rsi\),%rax
29
[       ]*[a-f0-9]+:    f2 0f 38 f0 c0          crc32b %al,%eax
30
[       ]*[a-f0-9]+:    f2 48 0f 38 f0 c0       crc32b %al,%rax
31
[       ]*[a-f0-9]+:    66 f2 0f 38 f1 c0       crc32w %ax,%eax
32
[       ]*[a-f0-9]+:    f2 0f 38 f1 c0          crc32l %eax,%eax
33
[       ]*[a-f0-9]+:    f2 48 0f 38 f1 c0       crc32q %rax,%rax
34
#pass

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.