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[/] [openrisc/] [trunk/] [gnu-stable/] [gcc-4.5.1/] [gcc/] [config/] [ia64/] [sync.md] - Blame information for rev 826

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1 282 jeremybenn
;; GCC machine description for IA-64 synchronization instructions.
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;; Copyright (C) 2005, 2007, 2008, 2009, 2010
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;; Free Software Foundation, Inc.
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;;
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;; This file is part of GCC.
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;;
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;; GCC is free software; you can redistribute it and/or modify
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;; it under the terms of the GNU General Public License as published by
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;; the Free Software Foundation; either version 3, or (at your option)
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;; any later version.
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;;
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;; GCC is distributed in the hope that it will be useful,
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;; but WITHOUT ANY WARRANTY; without even the implied warranty of
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;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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;; GNU General Public License for more details.
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;;
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;; You should have received a copy of the GNU General Public License
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;; along with GCC; see the file COPYING3.  If not see
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;; .
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(define_mode_iterator IMODE [QI HI SI DI])
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(define_mode_iterator I124MODE [QI HI SI])
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(define_mode_iterator I48MODE [SI DI])
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(define_mode_attr modesuffix [(QI "1") (HI "2") (SI "4") (DI "8")])
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(define_code_iterator FETCHOP [plus minus ior xor and])
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(define_code_attr fetchop_name
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  [(plus "add") (minus "sub") (ior "ior") (xor "xor") (and "and")])
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(define_expand "memory_barrier"
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  [(set (match_dup 0)
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        (unspec:BLK [(match_dup 0)] UNSPEC_MF))]
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  ""
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{
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  operands[0] = gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (Pmode));
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  MEM_VOLATILE_P (operands[0]) = 1;
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})
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(define_insn "*memory_barrier"
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  [(set (match_operand:BLK 0 "" "")
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        (unspec:BLK [(match_dup 0)] UNSPEC_MF))]
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  ""
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  "mf"
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  [(set_attr "itanium_class" "syst_m")])
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(define_insn "fetchadd_acq_"
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  [(set (match_operand:I48MODE 0 "gr_register_operand" "=r")
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        (match_operand:I48MODE 1 "not_postinc_memory_operand" "+S"))
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   (set (match_dup 1)
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        (unspec:I48MODE [(match_dup 1)
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                         (match_operand:I48MODE 2 "fetchadd_operand" "n")]
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                        UNSPEC_FETCHADD_ACQ))]
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  ""
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  "fetchadd.acq %0 = %1, %2"
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  [(set_attr "itanium_class" "sem")])
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(define_expand "sync_"
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  [(set (match_operand:IMODE 0 "memory_operand" "")
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        (FETCHOP:IMODE (match_dup 0)
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          (match_operand:IMODE 1 "general_operand" "")))]
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  ""
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{
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  ia64_expand_atomic_op (, operands[0], operands[1], NULL, NULL);
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  DONE;
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})
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(define_expand "sync_nand"
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  [(set (match_operand:IMODE 0 "memory_operand" "")
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        (not:IMODE
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          (and:IMODE (match_dup 0)
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                     (match_operand:IMODE 1 "general_operand" ""))))]
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  ""
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{
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  ia64_expand_atomic_op (NOT, operands[0], operands[1], NULL, NULL);
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  DONE;
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})
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(define_expand "sync_old_"
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  [(set (match_operand:IMODE 0 "gr_register_operand" "")
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        (FETCHOP:IMODE
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          (match_operand:IMODE 1 "memory_operand" "")
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          (match_operand:IMODE 2 "general_operand" "")))]
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  ""
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{
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  ia64_expand_atomic_op (, operands[1], operands[2], operands[0], NULL);
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  DONE;
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})
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(define_expand "sync_old_nand"
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  [(set (match_operand:IMODE 0 "gr_register_operand" "")
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        (not:IMODE
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          (and:IMODE (match_operand:IMODE 1 "memory_operand" "")
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                     (match_operand:IMODE 2 "general_operand" ""))))]
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  ""
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{
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  ia64_expand_atomic_op (NOT, operands[1], operands[2], operands[0], NULL);
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  DONE;
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})
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(define_expand "sync_new_"
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  [(set (match_operand:IMODE 0 "gr_register_operand" "")
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        (FETCHOP:IMODE
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          (match_operand:IMODE 1 "memory_operand" "")
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          (match_operand:IMODE 2 "general_operand" "")))]
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  ""
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{
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  ia64_expand_atomic_op (, operands[1], operands[2], NULL, operands[0]);
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  DONE;
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})
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(define_expand "sync_new_nand"
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  [(set (match_operand:IMODE 0 "gr_register_operand" "")
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        (not:IMODE
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          (and:IMODE (match_operand:IMODE 1 "memory_operand" "")
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                     (match_operand:IMODE 2 "general_operand" ""))))]
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  ""
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{
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  ia64_expand_atomic_op (NOT, operands[1], operands[2], NULL, operands[0]);
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  DONE;
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})
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(define_expand "sync_compare_and_swap"
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  [(match_operand:IMODE 0 "gr_register_operand" "")
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   (match_operand:IMODE 1 "memory_operand" "")
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   (match_operand:IMODE 2 "gr_register_operand" "")
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   (match_operand:IMODE 3 "gr_register_operand" "")]
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  ""
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{
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  rtx ccv = gen_rtx_REG (DImode, AR_CCV_REGNUM);
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  rtx dst;
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  convert_move (ccv, operands[2], 1);
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  dst = operands[0];
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  if (GET_MODE (dst) != DImode)
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    dst = gen_reg_rtx (DImode);
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  emit_insn (gen_cmpxchg_rel_ (dst, operands[1], ccv, operands[3]));
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  emit_insn (gen_memory_barrier ());
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  if (dst != operands[0])
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    emit_move_insn (operands[0], gen_lowpart (mode, dst));
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  DONE;
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})
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(define_insn "cmpxchg_rel_"
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  [(set (match_operand:DI 0 "gr_register_operand" "=r")
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        (zero_extend:DI
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          (match_operand:I124MODE 1 "not_postinc_memory_operand" "+S")))
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   (set (match_dup 1)
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        (unspec:I124MODE
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          [(match_dup 1)
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           (match_operand:DI 2 "ar_ccv_reg_operand" "")
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           (match_operand:I124MODE 3 "gr_reg_or_0_operand" "rO")]
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          UNSPEC_CMPXCHG_ACQ))]
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  ""
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  "cmpxchg.rel %0 = %1, %r3, %2"
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  [(set_attr "itanium_class" "sem")])
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(define_insn "cmpxchg_rel_di"
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  [(set (match_operand:DI 0 "gr_register_operand" "=r")
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        (match_operand:DI 1 "not_postinc_memory_operand" "+S"))
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   (set (match_dup 1)
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        (unspec:DI [(match_dup 1)
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                    (match_operand:DI 2 "ar_ccv_reg_operand" "")
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                    (match_operand:DI 3 "gr_reg_or_0_operand" "rO")]
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                   UNSPEC_CMPXCHG_ACQ))]
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  ""
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  "cmpxchg8.rel %0 = %1, %r3, %2"
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  [(set_attr "itanium_class" "sem")])
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(define_insn "sync_lock_test_and_set"
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  [(set (match_operand:IMODE 0 "gr_register_operand" "=r")
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        (match_operand:IMODE 1 "not_postinc_memory_operand" "+S"))
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   (set (match_dup 1)
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        (match_operand:IMODE 2 "gr_reg_or_0_operand" "rO"))]
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  ""
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  "xchg %0 = %1, %r2"
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  [(set_attr "itanium_class" "sem")])
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(define_expand "sync_lock_release"
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  [(set (match_operand:IMODE 0 "memory_operand" "")
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        (match_operand:IMODE 1 "gr_reg_or_0_operand" ""))]
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  ""
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{
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  gcc_assert (MEM_VOLATILE_P (operands[0]));
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})

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