OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [gnu-stable/] [gcc-4.5.1/] [gcc/] [doc/] [arm-neon-intrinsics.texi] - Blame information for rev 856

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 284 jeremybenn
@c Copyright (C) 2006 Free Software Foundation, Inc.
2
@c This is part of the GCC manual.
3
@c For copying conditions, see the file gcc.texi.
4
 
5
@c This file is generated automatically using gcc/config/arm/neon-docgen.ml
6
@c Please do not edit manually.
7
@subsubsection Addition
8
 
9
@itemize @bullet
10
@item uint32x2_t vadd_u32 (uint32x2_t, uint32x2_t)
11
@*@emph{Form of expected instruction(s):} @code{vadd.i32 @var{d0}, @var{d0}, @var{d0}}
12
@end itemize
13
 
14
 
15
@itemize @bullet
16
@item uint16x4_t vadd_u16 (uint16x4_t, uint16x4_t)
17
@*@emph{Form of expected instruction(s):} @code{vadd.i16 @var{d0}, @var{d0}, @var{d0}}
18
@end itemize
19
 
20
 
21
@itemize @bullet
22
@item uint8x8_t vadd_u8 (uint8x8_t, uint8x8_t)
23
@*@emph{Form of expected instruction(s):} @code{vadd.i8 @var{d0}, @var{d0}, @var{d0}}
24
@end itemize
25
 
26
 
27
@itemize @bullet
28
@item int32x2_t vadd_s32 (int32x2_t, int32x2_t)
29
@*@emph{Form of expected instruction(s):} @code{vadd.i32 @var{d0}, @var{d0}, @var{d0}}
30
@end itemize
31
 
32
 
33
@itemize @bullet
34
@item int16x4_t vadd_s16 (int16x4_t, int16x4_t)
35
@*@emph{Form of expected instruction(s):} @code{vadd.i16 @var{d0}, @var{d0}, @var{d0}}
36
@end itemize
37
 
38
 
39
@itemize @bullet
40
@item int8x8_t vadd_s8 (int8x8_t, int8x8_t)
41
@*@emph{Form of expected instruction(s):} @code{vadd.i8 @var{d0}, @var{d0}, @var{d0}}
42
@end itemize
43
 
44
 
45
@itemize @bullet
46
@item uint64x1_t vadd_u64 (uint64x1_t, uint64x1_t)
47
@*@emph{Form of expected instruction(s):} @code{vadd.i64 @var{d0}, @var{d0}, @var{d0}}
48
@end itemize
49
 
50
 
51
@itemize @bullet
52
@item int64x1_t vadd_s64 (int64x1_t, int64x1_t)
53
@*@emph{Form of expected instruction(s):} @code{vadd.i64 @var{d0}, @var{d0}, @var{d0}}
54
@end itemize
55
 
56
 
57
@itemize @bullet
58
@item float32x2_t vadd_f32 (float32x2_t, float32x2_t)
59
@*@emph{Form of expected instruction(s):} @code{vadd.f32 @var{d0}, @var{d0}, @var{d0}}
60
@end itemize
61
 
62
 
63
@itemize @bullet
64
@item uint32x4_t vaddq_u32 (uint32x4_t, uint32x4_t)
65
@*@emph{Form of expected instruction(s):} @code{vadd.i32 @var{q0}, @var{q0}, @var{q0}}
66
@end itemize
67
 
68
 
69
@itemize @bullet
70
@item uint16x8_t vaddq_u16 (uint16x8_t, uint16x8_t)
71
@*@emph{Form of expected instruction(s):} @code{vadd.i16 @var{q0}, @var{q0}, @var{q0}}
72
@end itemize
73
 
74
 
75
@itemize @bullet
76
@item uint8x16_t vaddq_u8 (uint8x16_t, uint8x16_t)
77
@*@emph{Form of expected instruction(s):} @code{vadd.i8 @var{q0}, @var{q0}, @var{q0}}
78
@end itemize
79
 
80
 
81
@itemize @bullet
82
@item int32x4_t vaddq_s32 (int32x4_t, int32x4_t)
83
@*@emph{Form of expected instruction(s):} @code{vadd.i32 @var{q0}, @var{q0}, @var{q0}}
84
@end itemize
85
 
86
 
87
@itemize @bullet
88
@item int16x8_t vaddq_s16 (int16x8_t, int16x8_t)
89
@*@emph{Form of expected instruction(s):} @code{vadd.i16 @var{q0}, @var{q0}, @var{q0}}
90
@end itemize
91
 
92
 
93
@itemize @bullet
94
@item int8x16_t vaddq_s8 (int8x16_t, int8x16_t)
95
@*@emph{Form of expected instruction(s):} @code{vadd.i8 @var{q0}, @var{q0}, @var{q0}}
96
@end itemize
97
 
98
 
99
@itemize @bullet
100
@item uint64x2_t vaddq_u64 (uint64x2_t, uint64x2_t)
101
@*@emph{Form of expected instruction(s):} @code{vadd.i64 @var{q0}, @var{q0}, @var{q0}}
102
@end itemize
103
 
104
 
105
@itemize @bullet
106
@item int64x2_t vaddq_s64 (int64x2_t, int64x2_t)
107
@*@emph{Form of expected instruction(s):} @code{vadd.i64 @var{q0}, @var{q0}, @var{q0}}
108
@end itemize
109
 
110
 
111
@itemize @bullet
112
@item float32x4_t vaddq_f32 (float32x4_t, float32x4_t)
113
@*@emph{Form of expected instruction(s):} @code{vadd.f32 @var{q0}, @var{q0}, @var{q0}}
114
@end itemize
115
 
116
 
117
@itemize @bullet
118
@item uint64x2_t vaddl_u32 (uint32x2_t, uint32x2_t)
119
@*@emph{Form of expected instruction(s):} @code{vaddl.u32 @var{q0}, @var{d0}, @var{d0}}
120
@end itemize
121
 
122
 
123
@itemize @bullet
124
@item uint32x4_t vaddl_u16 (uint16x4_t, uint16x4_t)
125
@*@emph{Form of expected instruction(s):} @code{vaddl.u16 @var{q0}, @var{d0}, @var{d0}}
126
@end itemize
127
 
128
 
129
@itemize @bullet
130
@item uint16x8_t vaddl_u8 (uint8x8_t, uint8x8_t)
131
@*@emph{Form of expected instruction(s):} @code{vaddl.u8 @var{q0}, @var{d0}, @var{d0}}
132
@end itemize
133
 
134
 
135
@itemize @bullet
136
@item int64x2_t vaddl_s32 (int32x2_t, int32x2_t)
137
@*@emph{Form of expected instruction(s):} @code{vaddl.s32 @var{q0}, @var{d0}, @var{d0}}
138
@end itemize
139
 
140
 
141
@itemize @bullet
142
@item int32x4_t vaddl_s16 (int16x4_t, int16x4_t)
143
@*@emph{Form of expected instruction(s):} @code{vaddl.s16 @var{q0}, @var{d0}, @var{d0}}
144
@end itemize
145
 
146
 
147
@itemize @bullet
148
@item int16x8_t vaddl_s8 (int8x8_t, int8x8_t)
149
@*@emph{Form of expected instruction(s):} @code{vaddl.s8 @var{q0}, @var{d0}, @var{d0}}
150
@end itemize
151
 
152
 
153
@itemize @bullet
154
@item uint64x2_t vaddw_u32 (uint64x2_t, uint32x2_t)
155
@*@emph{Form of expected instruction(s):} @code{vaddw.u32 @var{q0}, @var{q0}, @var{d0}}
156
@end itemize
157
 
158
 
159
@itemize @bullet
160
@item uint32x4_t vaddw_u16 (uint32x4_t, uint16x4_t)
161
@*@emph{Form of expected instruction(s):} @code{vaddw.u16 @var{q0}, @var{q0}, @var{d0}}
162
@end itemize
163
 
164
 
165
@itemize @bullet
166
@item uint16x8_t vaddw_u8 (uint16x8_t, uint8x8_t)
167
@*@emph{Form of expected instruction(s):} @code{vaddw.u8 @var{q0}, @var{q0}, @var{d0}}
168
@end itemize
169
 
170
 
171
@itemize @bullet
172
@item int64x2_t vaddw_s32 (int64x2_t, int32x2_t)
173
@*@emph{Form of expected instruction(s):} @code{vaddw.s32 @var{q0}, @var{q0}, @var{d0}}
174
@end itemize
175
 
176
 
177
@itemize @bullet
178
@item int32x4_t vaddw_s16 (int32x4_t, int16x4_t)
179
@*@emph{Form of expected instruction(s):} @code{vaddw.s16 @var{q0}, @var{q0}, @var{d0}}
180
@end itemize
181
 
182
 
183
@itemize @bullet
184
@item int16x8_t vaddw_s8 (int16x8_t, int8x8_t)
185
@*@emph{Form of expected instruction(s):} @code{vaddw.s8 @var{q0}, @var{q0}, @var{d0}}
186
@end itemize
187
 
188
 
189
@itemize @bullet
190
@item uint32x2_t vhadd_u32 (uint32x2_t, uint32x2_t)
191
@*@emph{Form of expected instruction(s):} @code{vhadd.u32 @var{d0}, @var{d0}, @var{d0}}
192
@end itemize
193
 
194
 
195
@itemize @bullet
196
@item uint16x4_t vhadd_u16 (uint16x4_t, uint16x4_t)
197
@*@emph{Form of expected instruction(s):} @code{vhadd.u16 @var{d0}, @var{d0}, @var{d0}}
198
@end itemize
199
 
200
 
201
@itemize @bullet
202
@item uint8x8_t vhadd_u8 (uint8x8_t, uint8x8_t)
203
@*@emph{Form of expected instruction(s):} @code{vhadd.u8 @var{d0}, @var{d0}, @var{d0}}
204
@end itemize
205
 
206
 
207
@itemize @bullet
208
@item int32x2_t vhadd_s32 (int32x2_t, int32x2_t)
209
@*@emph{Form of expected instruction(s):} @code{vhadd.s32 @var{d0}, @var{d0}, @var{d0}}
210
@end itemize
211
 
212
 
213
@itemize @bullet
214
@item int16x4_t vhadd_s16 (int16x4_t, int16x4_t)
215
@*@emph{Form of expected instruction(s):} @code{vhadd.s16 @var{d0}, @var{d0}, @var{d0}}
216
@end itemize
217
 
218
 
219
@itemize @bullet
220
@item int8x8_t vhadd_s8 (int8x8_t, int8x8_t)
221
@*@emph{Form of expected instruction(s):} @code{vhadd.s8 @var{d0}, @var{d0}, @var{d0}}
222
@end itemize
223
 
224
 
225
@itemize @bullet
226
@item uint32x4_t vhaddq_u32 (uint32x4_t, uint32x4_t)
227
@*@emph{Form of expected instruction(s):} @code{vhadd.u32 @var{q0}, @var{q0}, @var{q0}}
228
@end itemize
229
 
230
 
231
@itemize @bullet
232
@item uint16x8_t vhaddq_u16 (uint16x8_t, uint16x8_t)
233
@*@emph{Form of expected instruction(s):} @code{vhadd.u16 @var{q0}, @var{q0}, @var{q0}}
234
@end itemize
235
 
236
 
237
@itemize @bullet
238
@item uint8x16_t vhaddq_u8 (uint8x16_t, uint8x16_t)
239
@*@emph{Form of expected instruction(s):} @code{vhadd.u8 @var{q0}, @var{q0}, @var{q0}}
240
@end itemize
241
 
242
 
243
@itemize @bullet
244
@item int32x4_t vhaddq_s32 (int32x4_t, int32x4_t)
245
@*@emph{Form of expected instruction(s):} @code{vhadd.s32 @var{q0}, @var{q0}, @var{q0}}
246
@end itemize
247
 
248
 
249
@itemize @bullet
250
@item int16x8_t vhaddq_s16 (int16x8_t, int16x8_t)
251
@*@emph{Form of expected instruction(s):} @code{vhadd.s16 @var{q0}, @var{q0}, @var{q0}}
252
@end itemize
253
 
254
 
255
@itemize @bullet
256
@item int8x16_t vhaddq_s8 (int8x16_t, int8x16_t)
257
@*@emph{Form of expected instruction(s):} @code{vhadd.s8 @var{q0}, @var{q0}, @var{q0}}
258
@end itemize
259
 
260
 
261
@itemize @bullet
262
@item uint32x2_t vrhadd_u32 (uint32x2_t, uint32x2_t)
263
@*@emph{Form of expected instruction(s):} @code{vrhadd.u32 @var{d0}, @var{d0}, @var{d0}}
264
@end itemize
265
 
266
 
267
@itemize @bullet
268
@item uint16x4_t vrhadd_u16 (uint16x4_t, uint16x4_t)
269
@*@emph{Form of expected instruction(s):} @code{vrhadd.u16 @var{d0}, @var{d0}, @var{d0}}
270
@end itemize
271
 
272
 
273
@itemize @bullet
274
@item uint8x8_t vrhadd_u8 (uint8x8_t, uint8x8_t)
275
@*@emph{Form of expected instruction(s):} @code{vrhadd.u8 @var{d0}, @var{d0}, @var{d0}}
276
@end itemize
277
 
278
 
279
@itemize @bullet
280
@item int32x2_t vrhadd_s32 (int32x2_t, int32x2_t)
281
@*@emph{Form of expected instruction(s):} @code{vrhadd.s32 @var{d0}, @var{d0}, @var{d0}}
282
@end itemize
283
 
284
 
285
@itemize @bullet
286
@item int16x4_t vrhadd_s16 (int16x4_t, int16x4_t)
287
@*@emph{Form of expected instruction(s):} @code{vrhadd.s16 @var{d0}, @var{d0}, @var{d0}}
288
@end itemize
289
 
290
 
291
@itemize @bullet
292
@item int8x8_t vrhadd_s8 (int8x8_t, int8x8_t)
293
@*@emph{Form of expected instruction(s):} @code{vrhadd.s8 @var{d0}, @var{d0}, @var{d0}}
294
@end itemize
295
 
296
 
297
@itemize @bullet
298
@item uint32x4_t vrhaddq_u32 (uint32x4_t, uint32x4_t)
299
@*@emph{Form of expected instruction(s):} @code{vrhadd.u32 @var{q0}, @var{q0}, @var{q0}}
300
@end itemize
301
 
302
 
303
@itemize @bullet
304
@item uint16x8_t vrhaddq_u16 (uint16x8_t, uint16x8_t)
305
@*@emph{Form of expected instruction(s):} @code{vrhadd.u16 @var{q0}, @var{q0}, @var{q0}}
306
@end itemize
307
 
308
 
309
@itemize @bullet
310
@item uint8x16_t vrhaddq_u8 (uint8x16_t, uint8x16_t)
311
@*@emph{Form of expected instruction(s):} @code{vrhadd.u8 @var{q0}, @var{q0}, @var{q0}}
312
@end itemize
313
 
314
 
315
@itemize @bullet
316
@item int32x4_t vrhaddq_s32 (int32x4_t, int32x4_t)
317
@*@emph{Form of expected instruction(s):} @code{vrhadd.s32 @var{q0}, @var{q0}, @var{q0}}
318
@end itemize
319
 
320
 
321
@itemize @bullet
322
@item int16x8_t vrhaddq_s16 (int16x8_t, int16x8_t)
323
@*@emph{Form of expected instruction(s):} @code{vrhadd.s16 @var{q0}, @var{q0}, @var{q0}}
324
@end itemize
325
 
326
 
327
@itemize @bullet
328
@item int8x16_t vrhaddq_s8 (int8x16_t, int8x16_t)
329
@*@emph{Form of expected instruction(s):} @code{vrhadd.s8 @var{q0}, @var{q0}, @var{q0}}
330
@end itemize
331
 
332
 
333
@itemize @bullet
334
@item uint32x2_t vqadd_u32 (uint32x2_t, uint32x2_t)
335
@*@emph{Form of expected instruction(s):} @code{vqadd.u32 @var{d0}, @var{d0}, @var{d0}}
336
@end itemize
337
 
338
 
339
@itemize @bullet
340
@item uint16x4_t vqadd_u16 (uint16x4_t, uint16x4_t)
341
@*@emph{Form of expected instruction(s):} @code{vqadd.u16 @var{d0}, @var{d0}, @var{d0}}
342
@end itemize
343
 
344
 
345
@itemize @bullet
346
@item uint8x8_t vqadd_u8 (uint8x8_t, uint8x8_t)
347
@*@emph{Form of expected instruction(s):} @code{vqadd.u8 @var{d0}, @var{d0}, @var{d0}}
348
@end itemize
349
 
350
 
351
@itemize @bullet
352
@item int32x2_t vqadd_s32 (int32x2_t, int32x2_t)
353
@*@emph{Form of expected instruction(s):} @code{vqadd.s32 @var{d0}, @var{d0}, @var{d0}}
354
@end itemize
355
 
356
 
357
@itemize @bullet
358
@item int16x4_t vqadd_s16 (int16x4_t, int16x4_t)
359
@*@emph{Form of expected instruction(s):} @code{vqadd.s16 @var{d0}, @var{d0}, @var{d0}}
360
@end itemize
361
 
362
 
363
@itemize @bullet
364
@item int8x8_t vqadd_s8 (int8x8_t, int8x8_t)
365
@*@emph{Form of expected instruction(s):} @code{vqadd.s8 @var{d0}, @var{d0}, @var{d0}}
366
@end itemize
367
 
368
 
369
@itemize @bullet
370
@item uint64x1_t vqadd_u64 (uint64x1_t, uint64x1_t)
371
@*@emph{Form of expected instruction(s):} @code{vqadd.u64 @var{d0}, @var{d0}, @var{d0}}
372
@end itemize
373
 
374
 
375
@itemize @bullet
376
@item int64x1_t vqadd_s64 (int64x1_t, int64x1_t)
377
@*@emph{Form of expected instruction(s):} @code{vqadd.s64 @var{d0}, @var{d0}, @var{d0}}
378
@end itemize
379
 
380
 
381
@itemize @bullet
382
@item uint32x4_t vqaddq_u32 (uint32x4_t, uint32x4_t)
383
@*@emph{Form of expected instruction(s):} @code{vqadd.u32 @var{q0}, @var{q0}, @var{q0}}
384
@end itemize
385
 
386
 
387
@itemize @bullet
388
@item uint16x8_t vqaddq_u16 (uint16x8_t, uint16x8_t)
389
@*@emph{Form of expected instruction(s):} @code{vqadd.u16 @var{q0}, @var{q0}, @var{q0}}
390
@end itemize
391
 
392
 
393
@itemize @bullet
394
@item uint8x16_t vqaddq_u8 (uint8x16_t, uint8x16_t)
395
@*@emph{Form of expected instruction(s):} @code{vqadd.u8 @var{q0}, @var{q0}, @var{q0}}
396
@end itemize
397
 
398
 
399
@itemize @bullet
400
@item int32x4_t vqaddq_s32 (int32x4_t, int32x4_t)
401
@*@emph{Form of expected instruction(s):} @code{vqadd.s32 @var{q0}, @var{q0}, @var{q0}}
402
@end itemize
403
 
404
 
405
@itemize @bullet
406
@item int16x8_t vqaddq_s16 (int16x8_t, int16x8_t)
407
@*@emph{Form of expected instruction(s):} @code{vqadd.s16 @var{q0}, @var{q0}, @var{q0}}
408
@end itemize
409
 
410
 
411
@itemize @bullet
412
@item int8x16_t vqaddq_s8 (int8x16_t, int8x16_t)
413
@*@emph{Form of expected instruction(s):} @code{vqadd.s8 @var{q0}, @var{q0}, @var{q0}}
414
@end itemize
415
 
416
 
417
@itemize @bullet
418
@item uint64x2_t vqaddq_u64 (uint64x2_t, uint64x2_t)
419
@*@emph{Form of expected instruction(s):} @code{vqadd.u64 @var{q0}, @var{q0}, @var{q0}}
420
@end itemize
421
 
422
 
423
@itemize @bullet
424
@item int64x2_t vqaddq_s64 (int64x2_t, int64x2_t)
425
@*@emph{Form of expected instruction(s):} @code{vqadd.s64 @var{q0}, @var{q0}, @var{q0}}
426
@end itemize
427
 
428
 
429
@itemize @bullet
430
@item uint32x2_t vaddhn_u64 (uint64x2_t, uint64x2_t)
431
@*@emph{Form of expected instruction(s):} @code{vaddhn.i64 @var{d0}, @var{q0}, @var{q0}}
432
@end itemize
433
 
434
 
435
@itemize @bullet
436
@item uint16x4_t vaddhn_u32 (uint32x4_t, uint32x4_t)
437
@*@emph{Form of expected instruction(s):} @code{vaddhn.i32 @var{d0}, @var{q0}, @var{q0}}
438
@end itemize
439
 
440
 
441
@itemize @bullet
442
@item uint8x8_t vaddhn_u16 (uint16x8_t, uint16x8_t)
443
@*@emph{Form of expected instruction(s):} @code{vaddhn.i16 @var{d0}, @var{q0}, @var{q0}}
444
@end itemize
445
 
446
 
447
@itemize @bullet
448
@item int32x2_t vaddhn_s64 (int64x2_t, int64x2_t)
449
@*@emph{Form of expected instruction(s):} @code{vaddhn.i64 @var{d0}, @var{q0}, @var{q0}}
450
@end itemize
451
 
452
 
453
@itemize @bullet
454
@item int16x4_t vaddhn_s32 (int32x4_t, int32x4_t)
455
@*@emph{Form of expected instruction(s):} @code{vaddhn.i32 @var{d0}, @var{q0}, @var{q0}}
456
@end itemize
457
 
458
 
459
@itemize @bullet
460
@item int8x8_t vaddhn_s16 (int16x8_t, int16x8_t)
461
@*@emph{Form of expected instruction(s):} @code{vaddhn.i16 @var{d0}, @var{q0}, @var{q0}}
462
@end itemize
463
 
464
 
465
@itemize @bullet
466
@item uint32x2_t vraddhn_u64 (uint64x2_t, uint64x2_t)
467
@*@emph{Form of expected instruction(s):} @code{vraddhn.i64 @var{d0}, @var{q0}, @var{q0}}
468
@end itemize
469
 
470
 
471
@itemize @bullet
472
@item uint16x4_t vraddhn_u32 (uint32x4_t, uint32x4_t)
473
@*@emph{Form of expected instruction(s):} @code{vraddhn.i32 @var{d0}, @var{q0}, @var{q0}}
474
@end itemize
475
 
476
 
477
@itemize @bullet
478
@item uint8x8_t vraddhn_u16 (uint16x8_t, uint16x8_t)
479
@*@emph{Form of expected instruction(s):} @code{vraddhn.i16 @var{d0}, @var{q0}, @var{q0}}
480
@end itemize
481
 
482
 
483
@itemize @bullet
484
@item int32x2_t vraddhn_s64 (int64x2_t, int64x2_t)
485
@*@emph{Form of expected instruction(s):} @code{vraddhn.i64 @var{d0}, @var{q0}, @var{q0}}
486
@end itemize
487
 
488
 
489
@itemize @bullet
490
@item int16x4_t vraddhn_s32 (int32x4_t, int32x4_t)
491
@*@emph{Form of expected instruction(s):} @code{vraddhn.i32 @var{d0}, @var{q0}, @var{q0}}
492
@end itemize
493
 
494
 
495
@itemize @bullet
496
@item int8x8_t vraddhn_s16 (int16x8_t, int16x8_t)
497
@*@emph{Form of expected instruction(s):} @code{vraddhn.i16 @var{d0}, @var{q0}, @var{q0}}
498
@end itemize
499
 
500
 
501
 
502
 
503
@subsubsection Multiplication
504
 
505
@itemize @bullet
506
@item uint32x2_t vmul_u32 (uint32x2_t, uint32x2_t)
507
@*@emph{Form of expected instruction(s):} @code{vmul.i32 @var{d0}, @var{d0}, @var{d0}}
508
@end itemize
509
 
510
 
511
@itemize @bullet
512
@item uint16x4_t vmul_u16 (uint16x4_t, uint16x4_t)
513
@*@emph{Form of expected instruction(s):} @code{vmul.i16 @var{d0}, @var{d0}, @var{d0}}
514
@end itemize
515
 
516
 
517
@itemize @bullet
518
@item uint8x8_t vmul_u8 (uint8x8_t, uint8x8_t)
519
@*@emph{Form of expected instruction(s):} @code{vmul.i8 @var{d0}, @var{d0}, @var{d0}}
520
@end itemize
521
 
522
 
523
@itemize @bullet
524
@item int32x2_t vmul_s32 (int32x2_t, int32x2_t)
525
@*@emph{Form of expected instruction(s):} @code{vmul.i32 @var{d0}, @var{d0}, @var{d0}}
526
@end itemize
527
 
528
 
529
@itemize @bullet
530
@item int16x4_t vmul_s16 (int16x4_t, int16x4_t)
531
@*@emph{Form of expected instruction(s):} @code{vmul.i16 @var{d0}, @var{d0}, @var{d0}}
532
@end itemize
533
 
534
 
535
@itemize @bullet
536
@item int8x8_t vmul_s8 (int8x8_t, int8x8_t)
537
@*@emph{Form of expected instruction(s):} @code{vmul.i8 @var{d0}, @var{d0}, @var{d0}}
538
@end itemize
539
 
540
 
541
@itemize @bullet
542
@item float32x2_t vmul_f32 (float32x2_t, float32x2_t)
543
@*@emph{Form of expected instruction(s):} @code{vmul.f32 @var{d0}, @var{d0}, @var{d0}}
544
@end itemize
545
 
546
 
547
@itemize @bullet
548
@item poly8x8_t vmul_p8 (poly8x8_t, poly8x8_t)
549
@*@emph{Form of expected instruction(s):} @code{vmul.p8 @var{d0}, @var{d0}, @var{d0}}
550
@end itemize
551
 
552
 
553
@itemize @bullet
554
@item uint32x4_t vmulq_u32 (uint32x4_t, uint32x4_t)
555
@*@emph{Form of expected instruction(s):} @code{vmul.i32 @var{q0}, @var{q0}, @var{q0}}
556
@end itemize
557
 
558
 
559
@itemize @bullet
560
@item uint16x8_t vmulq_u16 (uint16x8_t, uint16x8_t)
561
@*@emph{Form of expected instruction(s):} @code{vmul.i16 @var{q0}, @var{q0}, @var{q0}}
562
@end itemize
563
 
564
 
565
@itemize @bullet
566
@item uint8x16_t vmulq_u8 (uint8x16_t, uint8x16_t)
567
@*@emph{Form of expected instruction(s):} @code{vmul.i8 @var{q0}, @var{q0}, @var{q0}}
568
@end itemize
569
 
570
 
571
@itemize @bullet
572
@item int32x4_t vmulq_s32 (int32x4_t, int32x4_t)
573
@*@emph{Form of expected instruction(s):} @code{vmul.i32 @var{q0}, @var{q0}, @var{q0}}
574
@end itemize
575
 
576
 
577
@itemize @bullet
578
@item int16x8_t vmulq_s16 (int16x8_t, int16x8_t)
579
@*@emph{Form of expected instruction(s):} @code{vmul.i16 @var{q0}, @var{q0}, @var{q0}}
580
@end itemize
581
 
582
 
583
@itemize @bullet
584
@item int8x16_t vmulq_s8 (int8x16_t, int8x16_t)
585
@*@emph{Form of expected instruction(s):} @code{vmul.i8 @var{q0}, @var{q0}, @var{q0}}
586
@end itemize
587
 
588
 
589
@itemize @bullet
590
@item float32x4_t vmulq_f32 (float32x4_t, float32x4_t)
591
@*@emph{Form of expected instruction(s):} @code{vmul.f32 @var{q0}, @var{q0}, @var{q0}}
592
@end itemize
593
 
594
 
595
@itemize @bullet
596
@item poly8x16_t vmulq_p8 (poly8x16_t, poly8x16_t)
597
@*@emph{Form of expected instruction(s):} @code{vmul.p8 @var{q0}, @var{q0}, @var{q0}}
598
@end itemize
599
 
600
 
601
@itemize @bullet
602
@item int32x2_t vqdmulh_s32 (int32x2_t, int32x2_t)
603
@*@emph{Form of expected instruction(s):} @code{vqdmulh.s32 @var{d0}, @var{d0}, @var{d0}}
604
@end itemize
605
 
606
 
607
@itemize @bullet
608
@item int16x4_t vqdmulh_s16 (int16x4_t, int16x4_t)
609
@*@emph{Form of expected instruction(s):} @code{vqdmulh.s16 @var{d0}, @var{d0}, @var{d0}}
610
@end itemize
611
 
612
 
613
@itemize @bullet
614
@item int32x4_t vqdmulhq_s32 (int32x4_t, int32x4_t)
615
@*@emph{Form of expected instruction(s):} @code{vqdmulh.s32 @var{q0}, @var{q0}, @var{q0}}
616
@end itemize
617
 
618
 
619
@itemize @bullet
620
@item int16x8_t vqdmulhq_s16 (int16x8_t, int16x8_t)
621
@*@emph{Form of expected instruction(s):} @code{vqdmulh.s16 @var{q0}, @var{q0}, @var{q0}}
622
@end itemize
623
 
624
 
625
@itemize @bullet
626
@item int32x2_t vqrdmulh_s32 (int32x2_t, int32x2_t)
627
@*@emph{Form of expected instruction(s):} @code{vqrdmulh.s32 @var{d0}, @var{d0}, @var{d0}}
628
@end itemize
629
 
630
 
631
@itemize @bullet
632
@item int16x4_t vqrdmulh_s16 (int16x4_t, int16x4_t)
633
@*@emph{Form of expected instruction(s):} @code{vqrdmulh.s16 @var{d0}, @var{d0}, @var{d0}}
634
@end itemize
635
 
636
 
637
@itemize @bullet
638
@item int32x4_t vqrdmulhq_s32 (int32x4_t, int32x4_t)
639
@*@emph{Form of expected instruction(s):} @code{vqrdmulh.s32 @var{q0}, @var{q0}, @var{q0}}
640
@end itemize
641
 
642
 
643
@itemize @bullet
644
@item int16x8_t vqrdmulhq_s16 (int16x8_t, int16x8_t)
645
@*@emph{Form of expected instruction(s):} @code{vqrdmulh.s16 @var{q0}, @var{q0}, @var{q0}}
646
@end itemize
647
 
648
 
649
@itemize @bullet
650
@item uint64x2_t vmull_u32 (uint32x2_t, uint32x2_t)
651
@*@emph{Form of expected instruction(s):} @code{vmull.u32 @var{q0}, @var{d0}, @var{d0}}
652
@end itemize
653
 
654
 
655
@itemize @bullet
656
@item uint32x4_t vmull_u16 (uint16x4_t, uint16x4_t)
657
@*@emph{Form of expected instruction(s):} @code{vmull.u16 @var{q0}, @var{d0}, @var{d0}}
658
@end itemize
659
 
660
 
661
@itemize @bullet
662
@item uint16x8_t vmull_u8 (uint8x8_t, uint8x8_t)
663
@*@emph{Form of expected instruction(s):} @code{vmull.u8 @var{q0}, @var{d0}, @var{d0}}
664
@end itemize
665
 
666
 
667
@itemize @bullet
668
@item int64x2_t vmull_s32 (int32x2_t, int32x2_t)
669
@*@emph{Form of expected instruction(s):} @code{vmull.s32 @var{q0}, @var{d0}, @var{d0}}
670
@end itemize
671
 
672
 
673
@itemize @bullet
674
@item int32x4_t vmull_s16 (int16x4_t, int16x4_t)
675
@*@emph{Form of expected instruction(s):} @code{vmull.s16 @var{q0}, @var{d0}, @var{d0}}
676
@end itemize
677
 
678
 
679
@itemize @bullet
680
@item int16x8_t vmull_s8 (int8x8_t, int8x8_t)
681
@*@emph{Form of expected instruction(s):} @code{vmull.s8 @var{q0}, @var{d0}, @var{d0}}
682
@end itemize
683
 
684
 
685
@itemize @bullet
686
@item poly16x8_t vmull_p8 (poly8x8_t, poly8x8_t)
687
@*@emph{Form of expected instruction(s):} @code{vmull.p8 @var{q0}, @var{d0}, @var{d0}}
688
@end itemize
689
 
690
 
691
@itemize @bullet
692
@item int64x2_t vqdmull_s32 (int32x2_t, int32x2_t)
693
@*@emph{Form of expected instruction(s):} @code{vqdmull.s32 @var{q0}, @var{d0}, @var{d0}}
694
@end itemize
695
 
696
 
697
@itemize @bullet
698
@item int32x4_t vqdmull_s16 (int16x4_t, int16x4_t)
699
@*@emph{Form of expected instruction(s):} @code{vqdmull.s16 @var{q0}, @var{d0}, @var{d0}}
700
@end itemize
701
 
702
 
703
 
704
 
705
@subsubsection Multiply-accumulate
706
 
707
@itemize @bullet
708
@item uint32x2_t vmla_u32 (uint32x2_t, uint32x2_t, uint32x2_t)
709
@*@emph{Form of expected instruction(s):} @code{vmla.i32 @var{d0}, @var{d0}, @var{d0}}
710
@end itemize
711
 
712
 
713
@itemize @bullet
714
@item uint16x4_t vmla_u16 (uint16x4_t, uint16x4_t, uint16x4_t)
715
@*@emph{Form of expected instruction(s):} @code{vmla.i16 @var{d0}, @var{d0}, @var{d0}}
716
@end itemize
717
 
718
 
719
@itemize @bullet
720
@item uint8x8_t vmla_u8 (uint8x8_t, uint8x8_t, uint8x8_t)
721
@*@emph{Form of expected instruction(s):} @code{vmla.i8 @var{d0}, @var{d0}, @var{d0}}
722
@end itemize
723
 
724
 
725
@itemize @bullet
726
@item int32x2_t vmla_s32 (int32x2_t, int32x2_t, int32x2_t)
727
@*@emph{Form of expected instruction(s):} @code{vmla.i32 @var{d0}, @var{d0}, @var{d0}}
728
@end itemize
729
 
730
 
731
@itemize @bullet
732
@item int16x4_t vmla_s16 (int16x4_t, int16x4_t, int16x4_t)
733
@*@emph{Form of expected instruction(s):} @code{vmla.i16 @var{d0}, @var{d0}, @var{d0}}
734
@end itemize
735
 
736
 
737
@itemize @bullet
738
@item int8x8_t vmla_s8 (int8x8_t, int8x8_t, int8x8_t)
739
@*@emph{Form of expected instruction(s):} @code{vmla.i8 @var{d0}, @var{d0}, @var{d0}}
740
@end itemize
741
 
742
 
743
@itemize @bullet
744
@item float32x2_t vmla_f32 (float32x2_t, float32x2_t, float32x2_t)
745
@*@emph{Form of expected instruction(s):} @code{vmla.f32 @var{d0}, @var{d0}, @var{d0}}
746
@end itemize
747
 
748
 
749
@itemize @bullet
750
@item uint32x4_t vmlaq_u32 (uint32x4_t, uint32x4_t, uint32x4_t)
751
@*@emph{Form of expected instruction(s):} @code{vmla.i32 @var{q0}, @var{q0}, @var{q0}}
752
@end itemize
753
 
754
 
755
@itemize @bullet
756
@item uint16x8_t vmlaq_u16 (uint16x8_t, uint16x8_t, uint16x8_t)
757
@*@emph{Form of expected instruction(s):} @code{vmla.i16 @var{q0}, @var{q0}, @var{q0}}
758
@end itemize
759
 
760
 
761
@itemize @bullet
762
@item uint8x16_t vmlaq_u8 (uint8x16_t, uint8x16_t, uint8x16_t)
763
@*@emph{Form of expected instruction(s):} @code{vmla.i8 @var{q0}, @var{q0}, @var{q0}}
764
@end itemize
765
 
766
 
767
@itemize @bullet
768
@item int32x4_t vmlaq_s32 (int32x4_t, int32x4_t, int32x4_t)
769
@*@emph{Form of expected instruction(s):} @code{vmla.i32 @var{q0}, @var{q0}, @var{q0}}
770
@end itemize
771
 
772
 
773
@itemize @bullet
774
@item int16x8_t vmlaq_s16 (int16x8_t, int16x8_t, int16x8_t)
775
@*@emph{Form of expected instruction(s):} @code{vmla.i16 @var{q0}, @var{q0}, @var{q0}}
776
@end itemize
777
 
778
 
779
@itemize @bullet
780
@item int8x16_t vmlaq_s8 (int8x16_t, int8x16_t, int8x16_t)
781
@*@emph{Form of expected instruction(s):} @code{vmla.i8 @var{q0}, @var{q0}, @var{q0}}
782
@end itemize
783
 
784
 
785
@itemize @bullet
786
@item float32x4_t vmlaq_f32 (float32x4_t, float32x4_t, float32x4_t)
787
@*@emph{Form of expected instruction(s):} @code{vmla.f32 @var{q0}, @var{q0}, @var{q0}}
788
@end itemize
789
 
790
 
791
@itemize @bullet
792
@item uint64x2_t vmlal_u32 (uint64x2_t, uint32x2_t, uint32x2_t)
793
@*@emph{Form of expected instruction(s):} @code{vmlal.u32 @var{q0}, @var{d0}, @var{d0}}
794
@end itemize
795
 
796
 
797
@itemize @bullet
798
@item uint32x4_t vmlal_u16 (uint32x4_t, uint16x4_t, uint16x4_t)
799
@*@emph{Form of expected instruction(s):} @code{vmlal.u16 @var{q0}, @var{d0}, @var{d0}}
800
@end itemize
801
 
802
 
803
@itemize @bullet
804
@item uint16x8_t vmlal_u8 (uint16x8_t, uint8x8_t, uint8x8_t)
805
@*@emph{Form of expected instruction(s):} @code{vmlal.u8 @var{q0}, @var{d0}, @var{d0}}
806
@end itemize
807
 
808
 
809
@itemize @bullet
810
@item int64x2_t vmlal_s32 (int64x2_t, int32x2_t, int32x2_t)
811
@*@emph{Form of expected instruction(s):} @code{vmlal.s32 @var{q0}, @var{d0}, @var{d0}}
812
@end itemize
813
 
814
 
815
@itemize @bullet
816
@item int32x4_t vmlal_s16 (int32x4_t, int16x4_t, int16x4_t)
817
@*@emph{Form of expected instruction(s):} @code{vmlal.s16 @var{q0}, @var{d0}, @var{d0}}
818
@end itemize
819
 
820
 
821
@itemize @bullet
822
@item int16x8_t vmlal_s8 (int16x8_t, int8x8_t, int8x8_t)
823
@*@emph{Form of expected instruction(s):} @code{vmlal.s8 @var{q0}, @var{d0}, @var{d0}}
824
@end itemize
825
 
826
 
827
@itemize @bullet
828
@item int64x2_t vqdmlal_s32 (int64x2_t, int32x2_t, int32x2_t)
829
@*@emph{Form of expected instruction(s):} @code{vqdmlal.s32 @var{q0}, @var{d0}, @var{d0}}
830
@end itemize
831
 
832
 
833
@itemize @bullet
834
@item int32x4_t vqdmlal_s16 (int32x4_t, int16x4_t, int16x4_t)
835
@*@emph{Form of expected instruction(s):} @code{vqdmlal.s16 @var{q0}, @var{d0}, @var{d0}}
836
@end itemize
837
 
838
 
839
 
840
 
841
@subsubsection Multiply-subtract
842
 
843
@itemize @bullet
844
@item uint32x2_t vmls_u32 (uint32x2_t, uint32x2_t, uint32x2_t)
845
@*@emph{Form of expected instruction(s):} @code{vmls.i32 @var{d0}, @var{d0}, @var{d0}}
846
@end itemize
847
 
848
 
849
@itemize @bullet
850
@item uint16x4_t vmls_u16 (uint16x4_t, uint16x4_t, uint16x4_t)
851
@*@emph{Form of expected instruction(s):} @code{vmls.i16 @var{d0}, @var{d0}, @var{d0}}
852
@end itemize
853
 
854
 
855
@itemize @bullet
856
@item uint8x8_t vmls_u8 (uint8x8_t, uint8x8_t, uint8x8_t)
857
@*@emph{Form of expected instruction(s):} @code{vmls.i8 @var{d0}, @var{d0}, @var{d0}}
858
@end itemize
859
 
860
 
861
@itemize @bullet
862
@item int32x2_t vmls_s32 (int32x2_t, int32x2_t, int32x2_t)
863
@*@emph{Form of expected instruction(s):} @code{vmls.i32 @var{d0}, @var{d0}, @var{d0}}
864
@end itemize
865
 
866
 
867
@itemize @bullet
868
@item int16x4_t vmls_s16 (int16x4_t, int16x4_t, int16x4_t)
869
@*@emph{Form of expected instruction(s):} @code{vmls.i16 @var{d0}, @var{d0}, @var{d0}}
870
@end itemize
871
 
872
 
873
@itemize @bullet
874
@item int8x8_t vmls_s8 (int8x8_t, int8x8_t, int8x8_t)
875
@*@emph{Form of expected instruction(s):} @code{vmls.i8 @var{d0}, @var{d0}, @var{d0}}
876
@end itemize
877
 
878
 
879
@itemize @bullet
880
@item float32x2_t vmls_f32 (float32x2_t, float32x2_t, float32x2_t)
881
@*@emph{Form of expected instruction(s):} @code{vmls.f32 @var{d0}, @var{d0}, @var{d0}}
882
@end itemize
883
 
884
 
885
@itemize @bullet
886
@item uint32x4_t vmlsq_u32 (uint32x4_t, uint32x4_t, uint32x4_t)
887
@*@emph{Form of expected instruction(s):} @code{vmls.i32 @var{q0}, @var{q0}, @var{q0}}
888
@end itemize
889
 
890
 
891
@itemize @bullet
892
@item uint16x8_t vmlsq_u16 (uint16x8_t, uint16x8_t, uint16x8_t)
893
@*@emph{Form of expected instruction(s):} @code{vmls.i16 @var{q0}, @var{q0}, @var{q0}}
894
@end itemize
895
 
896
 
897
@itemize @bullet
898
@item uint8x16_t vmlsq_u8 (uint8x16_t, uint8x16_t, uint8x16_t)
899
@*@emph{Form of expected instruction(s):} @code{vmls.i8 @var{q0}, @var{q0}, @var{q0}}
900
@end itemize
901
 
902
 
903
@itemize @bullet
904
@item int32x4_t vmlsq_s32 (int32x4_t, int32x4_t, int32x4_t)
905
@*@emph{Form of expected instruction(s):} @code{vmls.i32 @var{q0}, @var{q0}, @var{q0}}
906
@end itemize
907
 
908
 
909
@itemize @bullet
910
@item int16x8_t vmlsq_s16 (int16x8_t, int16x8_t, int16x8_t)
911
@*@emph{Form of expected instruction(s):} @code{vmls.i16 @var{q0}, @var{q0}, @var{q0}}
912
@end itemize
913
 
914
 
915
@itemize @bullet
916
@item int8x16_t vmlsq_s8 (int8x16_t, int8x16_t, int8x16_t)
917
@*@emph{Form of expected instruction(s):} @code{vmls.i8 @var{q0}, @var{q0}, @var{q0}}
918
@end itemize
919
 
920
 
921
@itemize @bullet
922
@item float32x4_t vmlsq_f32 (float32x4_t, float32x4_t, float32x4_t)
923
@*@emph{Form of expected instruction(s):} @code{vmls.f32 @var{q0}, @var{q0}, @var{q0}}
924
@end itemize
925
 
926
 
927
@itemize @bullet
928
@item uint64x2_t vmlsl_u32 (uint64x2_t, uint32x2_t, uint32x2_t)
929
@*@emph{Form of expected instruction(s):} @code{vmlsl.u32 @var{q0}, @var{d0}, @var{d0}}
930
@end itemize
931
 
932
 
933
@itemize @bullet
934
@item uint32x4_t vmlsl_u16 (uint32x4_t, uint16x4_t, uint16x4_t)
935
@*@emph{Form of expected instruction(s):} @code{vmlsl.u16 @var{q0}, @var{d0}, @var{d0}}
936
@end itemize
937
 
938
 
939
@itemize @bullet
940
@item uint16x8_t vmlsl_u8 (uint16x8_t, uint8x8_t, uint8x8_t)
941
@*@emph{Form of expected instruction(s):} @code{vmlsl.u8 @var{q0}, @var{d0}, @var{d0}}
942
@end itemize
943
 
944
 
945
@itemize @bullet
946
@item int64x2_t vmlsl_s32 (int64x2_t, int32x2_t, int32x2_t)
947
@*@emph{Form of expected instruction(s):} @code{vmlsl.s32 @var{q0}, @var{d0}, @var{d0}}
948
@end itemize
949
 
950
 
951
@itemize @bullet
952
@item int32x4_t vmlsl_s16 (int32x4_t, int16x4_t, int16x4_t)
953
@*@emph{Form of expected instruction(s):} @code{vmlsl.s16 @var{q0}, @var{d0}, @var{d0}}
954
@end itemize
955
 
956
 
957
@itemize @bullet
958
@item int16x8_t vmlsl_s8 (int16x8_t, int8x8_t, int8x8_t)
959
@*@emph{Form of expected instruction(s):} @code{vmlsl.s8 @var{q0}, @var{d0}, @var{d0}}
960
@end itemize
961
 
962
 
963
@itemize @bullet
964
@item int64x2_t vqdmlsl_s32 (int64x2_t, int32x2_t, int32x2_t)
965
@*@emph{Form of expected instruction(s):} @code{vqdmlsl.s32 @var{q0}, @var{d0}, @var{d0}}
966
@end itemize
967
 
968
 
969
@itemize @bullet
970
@item int32x4_t vqdmlsl_s16 (int32x4_t, int16x4_t, int16x4_t)
971
@*@emph{Form of expected instruction(s):} @code{vqdmlsl.s16 @var{q0}, @var{d0}, @var{d0}}
972
@end itemize
973
 
974
 
975
 
976
 
977
@subsubsection Subtraction
978
 
979
@itemize @bullet
980
@item uint32x2_t vsub_u32 (uint32x2_t, uint32x2_t)
981
@*@emph{Form of expected instruction(s):} @code{vsub.i32 @var{d0}, @var{d0}, @var{d0}}
982
@end itemize
983
 
984
 
985
@itemize @bullet
986
@item uint16x4_t vsub_u16 (uint16x4_t, uint16x4_t)
987
@*@emph{Form of expected instruction(s):} @code{vsub.i16 @var{d0}, @var{d0}, @var{d0}}
988
@end itemize
989
 
990
 
991
@itemize @bullet
992
@item uint8x8_t vsub_u8 (uint8x8_t, uint8x8_t)
993
@*@emph{Form of expected instruction(s):} @code{vsub.i8 @var{d0}, @var{d0}, @var{d0}}
994
@end itemize
995
 
996
 
997
@itemize @bullet
998
@item int32x2_t vsub_s32 (int32x2_t, int32x2_t)
999
@*@emph{Form of expected instruction(s):} @code{vsub.i32 @var{d0}, @var{d0}, @var{d0}}
1000
@end itemize
1001
 
1002
 
1003
@itemize @bullet
1004
@item int16x4_t vsub_s16 (int16x4_t, int16x4_t)
1005
@*@emph{Form of expected instruction(s):} @code{vsub.i16 @var{d0}, @var{d0}, @var{d0}}
1006
@end itemize
1007
 
1008
 
1009
@itemize @bullet
1010
@item int8x8_t vsub_s8 (int8x8_t, int8x8_t)
1011
@*@emph{Form of expected instruction(s):} @code{vsub.i8 @var{d0}, @var{d0}, @var{d0}}
1012
@end itemize
1013
 
1014
 
1015
@itemize @bullet
1016
@item uint64x1_t vsub_u64 (uint64x1_t, uint64x1_t)
1017
@*@emph{Form of expected instruction(s):} @code{vsub.i64 @var{d0}, @var{d0}, @var{d0}}
1018
@end itemize
1019
 
1020
 
1021
@itemize @bullet
1022
@item int64x1_t vsub_s64 (int64x1_t, int64x1_t)
1023
@*@emph{Form of expected instruction(s):} @code{vsub.i64 @var{d0}, @var{d0}, @var{d0}}
1024
@end itemize
1025
 
1026
 
1027
@itemize @bullet
1028
@item float32x2_t vsub_f32 (float32x2_t, float32x2_t)
1029
@*@emph{Form of expected instruction(s):} @code{vsub.f32 @var{d0}, @var{d0}, @var{d0}}
1030
@end itemize
1031
 
1032
 
1033
@itemize @bullet
1034
@item uint32x4_t vsubq_u32 (uint32x4_t, uint32x4_t)
1035
@*@emph{Form of expected instruction(s):} @code{vsub.i32 @var{q0}, @var{q0}, @var{q0}}
1036
@end itemize
1037
 
1038
 
1039
@itemize @bullet
1040
@item uint16x8_t vsubq_u16 (uint16x8_t, uint16x8_t)
1041
@*@emph{Form of expected instruction(s):} @code{vsub.i16 @var{q0}, @var{q0}, @var{q0}}
1042
@end itemize
1043
 
1044
 
1045
@itemize @bullet
1046
@item uint8x16_t vsubq_u8 (uint8x16_t, uint8x16_t)
1047
@*@emph{Form of expected instruction(s):} @code{vsub.i8 @var{q0}, @var{q0}, @var{q0}}
1048
@end itemize
1049
 
1050
 
1051
@itemize @bullet
1052
@item int32x4_t vsubq_s32 (int32x4_t, int32x4_t)
1053
@*@emph{Form of expected instruction(s):} @code{vsub.i32 @var{q0}, @var{q0}, @var{q0}}
1054
@end itemize
1055
 
1056
 
1057
@itemize @bullet
1058
@item int16x8_t vsubq_s16 (int16x8_t, int16x8_t)
1059
@*@emph{Form of expected instruction(s):} @code{vsub.i16 @var{q0}, @var{q0}, @var{q0}}
1060
@end itemize
1061
 
1062
 
1063
@itemize @bullet
1064
@item int8x16_t vsubq_s8 (int8x16_t, int8x16_t)
1065
@*@emph{Form of expected instruction(s):} @code{vsub.i8 @var{q0}, @var{q0}, @var{q0}}
1066
@end itemize
1067
 
1068
 
1069
@itemize @bullet
1070
@item uint64x2_t vsubq_u64 (uint64x2_t, uint64x2_t)
1071
@*@emph{Form of expected instruction(s):} @code{vsub.i64 @var{q0}, @var{q0}, @var{q0}}
1072
@end itemize
1073
 
1074
 
1075
@itemize @bullet
1076
@item int64x2_t vsubq_s64 (int64x2_t, int64x2_t)
1077
@*@emph{Form of expected instruction(s):} @code{vsub.i64 @var{q0}, @var{q0}, @var{q0}}
1078
@end itemize
1079
 
1080
 
1081
@itemize @bullet
1082
@item float32x4_t vsubq_f32 (float32x4_t, float32x4_t)
1083
@*@emph{Form of expected instruction(s):} @code{vsub.f32 @var{q0}, @var{q0}, @var{q0}}
1084
@end itemize
1085
 
1086
 
1087
@itemize @bullet
1088
@item uint64x2_t vsubl_u32 (uint32x2_t, uint32x2_t)
1089
@*@emph{Form of expected instruction(s):} @code{vsubl.u32 @var{q0}, @var{d0}, @var{d0}}
1090
@end itemize
1091
 
1092
 
1093
@itemize @bullet
1094
@item uint32x4_t vsubl_u16 (uint16x4_t, uint16x4_t)
1095
@*@emph{Form of expected instruction(s):} @code{vsubl.u16 @var{q0}, @var{d0}, @var{d0}}
1096
@end itemize
1097
 
1098
 
1099
@itemize @bullet
1100
@item uint16x8_t vsubl_u8 (uint8x8_t, uint8x8_t)
1101
@*@emph{Form of expected instruction(s):} @code{vsubl.u8 @var{q0}, @var{d0}, @var{d0}}
1102
@end itemize
1103
 
1104
 
1105
@itemize @bullet
1106
@item int64x2_t vsubl_s32 (int32x2_t, int32x2_t)
1107
@*@emph{Form of expected instruction(s):} @code{vsubl.s32 @var{q0}, @var{d0}, @var{d0}}
1108
@end itemize
1109
 
1110
 
1111
@itemize @bullet
1112
@item int32x4_t vsubl_s16 (int16x4_t, int16x4_t)
1113
@*@emph{Form of expected instruction(s):} @code{vsubl.s16 @var{q0}, @var{d0}, @var{d0}}
1114
@end itemize
1115
 
1116
 
1117
@itemize @bullet
1118
@item int16x8_t vsubl_s8 (int8x8_t, int8x8_t)
1119
@*@emph{Form of expected instruction(s):} @code{vsubl.s8 @var{q0}, @var{d0}, @var{d0}}
1120
@end itemize
1121
 
1122
 
1123
@itemize @bullet
1124
@item uint64x2_t vsubw_u32 (uint64x2_t, uint32x2_t)
1125
@*@emph{Form of expected instruction(s):} @code{vsubw.u32 @var{q0}, @var{q0}, @var{d0}}
1126
@end itemize
1127
 
1128
 
1129
@itemize @bullet
1130
@item uint32x4_t vsubw_u16 (uint32x4_t, uint16x4_t)
1131
@*@emph{Form of expected instruction(s):} @code{vsubw.u16 @var{q0}, @var{q0}, @var{d0}}
1132
@end itemize
1133
 
1134
 
1135
@itemize @bullet
1136
@item uint16x8_t vsubw_u8 (uint16x8_t, uint8x8_t)
1137
@*@emph{Form of expected instruction(s):} @code{vsubw.u8 @var{q0}, @var{q0}, @var{d0}}
1138
@end itemize
1139
 
1140
 
1141
@itemize @bullet
1142
@item int64x2_t vsubw_s32 (int64x2_t, int32x2_t)
1143
@*@emph{Form of expected instruction(s):} @code{vsubw.s32 @var{q0}, @var{q0}, @var{d0}}
1144
@end itemize
1145
 
1146
 
1147
@itemize @bullet
1148
@item int32x4_t vsubw_s16 (int32x4_t, int16x4_t)
1149
@*@emph{Form of expected instruction(s):} @code{vsubw.s16 @var{q0}, @var{q0}, @var{d0}}
1150
@end itemize
1151
 
1152
 
1153
@itemize @bullet
1154
@item int16x8_t vsubw_s8 (int16x8_t, int8x8_t)
1155
@*@emph{Form of expected instruction(s):} @code{vsubw.s8 @var{q0}, @var{q0}, @var{d0}}
1156
@end itemize
1157
 
1158
 
1159
@itemize @bullet
1160
@item uint32x2_t vhsub_u32 (uint32x2_t, uint32x2_t)
1161
@*@emph{Form of expected instruction(s):} @code{vhsub.u32 @var{d0}, @var{d0}, @var{d0}}
1162
@end itemize
1163
 
1164
 
1165
@itemize @bullet
1166
@item uint16x4_t vhsub_u16 (uint16x4_t, uint16x4_t)
1167
@*@emph{Form of expected instruction(s):} @code{vhsub.u16 @var{d0}, @var{d0}, @var{d0}}
1168
@end itemize
1169
 
1170
 
1171
@itemize @bullet
1172
@item uint8x8_t vhsub_u8 (uint8x8_t, uint8x8_t)
1173
@*@emph{Form of expected instruction(s):} @code{vhsub.u8 @var{d0}, @var{d0}, @var{d0}}
1174
@end itemize
1175
 
1176
 
1177
@itemize @bullet
1178
@item int32x2_t vhsub_s32 (int32x2_t, int32x2_t)
1179
@*@emph{Form of expected instruction(s):} @code{vhsub.s32 @var{d0}, @var{d0}, @var{d0}}
1180
@end itemize
1181
 
1182
 
1183
@itemize @bullet
1184
@item int16x4_t vhsub_s16 (int16x4_t, int16x4_t)
1185
@*@emph{Form of expected instruction(s):} @code{vhsub.s16 @var{d0}, @var{d0}, @var{d0}}
1186
@end itemize
1187
 
1188
 
1189
@itemize @bullet
1190
@item int8x8_t vhsub_s8 (int8x8_t, int8x8_t)
1191
@*@emph{Form of expected instruction(s):} @code{vhsub.s8 @var{d0}, @var{d0}, @var{d0}}
1192
@end itemize
1193
 
1194
 
1195
@itemize @bullet
1196
@item uint32x4_t vhsubq_u32 (uint32x4_t, uint32x4_t)
1197
@*@emph{Form of expected instruction(s):} @code{vhsub.u32 @var{q0}, @var{q0}, @var{q0}}
1198
@end itemize
1199
 
1200
 
1201
@itemize @bullet
1202
@item uint16x8_t vhsubq_u16 (uint16x8_t, uint16x8_t)
1203
@*@emph{Form of expected instruction(s):} @code{vhsub.u16 @var{q0}, @var{q0}, @var{q0}}
1204
@end itemize
1205
 
1206
 
1207
@itemize @bullet
1208
@item uint8x16_t vhsubq_u8 (uint8x16_t, uint8x16_t)
1209
@*@emph{Form of expected instruction(s):} @code{vhsub.u8 @var{q0}, @var{q0}, @var{q0}}
1210
@end itemize
1211
 
1212
 
1213
@itemize @bullet
1214
@item int32x4_t vhsubq_s32 (int32x4_t, int32x4_t)
1215
@*@emph{Form of expected instruction(s):} @code{vhsub.s32 @var{q0}, @var{q0}, @var{q0}}
1216
@end itemize
1217
 
1218
 
1219
@itemize @bullet
1220
@item int16x8_t vhsubq_s16 (int16x8_t, int16x8_t)
1221
@*@emph{Form of expected instruction(s):} @code{vhsub.s16 @var{q0}, @var{q0}, @var{q0}}
1222
@end itemize
1223
 
1224
 
1225
@itemize @bullet
1226
@item int8x16_t vhsubq_s8 (int8x16_t, int8x16_t)
1227
@*@emph{Form of expected instruction(s):} @code{vhsub.s8 @var{q0}, @var{q0}, @var{q0}}
1228
@end itemize
1229
 
1230
 
1231
@itemize @bullet
1232
@item uint32x2_t vqsub_u32 (uint32x2_t, uint32x2_t)
1233
@*@emph{Form of expected instruction(s):} @code{vqsub.u32 @var{d0}, @var{d0}, @var{d0}}
1234
@end itemize
1235
 
1236
 
1237
@itemize @bullet
1238
@item uint16x4_t vqsub_u16 (uint16x4_t, uint16x4_t)
1239
@*@emph{Form of expected instruction(s):} @code{vqsub.u16 @var{d0}, @var{d0}, @var{d0}}
1240
@end itemize
1241
 
1242
 
1243
@itemize @bullet
1244
@item uint8x8_t vqsub_u8 (uint8x8_t, uint8x8_t)
1245
@*@emph{Form of expected instruction(s):} @code{vqsub.u8 @var{d0}, @var{d0}, @var{d0}}
1246
@end itemize
1247
 
1248
 
1249
@itemize @bullet
1250
@item int32x2_t vqsub_s32 (int32x2_t, int32x2_t)
1251
@*@emph{Form of expected instruction(s):} @code{vqsub.s32 @var{d0}, @var{d0}, @var{d0}}
1252
@end itemize
1253
 
1254
 
1255
@itemize @bullet
1256
@item int16x4_t vqsub_s16 (int16x4_t, int16x4_t)
1257
@*@emph{Form of expected instruction(s):} @code{vqsub.s16 @var{d0}, @var{d0}, @var{d0}}
1258
@end itemize
1259
 
1260
 
1261
@itemize @bullet
1262
@item int8x8_t vqsub_s8 (int8x8_t, int8x8_t)
1263
@*@emph{Form of expected instruction(s):} @code{vqsub.s8 @var{d0}, @var{d0}, @var{d0}}
1264
@end itemize
1265
 
1266
 
1267
@itemize @bullet
1268
@item uint64x1_t vqsub_u64 (uint64x1_t, uint64x1_t)
1269
@*@emph{Form of expected instruction(s):} @code{vqsub.u64 @var{d0}, @var{d0}, @var{d0}}
1270
@end itemize
1271
 
1272
 
1273
@itemize @bullet
1274
@item int64x1_t vqsub_s64 (int64x1_t, int64x1_t)
1275
@*@emph{Form of expected instruction(s):} @code{vqsub.s64 @var{d0}, @var{d0}, @var{d0}}
1276
@end itemize
1277
 
1278
 
1279
@itemize @bullet
1280
@item uint32x4_t vqsubq_u32 (uint32x4_t, uint32x4_t)
1281
@*@emph{Form of expected instruction(s):} @code{vqsub.u32 @var{q0}, @var{q0}, @var{q0}}
1282
@end itemize
1283
 
1284
 
1285
@itemize @bullet
1286
@item uint16x8_t vqsubq_u16 (uint16x8_t, uint16x8_t)
1287
@*@emph{Form of expected instruction(s):} @code{vqsub.u16 @var{q0}, @var{q0}, @var{q0}}
1288
@end itemize
1289
 
1290
 
1291
@itemize @bullet
1292
@item uint8x16_t vqsubq_u8 (uint8x16_t, uint8x16_t)
1293
@*@emph{Form of expected instruction(s):} @code{vqsub.u8 @var{q0}, @var{q0}, @var{q0}}
1294
@end itemize
1295
 
1296
 
1297
@itemize @bullet
1298
@item int32x4_t vqsubq_s32 (int32x4_t, int32x4_t)
1299
@*@emph{Form of expected instruction(s):} @code{vqsub.s32 @var{q0}, @var{q0}, @var{q0}}
1300
@end itemize
1301
 
1302
 
1303
@itemize @bullet
1304
@item int16x8_t vqsubq_s16 (int16x8_t, int16x8_t)
1305
@*@emph{Form of expected instruction(s):} @code{vqsub.s16 @var{q0}, @var{q0}, @var{q0}}
1306
@end itemize
1307
 
1308
 
1309
@itemize @bullet
1310
@item int8x16_t vqsubq_s8 (int8x16_t, int8x16_t)
1311
@*@emph{Form of expected instruction(s):} @code{vqsub.s8 @var{q0}, @var{q0}, @var{q0}}
1312
@end itemize
1313
 
1314
 
1315
@itemize @bullet
1316
@item uint64x2_t vqsubq_u64 (uint64x2_t, uint64x2_t)
1317
@*@emph{Form of expected instruction(s):} @code{vqsub.u64 @var{q0}, @var{q0}, @var{q0}}
1318
@end itemize
1319
 
1320
 
1321
@itemize @bullet
1322
@item int64x2_t vqsubq_s64 (int64x2_t, int64x2_t)
1323
@*@emph{Form of expected instruction(s):} @code{vqsub.s64 @var{q0}, @var{q0}, @var{q0}}
1324
@end itemize
1325
 
1326
 
1327
@itemize @bullet
1328
@item uint32x2_t vsubhn_u64 (uint64x2_t, uint64x2_t)
1329
@*@emph{Form of expected instruction(s):} @code{vsubhn.i64 @var{d0}, @var{q0}, @var{q0}}
1330
@end itemize
1331
 
1332
 
1333
@itemize @bullet
1334
@item uint16x4_t vsubhn_u32 (uint32x4_t, uint32x4_t)
1335
@*@emph{Form of expected instruction(s):} @code{vsubhn.i32 @var{d0}, @var{q0}, @var{q0}}
1336
@end itemize
1337
 
1338
 
1339
@itemize @bullet
1340
@item uint8x8_t vsubhn_u16 (uint16x8_t, uint16x8_t)
1341
@*@emph{Form of expected instruction(s):} @code{vsubhn.i16 @var{d0}, @var{q0}, @var{q0}}
1342
@end itemize
1343
 
1344
 
1345
@itemize @bullet
1346
@item int32x2_t vsubhn_s64 (int64x2_t, int64x2_t)
1347
@*@emph{Form of expected instruction(s):} @code{vsubhn.i64 @var{d0}, @var{q0}, @var{q0}}
1348
@end itemize
1349
 
1350
 
1351
@itemize @bullet
1352
@item int16x4_t vsubhn_s32 (int32x4_t, int32x4_t)
1353
@*@emph{Form of expected instruction(s):} @code{vsubhn.i32 @var{d0}, @var{q0}, @var{q0}}
1354
@end itemize
1355
 
1356
 
1357
@itemize @bullet
1358
@item int8x8_t vsubhn_s16 (int16x8_t, int16x8_t)
1359
@*@emph{Form of expected instruction(s):} @code{vsubhn.i16 @var{d0}, @var{q0}, @var{q0}}
1360
@end itemize
1361
 
1362
 
1363
@itemize @bullet
1364
@item uint32x2_t vrsubhn_u64 (uint64x2_t, uint64x2_t)
1365
@*@emph{Form of expected instruction(s):} @code{vrsubhn.i64 @var{d0}, @var{q0}, @var{q0}}
1366
@end itemize
1367
 
1368
 
1369
@itemize @bullet
1370
@item uint16x4_t vrsubhn_u32 (uint32x4_t, uint32x4_t)
1371
@*@emph{Form of expected instruction(s):} @code{vrsubhn.i32 @var{d0}, @var{q0}, @var{q0}}
1372
@end itemize
1373
 
1374
 
1375
@itemize @bullet
1376
@item uint8x8_t vrsubhn_u16 (uint16x8_t, uint16x8_t)
1377
@*@emph{Form of expected instruction(s):} @code{vrsubhn.i16 @var{d0}, @var{q0}, @var{q0}}
1378
@end itemize
1379
 
1380
 
1381
@itemize @bullet
1382
@item int32x2_t vrsubhn_s64 (int64x2_t, int64x2_t)
1383
@*@emph{Form of expected instruction(s):} @code{vrsubhn.i64 @var{d0}, @var{q0}, @var{q0}}
1384
@end itemize
1385
 
1386
 
1387
@itemize @bullet
1388
@item int16x4_t vrsubhn_s32 (int32x4_t, int32x4_t)
1389
@*@emph{Form of expected instruction(s):} @code{vrsubhn.i32 @var{d0}, @var{q0}, @var{q0}}
1390
@end itemize
1391
 
1392
 
1393
@itemize @bullet
1394
@item int8x8_t vrsubhn_s16 (int16x8_t, int16x8_t)
1395
@*@emph{Form of expected instruction(s):} @code{vrsubhn.i16 @var{d0}, @var{q0}, @var{q0}}
1396
@end itemize
1397
 
1398
 
1399
 
1400
 
1401
@subsubsection Comparison (equal-to)
1402
 
1403
@itemize @bullet
1404
@item uint32x2_t vceq_u32 (uint32x2_t, uint32x2_t)
1405
@*@emph{Form of expected instruction(s):} @code{vceq.i32 @var{d0}, @var{d0}, @var{d0}}
1406
@end itemize
1407
 
1408
 
1409
@itemize @bullet
1410
@item uint16x4_t vceq_u16 (uint16x4_t, uint16x4_t)
1411
@*@emph{Form of expected instruction(s):} @code{vceq.i16 @var{d0}, @var{d0}, @var{d0}}
1412
@end itemize
1413
 
1414
 
1415
@itemize @bullet
1416
@item uint8x8_t vceq_u8 (uint8x8_t, uint8x8_t)
1417
@*@emph{Form of expected instruction(s):} @code{vceq.i8 @var{d0}, @var{d0}, @var{d0}}
1418
@end itemize
1419
 
1420
 
1421
@itemize @bullet
1422
@item uint32x2_t vceq_s32 (int32x2_t, int32x2_t)
1423
@*@emph{Form of expected instruction(s):} @code{vceq.i32 @var{d0}, @var{d0}, @var{d0}}
1424
@end itemize
1425
 
1426
 
1427
@itemize @bullet
1428
@item uint16x4_t vceq_s16 (int16x4_t, int16x4_t)
1429
@*@emph{Form of expected instruction(s):} @code{vceq.i16 @var{d0}, @var{d0}, @var{d0}}
1430
@end itemize
1431
 
1432
 
1433
@itemize @bullet
1434
@item uint8x8_t vceq_s8 (int8x8_t, int8x8_t)
1435
@*@emph{Form of expected instruction(s):} @code{vceq.i8 @var{d0}, @var{d0}, @var{d0}}
1436
@end itemize
1437
 
1438
 
1439
@itemize @bullet
1440
@item uint32x2_t vceq_f32 (float32x2_t, float32x2_t)
1441
@*@emph{Form of expected instruction(s):} @code{vceq.f32 @var{d0}, @var{d0}, @var{d0}}
1442
@end itemize
1443
 
1444
 
1445
@itemize @bullet
1446
@item uint8x8_t vceq_p8 (poly8x8_t, poly8x8_t)
1447
@*@emph{Form of expected instruction(s):} @code{vceq.i8 @var{d0}, @var{d0}, @var{d0}}
1448
@end itemize
1449
 
1450
 
1451
@itemize @bullet
1452
@item uint32x4_t vceqq_u32 (uint32x4_t, uint32x4_t)
1453
@*@emph{Form of expected instruction(s):} @code{vceq.i32 @var{q0}, @var{q0}, @var{q0}}
1454
@end itemize
1455
 
1456
 
1457
@itemize @bullet
1458
@item uint16x8_t vceqq_u16 (uint16x8_t, uint16x8_t)
1459
@*@emph{Form of expected instruction(s):} @code{vceq.i16 @var{q0}, @var{q0}, @var{q0}}
1460
@end itemize
1461
 
1462
 
1463
@itemize @bullet
1464
@item uint8x16_t vceqq_u8 (uint8x16_t, uint8x16_t)
1465
@*@emph{Form of expected instruction(s):} @code{vceq.i8 @var{q0}, @var{q0}, @var{q0}}
1466
@end itemize
1467
 
1468
 
1469
@itemize @bullet
1470
@item uint32x4_t vceqq_s32 (int32x4_t, int32x4_t)
1471
@*@emph{Form of expected instruction(s):} @code{vceq.i32 @var{q0}, @var{q0}, @var{q0}}
1472
@end itemize
1473
 
1474
 
1475
@itemize @bullet
1476
@item uint16x8_t vceqq_s16 (int16x8_t, int16x8_t)
1477
@*@emph{Form of expected instruction(s):} @code{vceq.i16 @var{q0}, @var{q0}, @var{q0}}
1478
@end itemize
1479
 
1480
 
1481
@itemize @bullet
1482
@item uint8x16_t vceqq_s8 (int8x16_t, int8x16_t)
1483
@*@emph{Form of expected instruction(s):} @code{vceq.i8 @var{q0}, @var{q0}, @var{q0}}
1484
@end itemize
1485
 
1486
 
1487
@itemize @bullet
1488
@item uint32x4_t vceqq_f32 (float32x4_t, float32x4_t)
1489
@*@emph{Form of expected instruction(s):} @code{vceq.f32 @var{q0}, @var{q0}, @var{q0}}
1490
@end itemize
1491
 
1492
 
1493
@itemize @bullet
1494
@item uint8x16_t vceqq_p8 (poly8x16_t, poly8x16_t)
1495
@*@emph{Form of expected instruction(s):} @code{vceq.i8 @var{q0}, @var{q0}, @var{q0}}
1496
@end itemize
1497
 
1498
 
1499
 
1500
 
1501
@subsubsection Comparison (greater-than-or-equal-to)
1502
 
1503
@itemize @bullet
1504
@item uint32x2_t vcge_u32 (uint32x2_t, uint32x2_t)
1505
@*@emph{Form of expected instruction(s):} @code{vcge.u32 @var{d0}, @var{d0}, @var{d0}}
1506
@end itemize
1507
 
1508
 
1509
@itemize @bullet
1510
@item uint16x4_t vcge_u16 (uint16x4_t, uint16x4_t)
1511
@*@emph{Form of expected instruction(s):} @code{vcge.u16 @var{d0}, @var{d0}, @var{d0}}
1512
@end itemize
1513
 
1514
 
1515
@itemize @bullet
1516
@item uint8x8_t vcge_u8 (uint8x8_t, uint8x8_t)
1517
@*@emph{Form of expected instruction(s):} @code{vcge.u8 @var{d0}, @var{d0}, @var{d0}}
1518
@end itemize
1519
 
1520
 
1521
@itemize @bullet
1522
@item uint32x2_t vcge_s32 (int32x2_t, int32x2_t)
1523
@*@emph{Form of expected instruction(s):} @code{vcge.s32 @var{d0}, @var{d0}, @var{d0}}
1524
@end itemize
1525
 
1526
 
1527
@itemize @bullet
1528
@item uint16x4_t vcge_s16 (int16x4_t, int16x4_t)
1529
@*@emph{Form of expected instruction(s):} @code{vcge.s16 @var{d0}, @var{d0}, @var{d0}}
1530
@end itemize
1531
 
1532
 
1533
@itemize @bullet
1534
@item uint8x8_t vcge_s8 (int8x8_t, int8x8_t)
1535
@*@emph{Form of expected instruction(s):} @code{vcge.s8 @var{d0}, @var{d0}, @var{d0}}
1536
@end itemize
1537
 
1538
 
1539
@itemize @bullet
1540
@item uint32x2_t vcge_f32 (float32x2_t, float32x2_t)
1541
@*@emph{Form of expected instruction(s):} @code{vcge.f32 @var{d0}, @var{d0}, @var{d0}}
1542
@end itemize
1543
 
1544
 
1545
@itemize @bullet
1546
@item uint32x4_t vcgeq_u32 (uint32x4_t, uint32x4_t)
1547
@*@emph{Form of expected instruction(s):} @code{vcge.u32 @var{q0}, @var{q0}, @var{q0}}
1548
@end itemize
1549
 
1550
 
1551
@itemize @bullet
1552
@item uint16x8_t vcgeq_u16 (uint16x8_t, uint16x8_t)
1553
@*@emph{Form of expected instruction(s):} @code{vcge.u16 @var{q0}, @var{q0}, @var{q0}}
1554
@end itemize
1555
 
1556
 
1557
@itemize @bullet
1558
@item uint8x16_t vcgeq_u8 (uint8x16_t, uint8x16_t)
1559
@*@emph{Form of expected instruction(s):} @code{vcge.u8 @var{q0}, @var{q0}, @var{q0}}
1560
@end itemize
1561
 
1562
 
1563
@itemize @bullet
1564
@item uint32x4_t vcgeq_s32 (int32x4_t, int32x4_t)
1565
@*@emph{Form of expected instruction(s):} @code{vcge.s32 @var{q0}, @var{q0}, @var{q0}}
1566
@end itemize
1567
 
1568
 
1569
@itemize @bullet
1570
@item uint16x8_t vcgeq_s16 (int16x8_t, int16x8_t)
1571
@*@emph{Form of expected instruction(s):} @code{vcge.s16 @var{q0}, @var{q0}, @var{q0}}
1572
@end itemize
1573
 
1574
 
1575
@itemize @bullet
1576
@item uint8x16_t vcgeq_s8 (int8x16_t, int8x16_t)
1577
@*@emph{Form of expected instruction(s):} @code{vcge.s8 @var{q0}, @var{q0}, @var{q0}}
1578
@end itemize
1579
 
1580
 
1581
@itemize @bullet
1582
@item uint32x4_t vcgeq_f32 (float32x4_t, float32x4_t)
1583
@*@emph{Form of expected instruction(s):} @code{vcge.f32 @var{q0}, @var{q0}, @var{q0}}
1584
@end itemize
1585
 
1586
 
1587
 
1588
 
1589
@subsubsection Comparison (less-than-or-equal-to)
1590
 
1591
@itemize @bullet
1592
@item uint32x2_t vcle_u32 (uint32x2_t, uint32x2_t)
1593
@*@emph{Form of expected instruction(s):} @code{vcge.u32 @var{d0}, @var{d0}, @var{d0}}
1594
@end itemize
1595
 
1596
 
1597
@itemize @bullet
1598
@item uint16x4_t vcle_u16 (uint16x4_t, uint16x4_t)
1599
@*@emph{Form of expected instruction(s):} @code{vcge.u16 @var{d0}, @var{d0}, @var{d0}}
1600
@end itemize
1601
 
1602
 
1603
@itemize @bullet
1604
@item uint8x8_t vcle_u8 (uint8x8_t, uint8x8_t)
1605
@*@emph{Form of expected instruction(s):} @code{vcge.u8 @var{d0}, @var{d0}, @var{d0}}
1606
@end itemize
1607
 
1608
 
1609
@itemize @bullet
1610
@item uint32x2_t vcle_s32 (int32x2_t, int32x2_t)
1611
@*@emph{Form of expected instruction(s):} @code{vcge.s32 @var{d0}, @var{d0}, @var{d0}}
1612
@end itemize
1613
 
1614
 
1615
@itemize @bullet
1616
@item uint16x4_t vcle_s16 (int16x4_t, int16x4_t)
1617
@*@emph{Form of expected instruction(s):} @code{vcge.s16 @var{d0}, @var{d0}, @var{d0}}
1618
@end itemize
1619
 
1620
 
1621
@itemize @bullet
1622
@item uint8x8_t vcle_s8 (int8x8_t, int8x8_t)
1623
@*@emph{Form of expected instruction(s):} @code{vcge.s8 @var{d0}, @var{d0}, @var{d0}}
1624
@end itemize
1625
 
1626
 
1627
@itemize @bullet
1628
@item uint32x2_t vcle_f32 (float32x2_t, float32x2_t)
1629
@*@emph{Form of expected instruction(s):} @code{vcge.f32 @var{d0}, @var{d0}, @var{d0}}
1630
@end itemize
1631
 
1632
 
1633
@itemize @bullet
1634
@item uint32x4_t vcleq_u32 (uint32x4_t, uint32x4_t)
1635
@*@emph{Form of expected instruction(s):} @code{vcge.u32 @var{q0}, @var{q0}, @var{q0}}
1636
@end itemize
1637
 
1638
 
1639
@itemize @bullet
1640
@item uint16x8_t vcleq_u16 (uint16x8_t, uint16x8_t)
1641
@*@emph{Form of expected instruction(s):} @code{vcge.u16 @var{q0}, @var{q0}, @var{q0}}
1642
@end itemize
1643
 
1644
 
1645
@itemize @bullet
1646
@item uint8x16_t vcleq_u8 (uint8x16_t, uint8x16_t)
1647
@*@emph{Form of expected instruction(s):} @code{vcge.u8 @var{q0}, @var{q0}, @var{q0}}
1648
@end itemize
1649
 
1650
 
1651
@itemize @bullet
1652
@item uint32x4_t vcleq_s32 (int32x4_t, int32x4_t)
1653
@*@emph{Form of expected instruction(s):} @code{vcge.s32 @var{q0}, @var{q0}, @var{q0}}
1654
@end itemize
1655
 
1656
 
1657
@itemize @bullet
1658
@item uint16x8_t vcleq_s16 (int16x8_t, int16x8_t)
1659
@*@emph{Form of expected instruction(s):} @code{vcge.s16 @var{q0}, @var{q0}, @var{q0}}
1660
@end itemize
1661
 
1662
 
1663
@itemize @bullet
1664
@item uint8x16_t vcleq_s8 (int8x16_t, int8x16_t)
1665
@*@emph{Form of expected instruction(s):} @code{vcge.s8 @var{q0}, @var{q0}, @var{q0}}
1666
@end itemize
1667
 
1668
 
1669
@itemize @bullet
1670
@item uint32x4_t vcleq_f32 (float32x4_t, float32x4_t)
1671
@*@emph{Form of expected instruction(s):} @code{vcge.f32 @var{q0}, @var{q0}, @var{q0}}
1672
@end itemize
1673
 
1674
 
1675
 
1676
 
1677
@subsubsection Comparison (greater-than)
1678
 
1679
@itemize @bullet
1680
@item uint32x2_t vcgt_u32 (uint32x2_t, uint32x2_t)
1681
@*@emph{Form of expected instruction(s):} @code{vcgt.u32 @var{d0}, @var{d0}, @var{d0}}
1682
@end itemize
1683
 
1684
 
1685
@itemize @bullet
1686
@item uint16x4_t vcgt_u16 (uint16x4_t, uint16x4_t)
1687
@*@emph{Form of expected instruction(s):} @code{vcgt.u16 @var{d0}, @var{d0}, @var{d0}}
1688
@end itemize
1689
 
1690
 
1691
@itemize @bullet
1692
@item uint8x8_t vcgt_u8 (uint8x8_t, uint8x8_t)
1693
@*@emph{Form of expected instruction(s):} @code{vcgt.u8 @var{d0}, @var{d0}, @var{d0}}
1694
@end itemize
1695
 
1696
 
1697
@itemize @bullet
1698
@item uint32x2_t vcgt_s32 (int32x2_t, int32x2_t)
1699
@*@emph{Form of expected instruction(s):} @code{vcgt.s32 @var{d0}, @var{d0}, @var{d0}}
1700
@end itemize
1701
 
1702
 
1703
@itemize @bullet
1704
@item uint16x4_t vcgt_s16 (int16x4_t, int16x4_t)
1705
@*@emph{Form of expected instruction(s):} @code{vcgt.s16 @var{d0}, @var{d0}, @var{d0}}
1706
@end itemize
1707
 
1708
 
1709
@itemize @bullet
1710
@item uint8x8_t vcgt_s8 (int8x8_t, int8x8_t)
1711
@*@emph{Form of expected instruction(s):} @code{vcgt.s8 @var{d0}, @var{d0}, @var{d0}}
1712
@end itemize
1713
 
1714
 
1715
@itemize @bullet
1716
@item uint32x2_t vcgt_f32 (float32x2_t, float32x2_t)
1717
@*@emph{Form of expected instruction(s):} @code{vcgt.f32 @var{d0}, @var{d0}, @var{d0}}
1718
@end itemize
1719
 
1720
 
1721
@itemize @bullet
1722
@item uint32x4_t vcgtq_u32 (uint32x4_t, uint32x4_t)
1723
@*@emph{Form of expected instruction(s):} @code{vcgt.u32 @var{q0}, @var{q0}, @var{q0}}
1724
@end itemize
1725
 
1726
 
1727
@itemize @bullet
1728
@item uint16x8_t vcgtq_u16 (uint16x8_t, uint16x8_t)
1729
@*@emph{Form of expected instruction(s):} @code{vcgt.u16 @var{q0}, @var{q0}, @var{q0}}
1730
@end itemize
1731
 
1732
 
1733
@itemize @bullet
1734
@item uint8x16_t vcgtq_u8 (uint8x16_t, uint8x16_t)
1735
@*@emph{Form of expected instruction(s):} @code{vcgt.u8 @var{q0}, @var{q0}, @var{q0}}
1736
@end itemize
1737
 
1738
 
1739
@itemize @bullet
1740
@item uint32x4_t vcgtq_s32 (int32x4_t, int32x4_t)
1741
@*@emph{Form of expected instruction(s):} @code{vcgt.s32 @var{q0}, @var{q0}, @var{q0}}
1742
@end itemize
1743
 
1744
 
1745
@itemize @bullet
1746
@item uint16x8_t vcgtq_s16 (int16x8_t, int16x8_t)
1747
@*@emph{Form of expected instruction(s):} @code{vcgt.s16 @var{q0}, @var{q0}, @var{q0}}
1748
@end itemize
1749
 
1750
 
1751
@itemize @bullet
1752
@item uint8x16_t vcgtq_s8 (int8x16_t, int8x16_t)
1753
@*@emph{Form of expected instruction(s):} @code{vcgt.s8 @var{q0}, @var{q0}, @var{q0}}
1754
@end itemize
1755
 
1756
 
1757
@itemize @bullet
1758
@item uint32x4_t vcgtq_f32 (float32x4_t, float32x4_t)
1759
@*@emph{Form of expected instruction(s):} @code{vcgt.f32 @var{q0}, @var{q0}, @var{q0}}
1760
@end itemize
1761
 
1762
 
1763
 
1764
 
1765
@subsubsection Comparison (less-than)
1766
 
1767
@itemize @bullet
1768
@item uint32x2_t vclt_u32 (uint32x2_t, uint32x2_t)
1769
@*@emph{Form of expected instruction(s):} @code{vcgt.u32 @var{d0}, @var{d0}, @var{d0}}
1770
@end itemize
1771
 
1772
 
1773
@itemize @bullet
1774
@item uint16x4_t vclt_u16 (uint16x4_t, uint16x4_t)
1775
@*@emph{Form of expected instruction(s):} @code{vcgt.u16 @var{d0}, @var{d0}, @var{d0}}
1776
@end itemize
1777
 
1778
 
1779
@itemize @bullet
1780
@item uint8x8_t vclt_u8 (uint8x8_t, uint8x8_t)
1781
@*@emph{Form of expected instruction(s):} @code{vcgt.u8 @var{d0}, @var{d0}, @var{d0}}
1782
@end itemize
1783
 
1784
 
1785
@itemize @bullet
1786
@item uint32x2_t vclt_s32 (int32x2_t, int32x2_t)
1787
@*@emph{Form of expected instruction(s):} @code{vcgt.s32 @var{d0}, @var{d0}, @var{d0}}
1788
@end itemize
1789
 
1790
 
1791
@itemize @bullet
1792
@item uint16x4_t vclt_s16 (int16x4_t, int16x4_t)
1793
@*@emph{Form of expected instruction(s):} @code{vcgt.s16 @var{d0}, @var{d0}, @var{d0}}
1794
@end itemize
1795
 
1796
 
1797
@itemize @bullet
1798
@item uint8x8_t vclt_s8 (int8x8_t, int8x8_t)
1799
@*@emph{Form of expected instruction(s):} @code{vcgt.s8 @var{d0}, @var{d0}, @var{d0}}
1800
@end itemize
1801
 
1802
 
1803
@itemize @bullet
1804
@item uint32x2_t vclt_f32 (float32x2_t, float32x2_t)
1805
@*@emph{Form of expected instruction(s):} @code{vcgt.f32 @var{d0}, @var{d0}, @var{d0}}
1806
@end itemize
1807
 
1808
 
1809
@itemize @bullet
1810
@item uint32x4_t vcltq_u32 (uint32x4_t, uint32x4_t)
1811
@*@emph{Form of expected instruction(s):} @code{vcgt.u32 @var{q0}, @var{q0}, @var{q0}}
1812
@end itemize
1813
 
1814
 
1815
@itemize @bullet
1816
@item uint16x8_t vcltq_u16 (uint16x8_t, uint16x8_t)
1817
@*@emph{Form of expected instruction(s):} @code{vcgt.u16 @var{q0}, @var{q0}, @var{q0}}
1818
@end itemize
1819
 
1820
 
1821
@itemize @bullet
1822
@item uint8x16_t vcltq_u8 (uint8x16_t, uint8x16_t)
1823
@*@emph{Form of expected instruction(s):} @code{vcgt.u8 @var{q0}, @var{q0}, @var{q0}}
1824
@end itemize
1825
 
1826
 
1827
@itemize @bullet
1828
@item uint32x4_t vcltq_s32 (int32x4_t, int32x4_t)
1829
@*@emph{Form of expected instruction(s):} @code{vcgt.s32 @var{q0}, @var{q0}, @var{q0}}
1830
@end itemize
1831
 
1832
 
1833
@itemize @bullet
1834
@item uint16x8_t vcltq_s16 (int16x8_t, int16x8_t)
1835
@*@emph{Form of expected instruction(s):} @code{vcgt.s16 @var{q0}, @var{q0}, @var{q0}}
1836
@end itemize
1837
 
1838
 
1839
@itemize @bullet
1840
@item uint8x16_t vcltq_s8 (int8x16_t, int8x16_t)
1841
@*@emph{Form of expected instruction(s):} @code{vcgt.s8 @var{q0}, @var{q0}, @var{q0}}
1842
@end itemize
1843
 
1844
 
1845
@itemize @bullet
1846
@item uint32x4_t vcltq_f32 (float32x4_t, float32x4_t)
1847
@*@emph{Form of expected instruction(s):} @code{vcgt.f32 @var{q0}, @var{q0}, @var{q0}}
1848
@end itemize
1849
 
1850
 
1851
 
1852
 
1853
@subsubsection Comparison (absolute greater-than-or-equal-to)
1854
 
1855
@itemize @bullet
1856
@item uint32x2_t vcage_f32 (float32x2_t, float32x2_t)
1857
@*@emph{Form of expected instruction(s):} @code{vacge.f32 @var{d0}, @var{d0}, @var{d0}}
1858
@end itemize
1859
 
1860
 
1861
@itemize @bullet
1862
@item uint32x4_t vcageq_f32 (float32x4_t, float32x4_t)
1863
@*@emph{Form of expected instruction(s):} @code{vacge.f32 @var{q0}, @var{q0}, @var{q0}}
1864
@end itemize
1865
 
1866
 
1867
 
1868
 
1869
@subsubsection Comparison (absolute less-than-or-equal-to)
1870
 
1871
@itemize @bullet
1872
@item uint32x2_t vcale_f32 (float32x2_t, float32x2_t)
1873
@*@emph{Form of expected instruction(s):} @code{vacge.f32 @var{d0}, @var{d0}, @var{d0}}
1874
@end itemize
1875
 
1876
 
1877
@itemize @bullet
1878
@item uint32x4_t vcaleq_f32 (float32x4_t, float32x4_t)
1879
@*@emph{Form of expected instruction(s):} @code{vacge.f32 @var{q0}, @var{q0}, @var{q0}}
1880
@end itemize
1881
 
1882
 
1883
 
1884
 
1885
@subsubsection Comparison (absolute greater-than)
1886
 
1887
@itemize @bullet
1888
@item uint32x2_t vcagt_f32 (float32x2_t, float32x2_t)
1889
@*@emph{Form of expected instruction(s):} @code{vacgt.f32 @var{d0}, @var{d0}, @var{d0}}
1890
@end itemize
1891
 
1892
 
1893
@itemize @bullet
1894
@item uint32x4_t vcagtq_f32 (float32x4_t, float32x4_t)
1895
@*@emph{Form of expected instruction(s):} @code{vacgt.f32 @var{q0}, @var{q0}, @var{q0}}
1896
@end itemize
1897
 
1898
 
1899
 
1900
 
1901
@subsubsection Comparison (absolute less-than)
1902
 
1903
@itemize @bullet
1904
@item uint32x2_t vcalt_f32 (float32x2_t, float32x2_t)
1905
@*@emph{Form of expected instruction(s):} @code{vacgt.f32 @var{d0}, @var{d0}, @var{d0}}
1906
@end itemize
1907
 
1908
 
1909
@itemize @bullet
1910
@item uint32x4_t vcaltq_f32 (float32x4_t, float32x4_t)
1911
@*@emph{Form of expected instruction(s):} @code{vacgt.f32 @var{q0}, @var{q0}, @var{q0}}
1912
@end itemize
1913
 
1914
 
1915
 
1916
 
1917
@subsubsection Test bits
1918
 
1919
@itemize @bullet
1920
@item uint32x2_t vtst_u32 (uint32x2_t, uint32x2_t)
1921
@*@emph{Form of expected instruction(s):} @code{vtst.32 @var{d0}, @var{d0}, @var{d0}}
1922
@end itemize
1923
 
1924
 
1925
@itemize @bullet
1926
@item uint16x4_t vtst_u16 (uint16x4_t, uint16x4_t)
1927
@*@emph{Form of expected instruction(s):} @code{vtst.16 @var{d0}, @var{d0}, @var{d0}}
1928
@end itemize
1929
 
1930
 
1931
@itemize @bullet
1932
@item uint8x8_t vtst_u8 (uint8x8_t, uint8x8_t)
1933
@*@emph{Form of expected instruction(s):} @code{vtst.8 @var{d0}, @var{d0}, @var{d0}}
1934
@end itemize
1935
 
1936
 
1937
@itemize @bullet
1938
@item uint32x2_t vtst_s32 (int32x2_t, int32x2_t)
1939
@*@emph{Form of expected instruction(s):} @code{vtst.32 @var{d0}, @var{d0}, @var{d0}}
1940
@end itemize
1941
 
1942
 
1943
@itemize @bullet
1944
@item uint16x4_t vtst_s16 (int16x4_t, int16x4_t)
1945
@*@emph{Form of expected instruction(s):} @code{vtst.16 @var{d0}, @var{d0}, @var{d0}}
1946
@end itemize
1947
 
1948
 
1949
@itemize @bullet
1950
@item uint8x8_t vtst_s8 (int8x8_t, int8x8_t)
1951
@*@emph{Form of expected instruction(s):} @code{vtst.8 @var{d0}, @var{d0}, @var{d0}}
1952
@end itemize
1953
 
1954
 
1955
@itemize @bullet
1956
@item uint8x8_t vtst_p8 (poly8x8_t, poly8x8_t)
1957
@*@emph{Form of expected instruction(s):} @code{vtst.8 @var{d0}, @var{d0}, @var{d0}}
1958
@end itemize
1959
 
1960
 
1961
@itemize @bullet
1962
@item uint32x4_t vtstq_u32 (uint32x4_t, uint32x4_t)
1963
@*@emph{Form of expected instruction(s):} @code{vtst.32 @var{q0}, @var{q0}, @var{q0}}
1964
@end itemize
1965
 
1966
 
1967
@itemize @bullet
1968
@item uint16x8_t vtstq_u16 (uint16x8_t, uint16x8_t)
1969
@*@emph{Form of expected instruction(s):} @code{vtst.16 @var{q0}, @var{q0}, @var{q0}}
1970
@end itemize
1971
 
1972
 
1973
@itemize @bullet
1974
@item uint8x16_t vtstq_u8 (uint8x16_t, uint8x16_t)
1975
@*@emph{Form of expected instruction(s):} @code{vtst.8 @var{q0}, @var{q0}, @var{q0}}
1976
@end itemize
1977
 
1978
 
1979
@itemize @bullet
1980
@item uint32x4_t vtstq_s32 (int32x4_t, int32x4_t)
1981
@*@emph{Form of expected instruction(s):} @code{vtst.32 @var{q0}, @var{q0}, @var{q0}}
1982
@end itemize
1983
 
1984
 
1985
@itemize @bullet
1986
@item uint16x8_t vtstq_s16 (int16x8_t, int16x8_t)
1987
@*@emph{Form of expected instruction(s):} @code{vtst.16 @var{q0}, @var{q0}, @var{q0}}
1988
@end itemize
1989
 
1990
 
1991
@itemize @bullet
1992
@item uint8x16_t vtstq_s8 (int8x16_t, int8x16_t)
1993
@*@emph{Form of expected instruction(s):} @code{vtst.8 @var{q0}, @var{q0}, @var{q0}}
1994
@end itemize
1995
 
1996
 
1997
@itemize @bullet
1998
@item uint8x16_t vtstq_p8 (poly8x16_t, poly8x16_t)
1999
@*@emph{Form of expected instruction(s):} @code{vtst.8 @var{q0}, @var{q0}, @var{q0}}
2000
@end itemize
2001
 
2002
 
2003
 
2004
 
2005
@subsubsection Absolute difference
2006
 
2007
@itemize @bullet
2008
@item uint32x2_t vabd_u32 (uint32x2_t, uint32x2_t)
2009
@*@emph{Form of expected instruction(s):} @code{vabd.u32 @var{d0}, @var{d0}, @var{d0}}
2010
@end itemize
2011
 
2012
 
2013
@itemize @bullet
2014
@item uint16x4_t vabd_u16 (uint16x4_t, uint16x4_t)
2015
@*@emph{Form of expected instruction(s):} @code{vabd.u16 @var{d0}, @var{d0}, @var{d0}}
2016
@end itemize
2017
 
2018
 
2019
@itemize @bullet
2020
@item uint8x8_t vabd_u8 (uint8x8_t, uint8x8_t)
2021
@*@emph{Form of expected instruction(s):} @code{vabd.u8 @var{d0}, @var{d0}, @var{d0}}
2022
@end itemize
2023
 
2024
 
2025
@itemize @bullet
2026
@item int32x2_t vabd_s32 (int32x2_t, int32x2_t)
2027
@*@emph{Form of expected instruction(s):} @code{vabd.s32 @var{d0}, @var{d0}, @var{d0}}
2028
@end itemize
2029
 
2030
 
2031
@itemize @bullet
2032
@item int16x4_t vabd_s16 (int16x4_t, int16x4_t)
2033
@*@emph{Form of expected instruction(s):} @code{vabd.s16 @var{d0}, @var{d0}, @var{d0}}
2034
@end itemize
2035
 
2036
 
2037
@itemize @bullet
2038
@item int8x8_t vabd_s8 (int8x8_t, int8x8_t)
2039
@*@emph{Form of expected instruction(s):} @code{vabd.s8 @var{d0}, @var{d0}, @var{d0}}
2040
@end itemize
2041
 
2042
 
2043
@itemize @bullet
2044
@item float32x2_t vabd_f32 (float32x2_t, float32x2_t)
2045
@*@emph{Form of expected instruction(s):} @code{vabd.f32 @var{d0}, @var{d0}, @var{d0}}
2046
@end itemize
2047
 
2048
 
2049
@itemize @bullet
2050
@item uint32x4_t vabdq_u32 (uint32x4_t, uint32x4_t)
2051
@*@emph{Form of expected instruction(s):} @code{vabd.u32 @var{q0}, @var{q0}, @var{q0}}
2052
@end itemize
2053
 
2054
 
2055
@itemize @bullet
2056
@item uint16x8_t vabdq_u16 (uint16x8_t, uint16x8_t)
2057
@*@emph{Form of expected instruction(s):} @code{vabd.u16 @var{q0}, @var{q0}, @var{q0}}
2058
@end itemize
2059
 
2060
 
2061
@itemize @bullet
2062
@item uint8x16_t vabdq_u8 (uint8x16_t, uint8x16_t)
2063
@*@emph{Form of expected instruction(s):} @code{vabd.u8 @var{q0}, @var{q0}, @var{q0}}
2064
@end itemize
2065
 
2066
 
2067
@itemize @bullet
2068
@item int32x4_t vabdq_s32 (int32x4_t, int32x4_t)
2069
@*@emph{Form of expected instruction(s):} @code{vabd.s32 @var{q0}, @var{q0}, @var{q0}}
2070
@end itemize
2071
 
2072
 
2073
@itemize @bullet
2074
@item int16x8_t vabdq_s16 (int16x8_t, int16x8_t)
2075
@*@emph{Form of expected instruction(s):} @code{vabd.s16 @var{q0}, @var{q0}, @var{q0}}
2076
@end itemize
2077
 
2078
 
2079
@itemize @bullet
2080
@item int8x16_t vabdq_s8 (int8x16_t, int8x16_t)
2081
@*@emph{Form of expected instruction(s):} @code{vabd.s8 @var{q0}, @var{q0}, @var{q0}}
2082
@end itemize
2083
 
2084
 
2085
@itemize @bullet
2086
@item float32x4_t vabdq_f32 (float32x4_t, float32x4_t)
2087
@*@emph{Form of expected instruction(s):} @code{vabd.f32 @var{q0}, @var{q0}, @var{q0}}
2088
@end itemize
2089
 
2090
 
2091
@itemize @bullet
2092
@item uint64x2_t vabdl_u32 (uint32x2_t, uint32x2_t)
2093
@*@emph{Form of expected instruction(s):} @code{vabdl.u32 @var{q0}, @var{d0}, @var{d0}}
2094
@end itemize
2095
 
2096
 
2097
@itemize @bullet
2098
@item uint32x4_t vabdl_u16 (uint16x4_t, uint16x4_t)
2099
@*@emph{Form of expected instruction(s):} @code{vabdl.u16 @var{q0}, @var{d0}, @var{d0}}
2100
@end itemize
2101
 
2102
 
2103
@itemize @bullet
2104
@item uint16x8_t vabdl_u8 (uint8x8_t, uint8x8_t)
2105
@*@emph{Form of expected instruction(s):} @code{vabdl.u8 @var{q0}, @var{d0}, @var{d0}}
2106
@end itemize
2107
 
2108
 
2109
@itemize @bullet
2110
@item int64x2_t vabdl_s32 (int32x2_t, int32x2_t)
2111
@*@emph{Form of expected instruction(s):} @code{vabdl.s32 @var{q0}, @var{d0}, @var{d0}}
2112
@end itemize
2113
 
2114
 
2115
@itemize @bullet
2116
@item int32x4_t vabdl_s16 (int16x4_t, int16x4_t)
2117
@*@emph{Form of expected instruction(s):} @code{vabdl.s16 @var{q0}, @var{d0}, @var{d0}}
2118
@end itemize
2119
 
2120
 
2121
@itemize @bullet
2122
@item int16x8_t vabdl_s8 (int8x8_t, int8x8_t)
2123
@*@emph{Form of expected instruction(s):} @code{vabdl.s8 @var{q0}, @var{d0}, @var{d0}}
2124
@end itemize
2125
 
2126
 
2127
 
2128
 
2129
@subsubsection Absolute difference and accumulate
2130
 
2131
@itemize @bullet
2132
@item uint32x2_t vaba_u32 (uint32x2_t, uint32x2_t, uint32x2_t)
2133
@*@emph{Form of expected instruction(s):} @code{vaba.u32 @var{d0}, @var{d0}, @var{d0}}
2134
@end itemize
2135
 
2136
 
2137
@itemize @bullet
2138
@item uint16x4_t vaba_u16 (uint16x4_t, uint16x4_t, uint16x4_t)
2139
@*@emph{Form of expected instruction(s):} @code{vaba.u16 @var{d0}, @var{d0}, @var{d0}}
2140
@end itemize
2141
 
2142
 
2143
@itemize @bullet
2144
@item uint8x8_t vaba_u8 (uint8x8_t, uint8x8_t, uint8x8_t)
2145
@*@emph{Form of expected instruction(s):} @code{vaba.u8 @var{d0}, @var{d0}, @var{d0}}
2146
@end itemize
2147
 
2148
 
2149
@itemize @bullet
2150
@item int32x2_t vaba_s32 (int32x2_t, int32x2_t, int32x2_t)
2151
@*@emph{Form of expected instruction(s):} @code{vaba.s32 @var{d0}, @var{d0}, @var{d0}}
2152
@end itemize
2153
 
2154
 
2155
@itemize @bullet
2156
@item int16x4_t vaba_s16 (int16x4_t, int16x4_t, int16x4_t)
2157
@*@emph{Form of expected instruction(s):} @code{vaba.s16 @var{d0}, @var{d0}, @var{d0}}
2158
@end itemize
2159
 
2160
 
2161
@itemize @bullet
2162
@item int8x8_t vaba_s8 (int8x8_t, int8x8_t, int8x8_t)
2163
@*@emph{Form of expected instruction(s):} @code{vaba.s8 @var{d0}, @var{d0}, @var{d0}}
2164
@end itemize
2165
 
2166
 
2167
@itemize @bullet
2168
@item uint32x4_t vabaq_u32 (uint32x4_t, uint32x4_t, uint32x4_t)
2169
@*@emph{Form of expected instruction(s):} @code{vaba.u32 @var{q0}, @var{q0}, @var{q0}}
2170
@end itemize
2171
 
2172
 
2173
@itemize @bullet
2174
@item uint16x8_t vabaq_u16 (uint16x8_t, uint16x8_t, uint16x8_t)
2175
@*@emph{Form of expected instruction(s):} @code{vaba.u16 @var{q0}, @var{q0}, @var{q0}}
2176
@end itemize
2177
 
2178
 
2179
@itemize @bullet
2180
@item uint8x16_t vabaq_u8 (uint8x16_t, uint8x16_t, uint8x16_t)
2181
@*@emph{Form of expected instruction(s):} @code{vaba.u8 @var{q0}, @var{q0}, @var{q0}}
2182
@end itemize
2183
 
2184
 
2185
@itemize @bullet
2186
@item int32x4_t vabaq_s32 (int32x4_t, int32x4_t, int32x4_t)
2187
@*@emph{Form of expected instruction(s):} @code{vaba.s32 @var{q0}, @var{q0}, @var{q0}}
2188
@end itemize
2189
 
2190
 
2191
@itemize @bullet
2192
@item int16x8_t vabaq_s16 (int16x8_t, int16x8_t, int16x8_t)
2193
@*@emph{Form of expected instruction(s):} @code{vaba.s16 @var{q0}, @var{q0}, @var{q0}}
2194
@end itemize
2195
 
2196
 
2197
@itemize @bullet
2198
@item int8x16_t vabaq_s8 (int8x16_t, int8x16_t, int8x16_t)
2199
@*@emph{Form of expected instruction(s):} @code{vaba.s8 @var{q0}, @var{q0}, @var{q0}}
2200
@end itemize
2201
 
2202
 
2203
@itemize @bullet
2204
@item uint64x2_t vabal_u32 (uint64x2_t, uint32x2_t, uint32x2_t)
2205
@*@emph{Form of expected instruction(s):} @code{vabal.u32 @var{q0}, @var{d0}, @var{d0}}
2206
@end itemize
2207
 
2208
 
2209
@itemize @bullet
2210
@item uint32x4_t vabal_u16 (uint32x4_t, uint16x4_t, uint16x4_t)
2211
@*@emph{Form of expected instruction(s):} @code{vabal.u16 @var{q0}, @var{d0}, @var{d0}}
2212
@end itemize
2213
 
2214
 
2215
@itemize @bullet
2216
@item uint16x8_t vabal_u8 (uint16x8_t, uint8x8_t, uint8x8_t)
2217
@*@emph{Form of expected instruction(s):} @code{vabal.u8 @var{q0}, @var{d0}, @var{d0}}
2218
@end itemize
2219
 
2220
 
2221
@itemize @bullet
2222
@item int64x2_t vabal_s32 (int64x2_t, int32x2_t, int32x2_t)
2223
@*@emph{Form of expected instruction(s):} @code{vabal.s32 @var{q0}, @var{d0}, @var{d0}}
2224
@end itemize
2225
 
2226
 
2227
@itemize @bullet
2228
@item int32x4_t vabal_s16 (int32x4_t, int16x4_t, int16x4_t)
2229
@*@emph{Form of expected instruction(s):} @code{vabal.s16 @var{q0}, @var{d0}, @var{d0}}
2230
@end itemize
2231
 
2232
 
2233
@itemize @bullet
2234
@item int16x8_t vabal_s8 (int16x8_t, int8x8_t, int8x8_t)
2235
@*@emph{Form of expected instruction(s):} @code{vabal.s8 @var{q0}, @var{d0}, @var{d0}}
2236
@end itemize
2237
 
2238
 
2239
 
2240
 
2241
@subsubsection Maximum
2242
 
2243
@itemize @bullet
2244
@item uint32x2_t vmax_u32 (uint32x2_t, uint32x2_t)
2245
@*@emph{Form of expected instruction(s):} @code{vmax.u32 @var{d0}, @var{d0}, @var{d0}}
2246
@end itemize
2247
 
2248
 
2249
@itemize @bullet
2250
@item uint16x4_t vmax_u16 (uint16x4_t, uint16x4_t)
2251
@*@emph{Form of expected instruction(s):} @code{vmax.u16 @var{d0}, @var{d0}, @var{d0}}
2252
@end itemize
2253
 
2254
 
2255
@itemize @bullet
2256
@item uint8x8_t vmax_u8 (uint8x8_t, uint8x8_t)
2257
@*@emph{Form of expected instruction(s):} @code{vmax.u8 @var{d0}, @var{d0}, @var{d0}}
2258
@end itemize
2259
 
2260
 
2261
@itemize @bullet
2262
@item int32x2_t vmax_s32 (int32x2_t, int32x2_t)
2263
@*@emph{Form of expected instruction(s):} @code{vmax.s32 @var{d0}, @var{d0}, @var{d0}}
2264
@end itemize
2265
 
2266
 
2267
@itemize @bullet
2268
@item int16x4_t vmax_s16 (int16x4_t, int16x4_t)
2269
@*@emph{Form of expected instruction(s):} @code{vmax.s16 @var{d0}, @var{d0}, @var{d0}}
2270
@end itemize
2271
 
2272
 
2273
@itemize @bullet
2274
@item int8x8_t vmax_s8 (int8x8_t, int8x8_t)
2275
@*@emph{Form of expected instruction(s):} @code{vmax.s8 @var{d0}, @var{d0}, @var{d0}}
2276
@end itemize
2277
 
2278
 
2279
@itemize @bullet
2280
@item float32x2_t vmax_f32 (float32x2_t, float32x2_t)
2281
@*@emph{Form of expected instruction(s):} @code{vmax.f32 @var{d0}, @var{d0}, @var{d0}}
2282
@end itemize
2283
 
2284
 
2285
@itemize @bullet
2286
@item uint32x4_t vmaxq_u32 (uint32x4_t, uint32x4_t)
2287
@*@emph{Form of expected instruction(s):} @code{vmax.u32 @var{q0}, @var{q0}, @var{q0}}
2288
@end itemize
2289
 
2290
 
2291
@itemize @bullet
2292
@item uint16x8_t vmaxq_u16 (uint16x8_t, uint16x8_t)
2293
@*@emph{Form of expected instruction(s):} @code{vmax.u16 @var{q0}, @var{q0}, @var{q0}}
2294
@end itemize
2295
 
2296
 
2297
@itemize @bullet
2298
@item uint8x16_t vmaxq_u8 (uint8x16_t, uint8x16_t)
2299
@*@emph{Form of expected instruction(s):} @code{vmax.u8 @var{q0}, @var{q0}, @var{q0}}
2300
@end itemize
2301
 
2302
 
2303
@itemize @bullet
2304
@item int32x4_t vmaxq_s32 (int32x4_t, int32x4_t)
2305
@*@emph{Form of expected instruction(s):} @code{vmax.s32 @var{q0}, @var{q0}, @var{q0}}
2306
@end itemize
2307
 
2308
 
2309
@itemize @bullet
2310
@item int16x8_t vmaxq_s16 (int16x8_t, int16x8_t)
2311
@*@emph{Form of expected instruction(s):} @code{vmax.s16 @var{q0}, @var{q0}, @var{q0}}
2312
@end itemize
2313
 
2314
 
2315
@itemize @bullet
2316
@item int8x16_t vmaxq_s8 (int8x16_t, int8x16_t)
2317
@*@emph{Form of expected instruction(s):} @code{vmax.s8 @var{q0}, @var{q0}, @var{q0}}
2318
@end itemize
2319
 
2320
 
2321
@itemize @bullet
2322
@item float32x4_t vmaxq_f32 (float32x4_t, float32x4_t)
2323
@*@emph{Form of expected instruction(s):} @code{vmax.f32 @var{q0}, @var{q0}, @var{q0}}
2324
@end itemize
2325
 
2326
 
2327
 
2328
 
2329
@subsubsection Minimum
2330
 
2331
@itemize @bullet
2332
@item uint32x2_t vmin_u32 (uint32x2_t, uint32x2_t)
2333
@*@emph{Form of expected instruction(s):} @code{vmin.u32 @var{d0}, @var{d0}, @var{d0}}
2334
@end itemize
2335
 
2336
 
2337
@itemize @bullet
2338
@item uint16x4_t vmin_u16 (uint16x4_t, uint16x4_t)
2339
@*@emph{Form of expected instruction(s):} @code{vmin.u16 @var{d0}, @var{d0}, @var{d0}}
2340
@end itemize
2341
 
2342
 
2343
@itemize @bullet
2344
@item uint8x8_t vmin_u8 (uint8x8_t, uint8x8_t)
2345
@*@emph{Form of expected instruction(s):} @code{vmin.u8 @var{d0}, @var{d0}, @var{d0}}
2346
@end itemize
2347
 
2348
 
2349
@itemize @bullet
2350
@item int32x2_t vmin_s32 (int32x2_t, int32x2_t)
2351
@*@emph{Form of expected instruction(s):} @code{vmin.s32 @var{d0}, @var{d0}, @var{d0}}
2352
@end itemize
2353
 
2354
 
2355
@itemize @bullet
2356
@item int16x4_t vmin_s16 (int16x4_t, int16x4_t)
2357
@*@emph{Form of expected instruction(s):} @code{vmin.s16 @var{d0}, @var{d0}, @var{d0}}
2358
@end itemize
2359
 
2360
 
2361
@itemize @bullet
2362
@item int8x8_t vmin_s8 (int8x8_t, int8x8_t)
2363
@*@emph{Form of expected instruction(s):} @code{vmin.s8 @var{d0}, @var{d0}, @var{d0}}
2364
@end itemize
2365
 
2366
 
2367
@itemize @bullet
2368
@item float32x2_t vmin_f32 (float32x2_t, float32x2_t)
2369
@*@emph{Form of expected instruction(s):} @code{vmin.f32 @var{d0}, @var{d0}, @var{d0}}
2370
@end itemize
2371
 
2372
 
2373
@itemize @bullet
2374
@item uint32x4_t vminq_u32 (uint32x4_t, uint32x4_t)
2375
@*@emph{Form of expected instruction(s):} @code{vmin.u32 @var{q0}, @var{q0}, @var{q0}}
2376
@end itemize
2377
 
2378
 
2379
@itemize @bullet
2380
@item uint16x8_t vminq_u16 (uint16x8_t, uint16x8_t)
2381
@*@emph{Form of expected instruction(s):} @code{vmin.u16 @var{q0}, @var{q0}, @var{q0}}
2382
@end itemize
2383
 
2384
 
2385
@itemize @bullet
2386
@item uint8x16_t vminq_u8 (uint8x16_t, uint8x16_t)
2387
@*@emph{Form of expected instruction(s):} @code{vmin.u8 @var{q0}, @var{q0}, @var{q0}}
2388
@end itemize
2389
 
2390
 
2391
@itemize @bullet
2392
@item int32x4_t vminq_s32 (int32x4_t, int32x4_t)
2393
@*@emph{Form of expected instruction(s):} @code{vmin.s32 @var{q0}, @var{q0}, @var{q0}}
2394
@end itemize
2395
 
2396
 
2397
@itemize @bullet
2398
@item int16x8_t vminq_s16 (int16x8_t, int16x8_t)
2399
@*@emph{Form of expected instruction(s):} @code{vmin.s16 @var{q0}, @var{q0}, @var{q0}}
2400
@end itemize
2401
 
2402
 
2403
@itemize @bullet
2404
@item int8x16_t vminq_s8 (int8x16_t, int8x16_t)
2405
@*@emph{Form of expected instruction(s):} @code{vmin.s8 @var{q0}, @var{q0}, @var{q0}}
2406
@end itemize
2407
 
2408
 
2409
@itemize @bullet
2410
@item float32x4_t vminq_f32 (float32x4_t, float32x4_t)
2411
@*@emph{Form of expected instruction(s):} @code{vmin.f32 @var{q0}, @var{q0}, @var{q0}}
2412
@end itemize
2413
 
2414
 
2415
 
2416
 
2417
@subsubsection Pairwise add
2418
 
2419
@itemize @bullet
2420
@item uint32x2_t vpadd_u32 (uint32x2_t, uint32x2_t)
2421
@*@emph{Form of expected instruction(s):} @code{vpadd.i32 @var{d0}, @var{d0}, @var{d0}}
2422
@end itemize
2423
 
2424
 
2425
@itemize @bullet
2426
@item uint16x4_t vpadd_u16 (uint16x4_t, uint16x4_t)
2427
@*@emph{Form of expected instruction(s):} @code{vpadd.i16 @var{d0}, @var{d0}, @var{d0}}
2428
@end itemize
2429
 
2430
 
2431
@itemize @bullet
2432
@item uint8x8_t vpadd_u8 (uint8x8_t, uint8x8_t)
2433
@*@emph{Form of expected instruction(s):} @code{vpadd.i8 @var{d0}, @var{d0}, @var{d0}}
2434
@end itemize
2435
 
2436
 
2437
@itemize @bullet
2438
@item int32x2_t vpadd_s32 (int32x2_t, int32x2_t)
2439
@*@emph{Form of expected instruction(s):} @code{vpadd.i32 @var{d0}, @var{d0}, @var{d0}}
2440
@end itemize
2441
 
2442
 
2443
@itemize @bullet
2444
@item int16x4_t vpadd_s16 (int16x4_t, int16x4_t)
2445
@*@emph{Form of expected instruction(s):} @code{vpadd.i16 @var{d0}, @var{d0}, @var{d0}}
2446
@end itemize
2447
 
2448
 
2449
@itemize @bullet
2450
@item int8x8_t vpadd_s8 (int8x8_t, int8x8_t)
2451
@*@emph{Form of expected instruction(s):} @code{vpadd.i8 @var{d0}, @var{d0}, @var{d0}}
2452
@end itemize
2453
 
2454
 
2455
@itemize @bullet
2456
@item float32x2_t vpadd_f32 (float32x2_t, float32x2_t)
2457
@*@emph{Form of expected instruction(s):} @code{vpadd.f32 @var{d0}, @var{d0}, @var{d0}}
2458
@end itemize
2459
 
2460
 
2461
@itemize @bullet
2462
@item uint64x1_t vpaddl_u32 (uint32x2_t)
2463
@*@emph{Form of expected instruction(s):} @code{vpaddl.u32 @var{d0}, @var{d0}}
2464
@end itemize
2465
 
2466
 
2467
@itemize @bullet
2468
@item uint32x2_t vpaddl_u16 (uint16x4_t)
2469
@*@emph{Form of expected instruction(s):} @code{vpaddl.u16 @var{d0}, @var{d0}}
2470
@end itemize
2471
 
2472
 
2473
@itemize @bullet
2474
@item uint16x4_t vpaddl_u8 (uint8x8_t)
2475
@*@emph{Form of expected instruction(s):} @code{vpaddl.u8 @var{d0}, @var{d0}}
2476
@end itemize
2477
 
2478
 
2479
@itemize @bullet
2480
@item int64x1_t vpaddl_s32 (int32x2_t)
2481
@*@emph{Form of expected instruction(s):} @code{vpaddl.s32 @var{d0}, @var{d0}}
2482
@end itemize
2483
 
2484
 
2485
@itemize @bullet
2486
@item int32x2_t vpaddl_s16 (int16x4_t)
2487
@*@emph{Form of expected instruction(s):} @code{vpaddl.s16 @var{d0}, @var{d0}}
2488
@end itemize
2489
 
2490
 
2491
@itemize @bullet
2492
@item int16x4_t vpaddl_s8 (int8x8_t)
2493
@*@emph{Form of expected instruction(s):} @code{vpaddl.s8 @var{d0}, @var{d0}}
2494
@end itemize
2495
 
2496
 
2497
@itemize @bullet
2498
@item uint64x2_t vpaddlq_u32 (uint32x4_t)
2499
@*@emph{Form of expected instruction(s):} @code{vpaddl.u32 @var{q0}, @var{q0}}
2500
@end itemize
2501
 
2502
 
2503
@itemize @bullet
2504
@item uint32x4_t vpaddlq_u16 (uint16x8_t)
2505
@*@emph{Form of expected instruction(s):} @code{vpaddl.u16 @var{q0}, @var{q0}}
2506
@end itemize
2507
 
2508
 
2509
@itemize @bullet
2510
@item uint16x8_t vpaddlq_u8 (uint8x16_t)
2511
@*@emph{Form of expected instruction(s):} @code{vpaddl.u8 @var{q0}, @var{q0}}
2512
@end itemize
2513
 
2514
 
2515
@itemize @bullet
2516
@item int64x2_t vpaddlq_s32 (int32x4_t)
2517
@*@emph{Form of expected instruction(s):} @code{vpaddl.s32 @var{q0}, @var{q0}}
2518
@end itemize
2519
 
2520
 
2521
@itemize @bullet
2522
@item int32x4_t vpaddlq_s16 (int16x8_t)
2523
@*@emph{Form of expected instruction(s):} @code{vpaddl.s16 @var{q0}, @var{q0}}
2524
@end itemize
2525
 
2526
 
2527
@itemize @bullet
2528
@item int16x8_t vpaddlq_s8 (int8x16_t)
2529
@*@emph{Form of expected instruction(s):} @code{vpaddl.s8 @var{q0}, @var{q0}}
2530
@end itemize
2531
 
2532
 
2533
 
2534
 
2535
@subsubsection Pairwise add, single_opcode widen and accumulate
2536
 
2537
@itemize @bullet
2538
@item uint64x1_t vpadal_u32 (uint64x1_t, uint32x2_t)
2539
@*@emph{Form of expected instruction(s):} @code{vpadal.u32 @var{d0}, @var{d0}}
2540
@end itemize
2541
 
2542
 
2543
@itemize @bullet
2544
@item uint32x2_t vpadal_u16 (uint32x2_t, uint16x4_t)
2545
@*@emph{Form of expected instruction(s):} @code{vpadal.u16 @var{d0}, @var{d0}}
2546
@end itemize
2547
 
2548
 
2549
@itemize @bullet
2550
@item uint16x4_t vpadal_u8 (uint16x4_t, uint8x8_t)
2551
@*@emph{Form of expected instruction(s):} @code{vpadal.u8 @var{d0}, @var{d0}}
2552
@end itemize
2553
 
2554
 
2555
@itemize @bullet
2556
@item int64x1_t vpadal_s32 (int64x1_t, int32x2_t)
2557
@*@emph{Form of expected instruction(s):} @code{vpadal.s32 @var{d0}, @var{d0}}
2558
@end itemize
2559
 
2560
 
2561
@itemize @bullet
2562
@item int32x2_t vpadal_s16 (int32x2_t, int16x4_t)
2563
@*@emph{Form of expected instruction(s):} @code{vpadal.s16 @var{d0}, @var{d0}}
2564
@end itemize
2565
 
2566
 
2567
@itemize @bullet
2568
@item int16x4_t vpadal_s8 (int16x4_t, int8x8_t)
2569
@*@emph{Form of expected instruction(s):} @code{vpadal.s8 @var{d0}, @var{d0}}
2570
@end itemize
2571
 
2572
 
2573
@itemize @bullet
2574
@item uint64x2_t vpadalq_u32 (uint64x2_t, uint32x4_t)
2575
@*@emph{Form of expected instruction(s):} @code{vpadal.u32 @var{q0}, @var{q0}}
2576
@end itemize
2577
 
2578
 
2579
@itemize @bullet
2580
@item uint32x4_t vpadalq_u16 (uint32x4_t, uint16x8_t)
2581
@*@emph{Form of expected instruction(s):} @code{vpadal.u16 @var{q0}, @var{q0}}
2582
@end itemize
2583
 
2584
 
2585
@itemize @bullet
2586
@item uint16x8_t vpadalq_u8 (uint16x8_t, uint8x16_t)
2587
@*@emph{Form of expected instruction(s):} @code{vpadal.u8 @var{q0}, @var{q0}}
2588
@end itemize
2589
 
2590
 
2591
@itemize @bullet
2592
@item int64x2_t vpadalq_s32 (int64x2_t, int32x4_t)
2593
@*@emph{Form of expected instruction(s):} @code{vpadal.s32 @var{q0}, @var{q0}}
2594
@end itemize
2595
 
2596
 
2597
@itemize @bullet
2598
@item int32x4_t vpadalq_s16 (int32x4_t, int16x8_t)
2599
@*@emph{Form of expected instruction(s):} @code{vpadal.s16 @var{q0}, @var{q0}}
2600
@end itemize
2601
 
2602
 
2603
@itemize @bullet
2604
@item int16x8_t vpadalq_s8 (int16x8_t, int8x16_t)
2605
@*@emph{Form of expected instruction(s):} @code{vpadal.s8 @var{q0}, @var{q0}}
2606
@end itemize
2607
 
2608
 
2609
 
2610
 
2611
@subsubsection Folding maximum
2612
 
2613
@itemize @bullet
2614
@item uint32x2_t vpmax_u32 (uint32x2_t, uint32x2_t)
2615
@*@emph{Form of expected instruction(s):} @code{vpmax.u32 @var{d0}, @var{d0}, @var{d0}}
2616
@end itemize
2617
 
2618
 
2619
@itemize @bullet
2620
@item uint16x4_t vpmax_u16 (uint16x4_t, uint16x4_t)
2621
@*@emph{Form of expected instruction(s):} @code{vpmax.u16 @var{d0}, @var{d0}, @var{d0}}
2622
@end itemize
2623
 
2624
 
2625
@itemize @bullet
2626
@item uint8x8_t vpmax_u8 (uint8x8_t, uint8x8_t)
2627
@*@emph{Form of expected instruction(s):} @code{vpmax.u8 @var{d0}, @var{d0}, @var{d0}}
2628
@end itemize
2629
 
2630
 
2631
@itemize @bullet
2632
@item int32x2_t vpmax_s32 (int32x2_t, int32x2_t)
2633
@*@emph{Form of expected instruction(s):} @code{vpmax.s32 @var{d0}, @var{d0}, @var{d0}}
2634
@end itemize
2635
 
2636
 
2637
@itemize @bullet
2638
@item int16x4_t vpmax_s16 (int16x4_t, int16x4_t)
2639
@*@emph{Form of expected instruction(s):} @code{vpmax.s16 @var{d0}, @var{d0}, @var{d0}}
2640
@end itemize
2641
 
2642
 
2643
@itemize @bullet
2644
@item int8x8_t vpmax_s8 (int8x8_t, int8x8_t)
2645
@*@emph{Form of expected instruction(s):} @code{vpmax.s8 @var{d0}, @var{d0}, @var{d0}}
2646
@end itemize
2647
 
2648
 
2649
@itemize @bullet
2650
@item float32x2_t vpmax_f32 (float32x2_t, float32x2_t)
2651
@*@emph{Form of expected instruction(s):} @code{vpmax.f32 @var{d0}, @var{d0}, @var{d0}}
2652
@end itemize
2653
 
2654
 
2655
 
2656
 
2657
@subsubsection Folding minimum
2658
 
2659
@itemize @bullet
2660
@item uint32x2_t vpmin_u32 (uint32x2_t, uint32x2_t)
2661
@*@emph{Form of expected instruction(s):} @code{vpmin.u32 @var{d0}, @var{d0}, @var{d0}}
2662
@end itemize
2663
 
2664
 
2665
@itemize @bullet
2666
@item uint16x4_t vpmin_u16 (uint16x4_t, uint16x4_t)
2667
@*@emph{Form of expected instruction(s):} @code{vpmin.u16 @var{d0}, @var{d0}, @var{d0}}
2668
@end itemize
2669
 
2670
 
2671
@itemize @bullet
2672
@item uint8x8_t vpmin_u8 (uint8x8_t, uint8x8_t)
2673
@*@emph{Form of expected instruction(s):} @code{vpmin.u8 @var{d0}, @var{d0}, @var{d0}}
2674
@end itemize
2675
 
2676
 
2677
@itemize @bullet
2678
@item int32x2_t vpmin_s32 (int32x2_t, int32x2_t)
2679
@*@emph{Form of expected instruction(s):} @code{vpmin.s32 @var{d0}, @var{d0}, @var{d0}}
2680
@end itemize
2681
 
2682
 
2683
@itemize @bullet
2684
@item int16x4_t vpmin_s16 (int16x4_t, int16x4_t)
2685
@*@emph{Form of expected instruction(s):} @code{vpmin.s16 @var{d0}, @var{d0}, @var{d0}}
2686
@end itemize
2687
 
2688
 
2689
@itemize @bullet
2690
@item int8x8_t vpmin_s8 (int8x8_t, int8x8_t)
2691
@*@emph{Form of expected instruction(s):} @code{vpmin.s8 @var{d0}, @var{d0}, @var{d0}}
2692
@end itemize
2693
 
2694
 
2695
@itemize @bullet
2696
@item float32x2_t vpmin_f32 (float32x2_t, float32x2_t)
2697
@*@emph{Form of expected instruction(s):} @code{vpmin.f32 @var{d0}, @var{d0}, @var{d0}}
2698
@end itemize
2699
 
2700
 
2701
 
2702
 
2703
@subsubsection Reciprocal step
2704
 
2705
@itemize @bullet
2706
@item float32x2_t vrecps_f32 (float32x2_t, float32x2_t)
2707
@*@emph{Form of expected instruction(s):} @code{vrecps.f32 @var{d0}, @var{d0}, @var{d0}}
2708
@end itemize
2709
 
2710
 
2711
@itemize @bullet
2712
@item float32x4_t vrecpsq_f32 (float32x4_t, float32x4_t)
2713
@*@emph{Form of expected instruction(s):} @code{vrecps.f32 @var{q0}, @var{q0}, @var{q0}}
2714
@end itemize
2715
 
2716
 
2717
@itemize @bullet
2718
@item float32x2_t vrsqrts_f32 (float32x2_t, float32x2_t)
2719
@*@emph{Form of expected instruction(s):} @code{vrsqrts.f32 @var{d0}, @var{d0}, @var{d0}}
2720
@end itemize
2721
 
2722
 
2723
@itemize @bullet
2724
@item float32x4_t vrsqrtsq_f32 (float32x4_t, float32x4_t)
2725
@*@emph{Form of expected instruction(s):} @code{vrsqrts.f32 @var{q0}, @var{q0}, @var{q0}}
2726
@end itemize
2727
 
2728
 
2729
 
2730
 
2731
@subsubsection Vector shift left
2732
 
2733
@itemize @bullet
2734
@item uint32x2_t vshl_u32 (uint32x2_t, int32x2_t)
2735
@*@emph{Form of expected instruction(s):} @code{vshl.u32 @var{d0}, @var{d0}, @var{d0}}
2736
@end itemize
2737
 
2738
 
2739
@itemize @bullet
2740
@item uint16x4_t vshl_u16 (uint16x4_t, int16x4_t)
2741
@*@emph{Form of expected instruction(s):} @code{vshl.u16 @var{d0}, @var{d0}, @var{d0}}
2742
@end itemize
2743
 
2744
 
2745
@itemize @bullet
2746
@item uint8x8_t vshl_u8 (uint8x8_t, int8x8_t)
2747
@*@emph{Form of expected instruction(s):} @code{vshl.u8 @var{d0}, @var{d0}, @var{d0}}
2748
@end itemize
2749
 
2750
 
2751
@itemize @bullet
2752
@item int32x2_t vshl_s32 (int32x2_t, int32x2_t)
2753
@*@emph{Form of expected instruction(s):} @code{vshl.s32 @var{d0}, @var{d0}, @var{d0}}
2754
@end itemize
2755
 
2756
 
2757
@itemize @bullet
2758
@item int16x4_t vshl_s16 (int16x4_t, int16x4_t)
2759
@*@emph{Form of expected instruction(s):} @code{vshl.s16 @var{d0}, @var{d0}, @var{d0}}
2760
@end itemize
2761
 
2762
 
2763
@itemize @bullet
2764
@item int8x8_t vshl_s8 (int8x8_t, int8x8_t)
2765
@*@emph{Form of expected instruction(s):} @code{vshl.s8 @var{d0}, @var{d0}, @var{d0}}
2766
@end itemize
2767
 
2768
 
2769
@itemize @bullet
2770
@item uint64x1_t vshl_u64 (uint64x1_t, int64x1_t)
2771
@*@emph{Form of expected instruction(s):} @code{vshl.u64 @var{d0}, @var{d0}, @var{d0}}
2772
@end itemize
2773
 
2774
 
2775
@itemize @bullet
2776
@item int64x1_t vshl_s64 (int64x1_t, int64x1_t)
2777
@*@emph{Form of expected instruction(s):} @code{vshl.s64 @var{d0}, @var{d0}, @var{d0}}
2778
@end itemize
2779
 
2780
 
2781
@itemize @bullet
2782
@item uint32x4_t vshlq_u32 (uint32x4_t, int32x4_t)
2783
@*@emph{Form of expected instruction(s):} @code{vshl.u32 @var{q0}, @var{q0}, @var{q0}}
2784
@end itemize
2785
 
2786
 
2787
@itemize @bullet
2788
@item uint16x8_t vshlq_u16 (uint16x8_t, int16x8_t)
2789
@*@emph{Form of expected instruction(s):} @code{vshl.u16 @var{q0}, @var{q0}, @var{q0}}
2790
@end itemize
2791
 
2792
 
2793
@itemize @bullet
2794
@item uint8x16_t vshlq_u8 (uint8x16_t, int8x16_t)
2795
@*@emph{Form of expected instruction(s):} @code{vshl.u8 @var{q0}, @var{q0}, @var{q0}}
2796
@end itemize
2797
 
2798
 
2799
@itemize @bullet
2800
@item int32x4_t vshlq_s32 (int32x4_t, int32x4_t)
2801
@*@emph{Form of expected instruction(s):} @code{vshl.s32 @var{q0}, @var{q0}, @var{q0}}
2802
@end itemize
2803
 
2804
 
2805
@itemize @bullet
2806
@item int16x8_t vshlq_s16 (int16x8_t, int16x8_t)
2807
@*@emph{Form of expected instruction(s):} @code{vshl.s16 @var{q0}, @var{q0}, @var{q0}}
2808
@end itemize
2809
 
2810
 
2811
@itemize @bullet
2812
@item int8x16_t vshlq_s8 (int8x16_t, int8x16_t)
2813
@*@emph{Form of expected instruction(s):} @code{vshl.s8 @var{q0}, @var{q0}, @var{q0}}
2814
@end itemize
2815
 
2816
 
2817
@itemize @bullet
2818
@item uint64x2_t vshlq_u64 (uint64x2_t, int64x2_t)
2819
@*@emph{Form of expected instruction(s):} @code{vshl.u64 @var{q0}, @var{q0}, @var{q0}}
2820
@end itemize
2821
 
2822
 
2823
@itemize @bullet
2824
@item int64x2_t vshlq_s64 (int64x2_t, int64x2_t)
2825
@*@emph{Form of expected instruction(s):} @code{vshl.s64 @var{q0}, @var{q0}, @var{q0}}
2826
@end itemize
2827
 
2828
 
2829
@itemize @bullet
2830
@item uint32x2_t vrshl_u32 (uint32x2_t, int32x2_t)
2831
@*@emph{Form of expected instruction(s):} @code{vrshl.u32 @var{d0}, @var{d0}, @var{d0}}
2832
@end itemize
2833
 
2834
 
2835
@itemize @bullet
2836
@item uint16x4_t vrshl_u16 (uint16x4_t, int16x4_t)
2837
@*@emph{Form of expected instruction(s):} @code{vrshl.u16 @var{d0}, @var{d0}, @var{d0}}
2838
@end itemize
2839
 
2840
 
2841
@itemize @bullet
2842
@item uint8x8_t vrshl_u8 (uint8x8_t, int8x8_t)
2843
@*@emph{Form of expected instruction(s):} @code{vrshl.u8 @var{d0}, @var{d0}, @var{d0}}
2844
@end itemize
2845
 
2846
 
2847
@itemize @bullet
2848
@item int32x2_t vrshl_s32 (int32x2_t, int32x2_t)
2849
@*@emph{Form of expected instruction(s):} @code{vrshl.s32 @var{d0}, @var{d0}, @var{d0}}
2850
@end itemize
2851
 
2852
 
2853
@itemize @bullet
2854
@item int16x4_t vrshl_s16 (int16x4_t, int16x4_t)
2855
@*@emph{Form of expected instruction(s):} @code{vrshl.s16 @var{d0}, @var{d0}, @var{d0}}
2856
@end itemize
2857
 
2858
 
2859
@itemize @bullet
2860
@item int8x8_t vrshl_s8 (int8x8_t, int8x8_t)
2861
@*@emph{Form of expected instruction(s):} @code{vrshl.s8 @var{d0}, @var{d0}, @var{d0}}
2862
@end itemize
2863
 
2864
 
2865
@itemize @bullet
2866
@item uint64x1_t vrshl_u64 (uint64x1_t, int64x1_t)
2867
@*@emph{Form of expected instruction(s):} @code{vrshl.u64 @var{d0}, @var{d0}, @var{d0}}
2868
@end itemize
2869
 
2870
 
2871
@itemize @bullet
2872
@item int64x1_t vrshl_s64 (int64x1_t, int64x1_t)
2873
@*@emph{Form of expected instruction(s):} @code{vrshl.s64 @var{d0}, @var{d0}, @var{d0}}
2874
@end itemize
2875
 
2876
 
2877
@itemize @bullet
2878
@item uint32x4_t vrshlq_u32 (uint32x4_t, int32x4_t)
2879
@*@emph{Form of expected instruction(s):} @code{vrshl.u32 @var{q0}, @var{q0}, @var{q0}}
2880
@end itemize
2881
 
2882
 
2883
@itemize @bullet
2884
@item uint16x8_t vrshlq_u16 (uint16x8_t, int16x8_t)
2885
@*@emph{Form of expected instruction(s):} @code{vrshl.u16 @var{q0}, @var{q0}, @var{q0}}
2886
@end itemize
2887
 
2888
 
2889
@itemize @bullet
2890
@item uint8x16_t vrshlq_u8 (uint8x16_t, int8x16_t)
2891
@*@emph{Form of expected instruction(s):} @code{vrshl.u8 @var{q0}, @var{q0}, @var{q0}}
2892
@end itemize
2893
 
2894
 
2895
@itemize @bullet
2896
@item int32x4_t vrshlq_s32 (int32x4_t, int32x4_t)
2897
@*@emph{Form of expected instruction(s):} @code{vrshl.s32 @var{q0}, @var{q0}, @var{q0}}
2898
@end itemize
2899
 
2900
 
2901
@itemize @bullet
2902
@item int16x8_t vrshlq_s16 (int16x8_t, int16x8_t)
2903
@*@emph{Form of expected instruction(s):} @code{vrshl.s16 @var{q0}, @var{q0}, @var{q0}}
2904
@end itemize
2905
 
2906
 
2907
@itemize @bullet
2908
@item int8x16_t vrshlq_s8 (int8x16_t, int8x16_t)
2909
@*@emph{Form of expected instruction(s):} @code{vrshl.s8 @var{q0}, @var{q0}, @var{q0}}
2910
@end itemize
2911
 
2912
 
2913
@itemize @bullet
2914
@item uint64x2_t vrshlq_u64 (uint64x2_t, int64x2_t)
2915
@*@emph{Form of expected instruction(s):} @code{vrshl.u64 @var{q0}, @var{q0}, @var{q0}}
2916
@end itemize
2917
 
2918
 
2919
@itemize @bullet
2920
@item int64x2_t vrshlq_s64 (int64x2_t, int64x2_t)
2921
@*@emph{Form of expected instruction(s):} @code{vrshl.s64 @var{q0}, @var{q0}, @var{q0}}
2922
@end itemize
2923
 
2924
 
2925
@itemize @bullet
2926
@item uint32x2_t vqshl_u32 (uint32x2_t, int32x2_t)
2927
@*@emph{Form of expected instruction(s):} @code{vqshl.u32 @var{d0}, @var{d0}, @var{d0}}
2928
@end itemize
2929
 
2930
 
2931
@itemize @bullet
2932
@item uint16x4_t vqshl_u16 (uint16x4_t, int16x4_t)
2933
@*@emph{Form of expected instruction(s):} @code{vqshl.u16 @var{d0}, @var{d0}, @var{d0}}
2934
@end itemize
2935
 
2936
 
2937
@itemize @bullet
2938
@item uint8x8_t vqshl_u8 (uint8x8_t, int8x8_t)
2939
@*@emph{Form of expected instruction(s):} @code{vqshl.u8 @var{d0}, @var{d0}, @var{d0}}
2940
@end itemize
2941
 
2942
 
2943
@itemize @bullet
2944
@item int32x2_t vqshl_s32 (int32x2_t, int32x2_t)
2945
@*@emph{Form of expected instruction(s):} @code{vqshl.s32 @var{d0}, @var{d0}, @var{d0}}
2946
@end itemize
2947
 
2948
 
2949
@itemize @bullet
2950
@item int16x4_t vqshl_s16 (int16x4_t, int16x4_t)
2951
@*@emph{Form of expected instruction(s):} @code{vqshl.s16 @var{d0}, @var{d0}, @var{d0}}
2952
@end itemize
2953
 
2954
 
2955
@itemize @bullet
2956
@item int8x8_t vqshl_s8 (int8x8_t, int8x8_t)
2957
@*@emph{Form of expected instruction(s):} @code{vqshl.s8 @var{d0}, @var{d0}, @var{d0}}
2958
@end itemize
2959
 
2960
 
2961
@itemize @bullet
2962
@item uint64x1_t vqshl_u64 (uint64x1_t, int64x1_t)
2963
@*@emph{Form of expected instruction(s):} @code{vqshl.u64 @var{d0}, @var{d0}, @var{d0}}
2964
@end itemize
2965
 
2966
 
2967
@itemize @bullet
2968
@item int64x1_t vqshl_s64 (int64x1_t, int64x1_t)
2969
@*@emph{Form of expected instruction(s):} @code{vqshl.s64 @var{d0}, @var{d0}, @var{d0}}
2970
@end itemize
2971
 
2972
 
2973
@itemize @bullet
2974
@item uint32x4_t vqshlq_u32 (uint32x4_t, int32x4_t)
2975
@*@emph{Form of expected instruction(s):} @code{vqshl.u32 @var{q0}, @var{q0}, @var{q0}}
2976
@end itemize
2977
 
2978
 
2979
@itemize @bullet
2980
@item uint16x8_t vqshlq_u16 (uint16x8_t, int16x8_t)
2981
@*@emph{Form of expected instruction(s):} @code{vqshl.u16 @var{q0}, @var{q0}, @var{q0}}
2982
@end itemize
2983
 
2984
 
2985
@itemize @bullet
2986
@item uint8x16_t vqshlq_u8 (uint8x16_t, int8x16_t)
2987
@*@emph{Form of expected instruction(s):} @code{vqshl.u8 @var{q0}, @var{q0}, @var{q0}}
2988
@end itemize
2989
 
2990
 
2991
@itemize @bullet
2992
@item int32x4_t vqshlq_s32 (int32x4_t, int32x4_t)
2993
@*@emph{Form of expected instruction(s):} @code{vqshl.s32 @var{q0}, @var{q0}, @var{q0}}
2994
@end itemize
2995
 
2996
 
2997
@itemize @bullet
2998
@item int16x8_t vqshlq_s16 (int16x8_t, int16x8_t)
2999
@*@emph{Form of expected instruction(s):} @code{vqshl.s16 @var{q0}, @var{q0}, @var{q0}}
3000
@end itemize
3001
 
3002
 
3003
@itemize @bullet
3004
@item int8x16_t vqshlq_s8 (int8x16_t, int8x16_t)
3005
@*@emph{Form of expected instruction(s):} @code{vqshl.s8 @var{q0}, @var{q0}, @var{q0}}
3006
@end itemize
3007
 
3008
 
3009
@itemize @bullet
3010
@item uint64x2_t vqshlq_u64 (uint64x2_t, int64x2_t)
3011
@*@emph{Form of expected instruction(s):} @code{vqshl.u64 @var{q0}, @var{q0}, @var{q0}}
3012
@end itemize
3013
 
3014
 
3015
@itemize @bullet
3016
@item int64x2_t vqshlq_s64 (int64x2_t, int64x2_t)
3017
@*@emph{Form of expected instruction(s):} @code{vqshl.s64 @var{q0}, @var{q0}, @var{q0}}
3018
@end itemize
3019
 
3020
 
3021
@itemize @bullet
3022
@item uint32x2_t vqrshl_u32 (uint32x2_t, int32x2_t)
3023
@*@emph{Form of expected instruction(s):} @code{vqrshl.u32 @var{d0}, @var{d0}, @var{d0}}
3024
@end itemize
3025
 
3026
 
3027
@itemize @bullet
3028
@item uint16x4_t vqrshl_u16 (uint16x4_t, int16x4_t)
3029
@*@emph{Form of expected instruction(s):} @code{vqrshl.u16 @var{d0}, @var{d0}, @var{d0}}
3030
@end itemize
3031
 
3032
 
3033
@itemize @bullet
3034
@item uint8x8_t vqrshl_u8 (uint8x8_t, int8x8_t)
3035
@*@emph{Form of expected instruction(s):} @code{vqrshl.u8 @var{d0}, @var{d0}, @var{d0}}
3036
@end itemize
3037
 
3038
 
3039
@itemize @bullet
3040
@item int32x2_t vqrshl_s32 (int32x2_t, int32x2_t)
3041
@*@emph{Form of expected instruction(s):} @code{vqrshl.s32 @var{d0}, @var{d0}, @var{d0}}
3042
@end itemize
3043
 
3044
 
3045
@itemize @bullet
3046
@item int16x4_t vqrshl_s16 (int16x4_t, int16x4_t)
3047
@*@emph{Form of expected instruction(s):} @code{vqrshl.s16 @var{d0}, @var{d0}, @var{d0}}
3048
@end itemize
3049
 
3050
 
3051
@itemize @bullet
3052
@item int8x8_t vqrshl_s8 (int8x8_t, int8x8_t)
3053
@*@emph{Form of expected instruction(s):} @code{vqrshl.s8 @var{d0}, @var{d0}, @var{d0}}
3054
@end itemize
3055
 
3056
 
3057
@itemize @bullet
3058
@item uint64x1_t vqrshl_u64 (uint64x1_t, int64x1_t)
3059
@*@emph{Form of expected instruction(s):} @code{vqrshl.u64 @var{d0}, @var{d0}, @var{d0}}
3060
@end itemize
3061
 
3062
 
3063
@itemize @bullet
3064
@item int64x1_t vqrshl_s64 (int64x1_t, int64x1_t)
3065
@*@emph{Form of expected instruction(s):} @code{vqrshl.s64 @var{d0}, @var{d0}, @var{d0}}
3066
@end itemize
3067
 
3068
 
3069
@itemize @bullet
3070
@item uint32x4_t vqrshlq_u32 (uint32x4_t, int32x4_t)
3071
@*@emph{Form of expected instruction(s):} @code{vqrshl.u32 @var{q0}, @var{q0}, @var{q0}}
3072
@end itemize
3073
 
3074
 
3075
@itemize @bullet
3076
@item uint16x8_t vqrshlq_u16 (uint16x8_t, int16x8_t)
3077
@*@emph{Form of expected instruction(s):} @code{vqrshl.u16 @var{q0}, @var{q0}, @var{q0}}
3078
@end itemize
3079
 
3080
 
3081
@itemize @bullet
3082
@item uint8x16_t vqrshlq_u8 (uint8x16_t, int8x16_t)
3083
@*@emph{Form of expected instruction(s):} @code{vqrshl.u8 @var{q0}, @var{q0}, @var{q0}}
3084
@end itemize
3085
 
3086
 
3087
@itemize @bullet
3088
@item int32x4_t vqrshlq_s32 (int32x4_t, int32x4_t)
3089
@*@emph{Form of expected instruction(s):} @code{vqrshl.s32 @var{q0}, @var{q0}, @var{q0}}
3090
@end itemize
3091
 
3092
 
3093
@itemize @bullet
3094
@item int16x8_t vqrshlq_s16 (int16x8_t, int16x8_t)
3095
@*@emph{Form of expected instruction(s):} @code{vqrshl.s16 @var{q0}, @var{q0}, @var{q0}}
3096
@end itemize
3097
 
3098
 
3099
@itemize @bullet
3100
@item int8x16_t vqrshlq_s8 (int8x16_t, int8x16_t)
3101
@*@emph{Form of expected instruction(s):} @code{vqrshl.s8 @var{q0}, @var{q0}, @var{q0}}
3102
@end itemize
3103
 
3104
 
3105
@itemize @bullet
3106
@item uint64x2_t vqrshlq_u64 (uint64x2_t, int64x2_t)
3107
@*@emph{Form of expected instruction(s):} @code{vqrshl.u64 @var{q0}, @var{q0}, @var{q0}}
3108
@end itemize
3109
 
3110
 
3111
@itemize @bullet
3112
@item int64x2_t vqrshlq_s64 (int64x2_t, int64x2_t)
3113
@*@emph{Form of expected instruction(s):} @code{vqrshl.s64 @var{q0}, @var{q0}, @var{q0}}
3114
@end itemize
3115
 
3116
 
3117
 
3118
 
3119
@subsubsection Vector shift left by constant
3120
 
3121
@itemize @bullet
3122
@item uint32x2_t vshl_n_u32 (uint32x2_t, const int)
3123
@*@emph{Form of expected instruction(s):} @code{vshl.i32 @var{d0}, @var{d0}, #@var{0}}
3124
@end itemize
3125
 
3126
 
3127
@itemize @bullet
3128
@item uint16x4_t vshl_n_u16 (uint16x4_t, const int)
3129
@*@emph{Form of expected instruction(s):} @code{vshl.i16 @var{d0}, @var{d0}, #@var{0}}
3130
@end itemize
3131
 
3132
 
3133
@itemize @bullet
3134
@item uint8x8_t vshl_n_u8 (uint8x8_t, const int)
3135
@*@emph{Form of expected instruction(s):} @code{vshl.i8 @var{d0}, @var{d0}, #@var{0}}
3136
@end itemize
3137
 
3138
 
3139
@itemize @bullet
3140
@item int32x2_t vshl_n_s32 (int32x2_t, const int)
3141
@*@emph{Form of expected instruction(s):} @code{vshl.i32 @var{d0}, @var{d0}, #@var{0}}
3142
@end itemize
3143
 
3144
 
3145
@itemize @bullet
3146
@item int16x4_t vshl_n_s16 (int16x4_t, const int)
3147
@*@emph{Form of expected instruction(s):} @code{vshl.i16 @var{d0}, @var{d0}, #@var{0}}
3148
@end itemize
3149
 
3150
 
3151
@itemize @bullet
3152
@item int8x8_t vshl_n_s8 (int8x8_t, const int)
3153
@*@emph{Form of expected instruction(s):} @code{vshl.i8 @var{d0}, @var{d0}, #@var{0}}
3154
@end itemize
3155
 
3156
 
3157
@itemize @bullet
3158
@item uint64x1_t vshl_n_u64 (uint64x1_t, const int)
3159
@*@emph{Form of expected instruction(s):} @code{vshl.i64 @var{d0}, @var{d0}, #@var{0}}
3160
@end itemize
3161
 
3162
 
3163
@itemize @bullet
3164
@item int64x1_t vshl_n_s64 (int64x1_t, const int)
3165
@*@emph{Form of expected instruction(s):} @code{vshl.i64 @var{d0}, @var{d0}, #@var{0}}
3166
@end itemize
3167
 
3168
 
3169
@itemize @bullet
3170
@item uint32x4_t vshlq_n_u32 (uint32x4_t, const int)
3171
@*@emph{Form of expected instruction(s):} @code{vshl.i32 @var{q0}, @var{q0}, #@var{0}}
3172
@end itemize
3173
 
3174
 
3175
@itemize @bullet
3176
@item uint16x8_t vshlq_n_u16 (uint16x8_t, const int)
3177
@*@emph{Form of expected instruction(s):} @code{vshl.i16 @var{q0}, @var{q0}, #@var{0}}
3178
@end itemize
3179
 
3180
 
3181
@itemize @bullet
3182
@item uint8x16_t vshlq_n_u8 (uint8x16_t, const int)
3183
@*@emph{Form of expected instruction(s):} @code{vshl.i8 @var{q0}, @var{q0}, #@var{0}}
3184
@end itemize
3185
 
3186
 
3187
@itemize @bullet
3188
@item int32x4_t vshlq_n_s32 (int32x4_t, const int)
3189
@*@emph{Form of expected instruction(s):} @code{vshl.i32 @var{q0}, @var{q0}, #@var{0}}
3190
@end itemize
3191
 
3192
 
3193
@itemize @bullet
3194
@item int16x8_t vshlq_n_s16 (int16x8_t, const int)
3195
@*@emph{Form of expected instruction(s):} @code{vshl.i16 @var{q0}, @var{q0}, #@var{0}}
3196
@end itemize
3197
 
3198
 
3199
@itemize @bullet
3200
@item int8x16_t vshlq_n_s8 (int8x16_t, const int)
3201
@*@emph{Form of expected instruction(s):} @code{vshl.i8 @var{q0}, @var{q0}, #@var{0}}
3202
@end itemize
3203
 
3204
 
3205
@itemize @bullet
3206
@item uint64x2_t vshlq_n_u64 (uint64x2_t, const int)
3207
@*@emph{Form of expected instruction(s):} @code{vshl.i64 @var{q0}, @var{q0}, #@var{0}}
3208
@end itemize
3209
 
3210
 
3211
@itemize @bullet
3212
@item int64x2_t vshlq_n_s64 (int64x2_t, const int)
3213
@*@emph{Form of expected instruction(s):} @code{vshl.i64 @var{q0}, @var{q0}, #@var{0}}
3214
@end itemize
3215
 
3216
 
3217
@itemize @bullet
3218
@item uint32x2_t vqshl_n_u32 (uint32x2_t, const int)
3219
@*@emph{Form of expected instruction(s):} @code{vqshl.u32 @var{d0}, @var{d0}, #@var{0}}
3220
@end itemize
3221
 
3222
 
3223
@itemize @bullet
3224
@item uint16x4_t vqshl_n_u16 (uint16x4_t, const int)
3225
@*@emph{Form of expected instruction(s):} @code{vqshl.u16 @var{d0}, @var{d0}, #@var{0}}
3226
@end itemize
3227
 
3228
 
3229
@itemize @bullet
3230
@item uint8x8_t vqshl_n_u8 (uint8x8_t, const int)
3231
@*@emph{Form of expected instruction(s):} @code{vqshl.u8 @var{d0}, @var{d0}, #@var{0}}
3232
@end itemize
3233
 
3234
 
3235
@itemize @bullet
3236
@item int32x2_t vqshl_n_s32 (int32x2_t, const int)
3237
@*@emph{Form of expected instruction(s):} @code{vqshl.s32 @var{d0}, @var{d0}, #@var{0}}
3238
@end itemize
3239
 
3240
 
3241
@itemize @bullet
3242
@item int16x4_t vqshl_n_s16 (int16x4_t, const int)
3243
@*@emph{Form of expected instruction(s):} @code{vqshl.s16 @var{d0}, @var{d0}, #@var{0}}
3244
@end itemize
3245
 
3246
 
3247
@itemize @bullet
3248
@item int8x8_t vqshl_n_s8 (int8x8_t, const int)
3249
@*@emph{Form of expected instruction(s):} @code{vqshl.s8 @var{d0}, @var{d0}, #@var{0}}
3250
@end itemize
3251
 
3252
 
3253
@itemize @bullet
3254
@item uint64x1_t vqshl_n_u64 (uint64x1_t, const int)
3255
@*@emph{Form of expected instruction(s):} @code{vqshl.u64 @var{d0}, @var{d0}, #@var{0}}
3256
@end itemize
3257
 
3258
 
3259
@itemize @bullet
3260
@item int64x1_t vqshl_n_s64 (int64x1_t, const int)
3261
@*@emph{Form of expected instruction(s):} @code{vqshl.s64 @var{d0}, @var{d0}, #@var{0}}
3262
@end itemize
3263
 
3264
 
3265
@itemize @bullet
3266
@item uint32x4_t vqshlq_n_u32 (uint32x4_t, const int)
3267
@*@emph{Form of expected instruction(s):} @code{vqshl.u32 @var{q0}, @var{q0}, #@var{0}}
3268
@end itemize
3269
 
3270
 
3271
@itemize @bullet
3272
@item uint16x8_t vqshlq_n_u16 (uint16x8_t, const int)
3273
@*@emph{Form of expected instruction(s):} @code{vqshl.u16 @var{q0}, @var{q0}, #@var{0}}
3274
@end itemize
3275
 
3276
 
3277
@itemize @bullet
3278
@item uint8x16_t vqshlq_n_u8 (uint8x16_t, const int)
3279
@*@emph{Form of expected instruction(s):} @code{vqshl.u8 @var{q0}, @var{q0}, #@var{0}}
3280
@end itemize
3281
 
3282
 
3283
@itemize @bullet
3284
@item int32x4_t vqshlq_n_s32 (int32x4_t, const int)
3285
@*@emph{Form of expected instruction(s):} @code{vqshl.s32 @var{q0}, @var{q0}, #@var{0}}
3286
@end itemize
3287
 
3288
 
3289
@itemize @bullet
3290
@item int16x8_t vqshlq_n_s16 (int16x8_t, const int)
3291
@*@emph{Form of expected instruction(s):} @code{vqshl.s16 @var{q0}, @var{q0}, #@var{0}}
3292
@end itemize
3293
 
3294
 
3295
@itemize @bullet
3296
@item int8x16_t vqshlq_n_s8 (int8x16_t, const int)
3297
@*@emph{Form of expected instruction(s):} @code{vqshl.s8 @var{q0}, @var{q0}, #@var{0}}
3298
@end itemize
3299
 
3300
 
3301
@itemize @bullet
3302
@item uint64x2_t vqshlq_n_u64 (uint64x2_t, const int)
3303
@*@emph{Form of expected instruction(s):} @code{vqshl.u64 @var{q0}, @var{q0}, #@var{0}}
3304
@end itemize
3305
 
3306
 
3307
@itemize @bullet
3308
@item int64x2_t vqshlq_n_s64 (int64x2_t, const int)
3309
@*@emph{Form of expected instruction(s):} @code{vqshl.s64 @var{q0}, @var{q0}, #@var{0}}
3310
@end itemize
3311
 
3312
 
3313
@itemize @bullet
3314
@item uint64x1_t vqshlu_n_s64 (int64x1_t, const int)
3315
@*@emph{Form of expected instruction(s):} @code{vqshlu.s64 @var{d0}, @var{d0}, #@var{0}}
3316
@end itemize
3317
 
3318
 
3319
@itemize @bullet
3320
@item uint32x2_t vqshlu_n_s32 (int32x2_t, const int)
3321
@*@emph{Form of expected instruction(s):} @code{vqshlu.s32 @var{d0}, @var{d0}, #@var{0}}
3322
@end itemize
3323
 
3324
 
3325
@itemize @bullet
3326
@item uint16x4_t vqshlu_n_s16 (int16x4_t, const int)
3327
@*@emph{Form of expected instruction(s):} @code{vqshlu.s16 @var{d0}, @var{d0}, #@var{0}}
3328
@end itemize
3329
 
3330
 
3331
@itemize @bullet
3332
@item uint8x8_t vqshlu_n_s8 (int8x8_t, const int)
3333
@*@emph{Form of expected instruction(s):} @code{vqshlu.s8 @var{d0}, @var{d0}, #@var{0}}
3334
@end itemize
3335
 
3336
 
3337
@itemize @bullet
3338
@item uint64x2_t vqshluq_n_s64 (int64x2_t, const int)
3339
@*@emph{Form of expected instruction(s):} @code{vqshlu.s64 @var{q0}, @var{q0}, #@var{0}}
3340
@end itemize
3341
 
3342
 
3343
@itemize @bullet
3344
@item uint32x4_t vqshluq_n_s32 (int32x4_t, const int)
3345
@*@emph{Form of expected instruction(s):} @code{vqshlu.s32 @var{q0}, @var{q0}, #@var{0}}
3346
@end itemize
3347
 
3348
 
3349
@itemize @bullet
3350
@item uint16x8_t vqshluq_n_s16 (int16x8_t, const int)
3351
@*@emph{Form of expected instruction(s):} @code{vqshlu.s16 @var{q0}, @var{q0}, #@var{0}}
3352
@end itemize
3353
 
3354
 
3355
@itemize @bullet
3356
@item uint8x16_t vqshluq_n_s8 (int8x16_t, const int)
3357
@*@emph{Form of expected instruction(s):} @code{vqshlu.s8 @var{q0}, @var{q0}, #@var{0}}
3358
@end itemize
3359
 
3360
 
3361
@itemize @bullet
3362
@item uint64x2_t vshll_n_u32 (uint32x2_t, const int)
3363
@*@emph{Form of expected instruction(s):} @code{vshll.u32 @var{q0}, @var{d0}, #@var{0}}
3364
@end itemize
3365
 
3366
 
3367
@itemize @bullet
3368
@item uint32x4_t vshll_n_u16 (uint16x4_t, const int)
3369
@*@emph{Form of expected instruction(s):} @code{vshll.u16 @var{q0}, @var{d0}, #@var{0}}
3370
@end itemize
3371
 
3372
 
3373
@itemize @bullet
3374
@item uint16x8_t vshll_n_u8 (uint8x8_t, const int)
3375
@*@emph{Form of expected instruction(s):} @code{vshll.u8 @var{q0}, @var{d0}, #@var{0}}
3376
@end itemize
3377
 
3378
 
3379
@itemize @bullet
3380
@item int64x2_t vshll_n_s32 (int32x2_t, const int)
3381
@*@emph{Form of expected instruction(s):} @code{vshll.s32 @var{q0}, @var{d0}, #@var{0}}
3382
@end itemize
3383
 
3384
 
3385
@itemize @bullet
3386
@item int32x4_t vshll_n_s16 (int16x4_t, const int)
3387
@*@emph{Form of expected instruction(s):} @code{vshll.s16 @var{q0}, @var{d0}, #@var{0}}
3388
@end itemize
3389
 
3390
 
3391
@itemize @bullet
3392
@item int16x8_t vshll_n_s8 (int8x8_t, const int)
3393
@*@emph{Form of expected instruction(s):} @code{vshll.s8 @var{q0}, @var{d0}, #@var{0}}
3394
@end itemize
3395
 
3396
 
3397
 
3398
 
3399
@subsubsection Vector shift right by constant
3400
 
3401
@itemize @bullet
3402
@item uint32x2_t vshr_n_u32 (uint32x2_t, const int)
3403
@*@emph{Form of expected instruction(s):} @code{vshr.u32 @var{d0}, @var{d0}, #@var{0}}
3404
@end itemize
3405
 
3406
 
3407
@itemize @bullet
3408
@item uint16x4_t vshr_n_u16 (uint16x4_t, const int)
3409
@*@emph{Form of expected instruction(s):} @code{vshr.u16 @var{d0}, @var{d0}, #@var{0}}
3410
@end itemize
3411
 
3412
 
3413
@itemize @bullet
3414
@item uint8x8_t vshr_n_u8 (uint8x8_t, const int)
3415
@*@emph{Form of expected instruction(s):} @code{vshr.u8 @var{d0}, @var{d0}, #@var{0}}
3416
@end itemize
3417
 
3418
 
3419
@itemize @bullet
3420
@item int32x2_t vshr_n_s32 (int32x2_t, const int)
3421
@*@emph{Form of expected instruction(s):} @code{vshr.s32 @var{d0}, @var{d0}, #@var{0}}
3422
@end itemize
3423
 
3424
 
3425
@itemize @bullet
3426
@item int16x4_t vshr_n_s16 (int16x4_t, const int)
3427
@*@emph{Form of expected instruction(s):} @code{vshr.s16 @var{d0}, @var{d0}, #@var{0}}
3428
@end itemize
3429
 
3430
 
3431
@itemize @bullet
3432
@item int8x8_t vshr_n_s8 (int8x8_t, const int)
3433
@*@emph{Form of expected instruction(s):} @code{vshr.s8 @var{d0}, @var{d0}, #@var{0}}
3434
@end itemize
3435
 
3436
 
3437
@itemize @bullet
3438
@item uint64x1_t vshr_n_u64 (uint64x1_t, const int)
3439
@*@emph{Form of expected instruction(s):} @code{vshr.u64 @var{d0}, @var{d0}, #@var{0}}
3440
@end itemize
3441
 
3442
 
3443
@itemize @bullet
3444
@item int64x1_t vshr_n_s64 (int64x1_t, const int)
3445
@*@emph{Form of expected instruction(s):} @code{vshr.s64 @var{d0}, @var{d0}, #@var{0}}
3446
@end itemize
3447
 
3448
 
3449
@itemize @bullet
3450
@item uint32x4_t vshrq_n_u32 (uint32x4_t, const int)
3451
@*@emph{Form of expected instruction(s):} @code{vshr.u32 @var{q0}, @var{q0}, #@var{0}}
3452
@end itemize
3453
 
3454
 
3455
@itemize @bullet
3456
@item uint16x8_t vshrq_n_u16 (uint16x8_t, const int)
3457
@*@emph{Form of expected instruction(s):} @code{vshr.u16 @var{q0}, @var{q0}, #@var{0}}
3458
@end itemize
3459
 
3460
 
3461
@itemize @bullet
3462
@item uint8x16_t vshrq_n_u8 (uint8x16_t, const int)
3463
@*@emph{Form of expected instruction(s):} @code{vshr.u8 @var{q0}, @var{q0}, #@var{0}}
3464
@end itemize
3465
 
3466
 
3467
@itemize @bullet
3468
@item int32x4_t vshrq_n_s32 (int32x4_t, const int)
3469
@*@emph{Form of expected instruction(s):} @code{vshr.s32 @var{q0}, @var{q0}, #@var{0}}
3470
@end itemize
3471
 
3472
 
3473
@itemize @bullet
3474
@item int16x8_t vshrq_n_s16 (int16x8_t, const int)
3475
@*@emph{Form of expected instruction(s):} @code{vshr.s16 @var{q0}, @var{q0}, #@var{0}}
3476
@end itemize
3477
 
3478
 
3479
@itemize @bullet
3480
@item int8x16_t vshrq_n_s8 (int8x16_t, const int)
3481
@*@emph{Form of expected instruction(s):} @code{vshr.s8 @var{q0}, @var{q0}, #@var{0}}
3482
@end itemize
3483
 
3484
 
3485
@itemize @bullet
3486
@item uint64x2_t vshrq_n_u64 (uint64x2_t, const int)
3487
@*@emph{Form of expected instruction(s):} @code{vshr.u64 @var{q0}, @var{q0}, #@var{0}}
3488
@end itemize
3489
 
3490
 
3491
@itemize @bullet
3492
@item int64x2_t vshrq_n_s64 (int64x2_t, const int)
3493
@*@emph{Form of expected instruction(s):} @code{vshr.s64 @var{q0}, @var{q0}, #@var{0}}
3494
@end itemize
3495
 
3496
 
3497
@itemize @bullet
3498
@item uint32x2_t vrshr_n_u32 (uint32x2_t, const int)
3499
@*@emph{Form of expected instruction(s):} @code{vrshr.u32 @var{d0}, @var{d0}, #@var{0}}
3500
@end itemize
3501
 
3502
 
3503
@itemize @bullet
3504
@item uint16x4_t vrshr_n_u16 (uint16x4_t, const int)
3505
@*@emph{Form of expected instruction(s):} @code{vrshr.u16 @var{d0}, @var{d0}, #@var{0}}
3506
@end itemize
3507
 
3508
 
3509
@itemize @bullet
3510
@item uint8x8_t vrshr_n_u8 (uint8x8_t, const int)
3511
@*@emph{Form of expected instruction(s):} @code{vrshr.u8 @var{d0}, @var{d0}, #@var{0}}
3512
@end itemize
3513
 
3514
 
3515
@itemize @bullet
3516
@item int32x2_t vrshr_n_s32 (int32x2_t, const int)
3517
@*@emph{Form of expected instruction(s):} @code{vrshr.s32 @var{d0}, @var{d0}, #@var{0}}
3518
@end itemize
3519
 
3520
 
3521
@itemize @bullet
3522
@item int16x4_t vrshr_n_s16 (int16x4_t, const int)
3523
@*@emph{Form of expected instruction(s):} @code{vrshr.s16 @var{d0}, @var{d0}, #@var{0}}
3524
@end itemize
3525
 
3526
 
3527
@itemize @bullet
3528
@item int8x8_t vrshr_n_s8 (int8x8_t, const int)
3529
@*@emph{Form of expected instruction(s):} @code{vrshr.s8 @var{d0}, @var{d0}, #@var{0}}
3530
@end itemize
3531
 
3532
 
3533
@itemize @bullet
3534
@item uint64x1_t vrshr_n_u64 (uint64x1_t, const int)
3535
@*@emph{Form of expected instruction(s):} @code{vrshr.u64 @var{d0}, @var{d0}, #@var{0}}
3536
@end itemize
3537
 
3538
 
3539
@itemize @bullet
3540
@item int64x1_t vrshr_n_s64 (int64x1_t, const int)
3541
@*@emph{Form of expected instruction(s):} @code{vrshr.s64 @var{d0}, @var{d0}, #@var{0}}
3542
@end itemize
3543
 
3544
 
3545
@itemize @bullet
3546
@item uint32x4_t vrshrq_n_u32 (uint32x4_t, const int)
3547
@*@emph{Form of expected instruction(s):} @code{vrshr.u32 @var{q0}, @var{q0}, #@var{0}}
3548
@end itemize
3549
 
3550
 
3551
@itemize @bullet
3552
@item uint16x8_t vrshrq_n_u16 (uint16x8_t, const int)
3553
@*@emph{Form of expected instruction(s):} @code{vrshr.u16 @var{q0}, @var{q0}, #@var{0}}
3554
@end itemize
3555
 
3556
 
3557
@itemize @bullet
3558
@item uint8x16_t vrshrq_n_u8 (uint8x16_t, const int)
3559
@*@emph{Form of expected instruction(s):} @code{vrshr.u8 @var{q0}, @var{q0}, #@var{0}}
3560
@end itemize
3561
 
3562
 
3563
@itemize @bullet
3564
@item int32x4_t vrshrq_n_s32 (int32x4_t, const int)
3565
@*@emph{Form of expected instruction(s):} @code{vrshr.s32 @var{q0}, @var{q0}, #@var{0}}
3566
@end itemize
3567
 
3568
 
3569
@itemize @bullet
3570
@item int16x8_t vrshrq_n_s16 (int16x8_t, const int)
3571
@*@emph{Form of expected instruction(s):} @code{vrshr.s16 @var{q0}, @var{q0}, #@var{0}}
3572
@end itemize
3573
 
3574
 
3575
@itemize @bullet
3576
@item int8x16_t vrshrq_n_s8 (int8x16_t, const int)
3577
@*@emph{Form of expected instruction(s):} @code{vrshr.s8 @var{q0}, @var{q0}, #@var{0}}
3578
@end itemize
3579
 
3580
 
3581
@itemize @bullet
3582
@item uint64x2_t vrshrq_n_u64 (uint64x2_t, const int)
3583
@*@emph{Form of expected instruction(s):} @code{vrshr.u64 @var{q0}, @var{q0}, #@var{0}}
3584
@end itemize
3585
 
3586
 
3587
@itemize @bullet
3588
@item int64x2_t vrshrq_n_s64 (int64x2_t, const int)
3589
@*@emph{Form of expected instruction(s):} @code{vrshr.s64 @var{q0}, @var{q0}, #@var{0}}
3590
@end itemize
3591
 
3592
 
3593
@itemize @bullet
3594
@item uint32x2_t vshrn_n_u64 (uint64x2_t, const int)
3595
@*@emph{Form of expected instruction(s):} @code{vshrn.i64 @var{d0}, @var{q0}, #@var{0}}
3596
@end itemize
3597
 
3598
 
3599
@itemize @bullet
3600
@item uint16x4_t vshrn_n_u32 (uint32x4_t, const int)
3601
@*@emph{Form of expected instruction(s):} @code{vshrn.i32 @var{d0}, @var{q0}, #@var{0}}
3602
@end itemize
3603
 
3604
 
3605
@itemize @bullet
3606
@item uint8x8_t vshrn_n_u16 (uint16x8_t, const int)
3607
@*@emph{Form of expected instruction(s):} @code{vshrn.i16 @var{d0}, @var{q0}, #@var{0}}
3608
@end itemize
3609
 
3610
 
3611
@itemize @bullet
3612
@item int32x2_t vshrn_n_s64 (int64x2_t, const int)
3613
@*@emph{Form of expected instruction(s):} @code{vshrn.i64 @var{d0}, @var{q0}, #@var{0}}
3614
@end itemize
3615
 
3616
 
3617
@itemize @bullet
3618
@item int16x4_t vshrn_n_s32 (int32x4_t, const int)
3619
@*@emph{Form of expected instruction(s):} @code{vshrn.i32 @var{d0}, @var{q0}, #@var{0}}
3620
@end itemize
3621
 
3622
 
3623
@itemize @bullet
3624
@item int8x8_t vshrn_n_s16 (int16x8_t, const int)
3625
@*@emph{Form of expected instruction(s):} @code{vshrn.i16 @var{d0}, @var{q0}, #@var{0}}
3626
@end itemize
3627
 
3628
 
3629
@itemize @bullet
3630
@item uint32x2_t vrshrn_n_u64 (uint64x2_t, const int)
3631
@*@emph{Form of expected instruction(s):} @code{vrshrn.i64 @var{d0}, @var{q0}, #@var{0}}
3632
@end itemize
3633
 
3634
 
3635
@itemize @bullet
3636
@item uint16x4_t vrshrn_n_u32 (uint32x4_t, const int)
3637
@*@emph{Form of expected instruction(s):} @code{vrshrn.i32 @var{d0}, @var{q0}, #@var{0}}
3638
@end itemize
3639
 
3640
 
3641
@itemize @bullet
3642
@item uint8x8_t vrshrn_n_u16 (uint16x8_t, const int)
3643
@*@emph{Form of expected instruction(s):} @code{vrshrn.i16 @var{d0}, @var{q0}, #@var{0}}
3644
@end itemize
3645
 
3646
 
3647
@itemize @bullet
3648
@item int32x2_t vrshrn_n_s64 (int64x2_t, const int)
3649
@*@emph{Form of expected instruction(s):} @code{vrshrn.i64 @var{d0}, @var{q0}, #@var{0}}
3650
@end itemize
3651
 
3652
 
3653
@itemize @bullet
3654
@item int16x4_t vrshrn_n_s32 (int32x4_t, const int)
3655
@*@emph{Form of expected instruction(s):} @code{vrshrn.i32 @var{d0}, @var{q0}, #@var{0}}
3656
@end itemize
3657
 
3658
 
3659
@itemize @bullet
3660
@item int8x8_t vrshrn_n_s16 (int16x8_t, const int)
3661
@*@emph{Form of expected instruction(s):} @code{vrshrn.i16 @var{d0}, @var{q0}, #@var{0}}
3662
@end itemize
3663
 
3664
 
3665
@itemize @bullet
3666
@item uint32x2_t vqshrn_n_u64 (uint64x2_t, const int)
3667
@*@emph{Form of expected instruction(s):} @code{vqshrn.u64 @var{d0}, @var{q0}, #@var{0}}
3668
@end itemize
3669
 
3670
 
3671
@itemize @bullet
3672
@item uint16x4_t vqshrn_n_u32 (uint32x4_t, const int)
3673
@*@emph{Form of expected instruction(s):} @code{vqshrn.u32 @var{d0}, @var{q0}, #@var{0}}
3674
@end itemize
3675
 
3676
 
3677
@itemize @bullet
3678
@item uint8x8_t vqshrn_n_u16 (uint16x8_t, const int)
3679
@*@emph{Form of expected instruction(s):} @code{vqshrn.u16 @var{d0}, @var{q0}, #@var{0}}
3680
@end itemize
3681
 
3682
 
3683
@itemize @bullet
3684
@item int32x2_t vqshrn_n_s64 (int64x2_t, const int)
3685
@*@emph{Form of expected instruction(s):} @code{vqshrn.s64 @var{d0}, @var{q0}, #@var{0}}
3686
@end itemize
3687
 
3688
 
3689
@itemize @bullet
3690
@item int16x4_t vqshrn_n_s32 (int32x4_t, const int)
3691
@*@emph{Form of expected instruction(s):} @code{vqshrn.s32 @var{d0}, @var{q0}, #@var{0}}
3692
@end itemize
3693
 
3694
 
3695
@itemize @bullet
3696
@item int8x8_t vqshrn_n_s16 (int16x8_t, const int)
3697
@*@emph{Form of expected instruction(s):} @code{vqshrn.s16 @var{d0}, @var{q0}, #@var{0}}
3698
@end itemize
3699
 
3700
 
3701
@itemize @bullet
3702
@item uint32x2_t vqrshrn_n_u64 (uint64x2_t, const int)
3703
@*@emph{Form of expected instruction(s):} @code{vqrshrn.u64 @var{d0}, @var{q0}, #@var{0}}
3704
@end itemize
3705
 
3706
 
3707
@itemize @bullet
3708
@item uint16x4_t vqrshrn_n_u32 (uint32x4_t, const int)
3709
@*@emph{Form of expected instruction(s):} @code{vqrshrn.u32 @var{d0}, @var{q0}, #@var{0}}
3710
@end itemize
3711
 
3712
 
3713
@itemize @bullet
3714
@item uint8x8_t vqrshrn_n_u16 (uint16x8_t, const int)
3715
@*@emph{Form of expected instruction(s):} @code{vqrshrn.u16 @var{d0}, @var{q0}, #@var{0}}
3716
@end itemize
3717
 
3718
 
3719
@itemize @bullet
3720
@item int32x2_t vqrshrn_n_s64 (int64x2_t, const int)
3721
@*@emph{Form of expected instruction(s):} @code{vqrshrn.s64 @var{d0}, @var{q0}, #@var{0}}
3722
@end itemize
3723
 
3724
 
3725
@itemize @bullet
3726
@item int16x4_t vqrshrn_n_s32 (int32x4_t, const int)
3727
@*@emph{Form of expected instruction(s):} @code{vqrshrn.s32 @var{d0}, @var{q0}, #@var{0}}
3728
@end itemize
3729
 
3730
 
3731
@itemize @bullet
3732
@item int8x8_t vqrshrn_n_s16 (int16x8_t, const int)
3733
@*@emph{Form of expected instruction(s):} @code{vqrshrn.s16 @var{d0}, @var{q0}, #@var{0}}
3734
@end itemize
3735
 
3736
 
3737
@itemize @bullet
3738
@item uint32x2_t vqshrun_n_s64 (int64x2_t, const int)
3739
@*@emph{Form of expected instruction(s):} @code{vqshrun.s64 @var{d0}, @var{q0}, #@var{0}}
3740
@end itemize
3741
 
3742
 
3743
@itemize @bullet
3744
@item uint16x4_t vqshrun_n_s32 (int32x4_t, const int)
3745
@*@emph{Form of expected instruction(s):} @code{vqshrun.s32 @var{d0}, @var{q0}, #@var{0}}
3746
@end itemize
3747
 
3748
 
3749
@itemize @bullet
3750
@item uint8x8_t vqshrun_n_s16 (int16x8_t, const int)
3751
@*@emph{Form of expected instruction(s):} @code{vqshrun.s16 @var{d0}, @var{q0}, #@var{0}}
3752
@end itemize
3753
 
3754
 
3755
@itemize @bullet
3756
@item uint32x2_t vqrshrun_n_s64 (int64x2_t, const int)
3757
@*@emph{Form of expected instruction(s):} @code{vqrshrun.s64 @var{d0}, @var{q0}, #@var{0}}
3758
@end itemize
3759
 
3760
 
3761
@itemize @bullet
3762
@item uint16x4_t vqrshrun_n_s32 (int32x4_t, const int)
3763
@*@emph{Form of expected instruction(s):} @code{vqrshrun.s32 @var{d0}, @var{q0}, #@var{0}}
3764
@end itemize
3765
 
3766
 
3767
@itemize @bullet
3768
@item uint8x8_t vqrshrun_n_s16 (int16x8_t, const int)
3769
@*@emph{Form of expected instruction(s):} @code{vqrshrun.s16 @var{d0}, @var{q0}, #@var{0}}
3770
@end itemize
3771
 
3772
 
3773
 
3774
 
3775
@subsubsection Vector shift right by constant and accumulate
3776
 
3777
@itemize @bullet
3778
@item uint32x2_t vsra_n_u32 (uint32x2_t, uint32x2_t, const int)
3779
@*@emph{Form of expected instruction(s):} @code{vsra.u32 @var{d0}, @var{d0}, #@var{0}}
3780
@end itemize
3781
 
3782
 
3783
@itemize @bullet
3784
@item uint16x4_t vsra_n_u16 (uint16x4_t, uint16x4_t, const int)
3785
@*@emph{Form of expected instruction(s):} @code{vsra.u16 @var{d0}, @var{d0}, #@var{0}}
3786
@end itemize
3787
 
3788
 
3789
@itemize @bullet
3790
@item uint8x8_t vsra_n_u8 (uint8x8_t, uint8x8_t, const int)
3791
@*@emph{Form of expected instruction(s):} @code{vsra.u8 @var{d0}, @var{d0}, #@var{0}}
3792
@end itemize
3793
 
3794
 
3795
@itemize @bullet
3796
@item int32x2_t vsra_n_s32 (int32x2_t, int32x2_t, const int)
3797
@*@emph{Form of expected instruction(s):} @code{vsra.s32 @var{d0}, @var{d0}, #@var{0}}
3798
@end itemize
3799
 
3800
 
3801
@itemize @bullet
3802
@item int16x4_t vsra_n_s16 (int16x4_t, int16x4_t, const int)
3803
@*@emph{Form of expected instruction(s):} @code{vsra.s16 @var{d0}, @var{d0}, #@var{0}}
3804
@end itemize
3805
 
3806
 
3807
@itemize @bullet
3808
@item int8x8_t vsra_n_s8 (int8x8_t, int8x8_t, const int)
3809
@*@emph{Form of expected instruction(s):} @code{vsra.s8 @var{d0}, @var{d0}, #@var{0}}
3810
@end itemize
3811
 
3812
 
3813
@itemize @bullet
3814
@item uint64x1_t vsra_n_u64 (uint64x1_t, uint64x1_t, const int)
3815
@*@emph{Form of expected instruction(s):} @code{vsra.u64 @var{d0}, @var{d0}, #@var{0}}
3816
@end itemize
3817
 
3818
 
3819
@itemize @bullet
3820
@item int64x1_t vsra_n_s64 (int64x1_t, int64x1_t, const int)
3821
@*@emph{Form of expected instruction(s):} @code{vsra.s64 @var{d0}, @var{d0}, #@var{0}}
3822
@end itemize
3823
 
3824
 
3825
@itemize @bullet
3826
@item uint32x4_t vsraq_n_u32 (uint32x4_t, uint32x4_t, const int)
3827
@*@emph{Form of expected instruction(s):} @code{vsra.u32 @var{q0}, @var{q0}, #@var{0}}
3828
@end itemize
3829
 
3830
 
3831
@itemize @bullet
3832
@item uint16x8_t vsraq_n_u16 (uint16x8_t, uint16x8_t, const int)
3833
@*@emph{Form of expected instruction(s):} @code{vsra.u16 @var{q0}, @var{q0}, #@var{0}}
3834
@end itemize
3835
 
3836
 
3837
@itemize @bullet
3838
@item uint8x16_t vsraq_n_u8 (uint8x16_t, uint8x16_t, const int)
3839
@*@emph{Form of expected instruction(s):} @code{vsra.u8 @var{q0}, @var{q0}, #@var{0}}
3840
@end itemize
3841
 
3842
 
3843
@itemize @bullet
3844
@item int32x4_t vsraq_n_s32 (int32x4_t, int32x4_t, const int)
3845
@*@emph{Form of expected instruction(s):} @code{vsra.s32 @var{q0}, @var{q0}, #@var{0}}
3846
@end itemize
3847
 
3848
 
3849
@itemize @bullet
3850
@item int16x8_t vsraq_n_s16 (int16x8_t, int16x8_t, const int)
3851
@*@emph{Form of expected instruction(s):} @code{vsra.s16 @var{q0}, @var{q0}, #@var{0}}
3852
@end itemize
3853
 
3854
 
3855
@itemize @bullet
3856
@item int8x16_t vsraq_n_s8 (int8x16_t, int8x16_t, const int)
3857
@*@emph{Form of expected instruction(s):} @code{vsra.s8 @var{q0}, @var{q0}, #@var{0}}
3858
@end itemize
3859
 
3860
 
3861
@itemize @bullet
3862
@item uint64x2_t vsraq_n_u64 (uint64x2_t, uint64x2_t, const int)
3863
@*@emph{Form of expected instruction(s):} @code{vsra.u64 @var{q0}, @var{q0}, #@var{0}}
3864
@end itemize
3865
 
3866
 
3867
@itemize @bullet
3868
@item int64x2_t vsraq_n_s64 (int64x2_t, int64x2_t, const int)
3869
@*@emph{Form of expected instruction(s):} @code{vsra.s64 @var{q0}, @var{q0}, #@var{0}}
3870
@end itemize
3871
 
3872
 
3873
@itemize @bullet
3874
@item uint32x2_t vrsra_n_u32 (uint32x2_t, uint32x2_t, const int)
3875
@*@emph{Form of expected instruction(s):} @code{vrsra.u32 @var{d0}, @var{d0}, #@var{0}}
3876
@end itemize
3877
 
3878
 
3879
@itemize @bullet
3880
@item uint16x4_t vrsra_n_u16 (uint16x4_t, uint16x4_t, const int)
3881
@*@emph{Form of expected instruction(s):} @code{vrsra.u16 @var{d0}, @var{d0}, #@var{0}}
3882
@end itemize
3883
 
3884
 
3885
@itemize @bullet
3886
@item uint8x8_t vrsra_n_u8 (uint8x8_t, uint8x8_t, const int)
3887
@*@emph{Form of expected instruction(s):} @code{vrsra.u8 @var{d0}, @var{d0}, #@var{0}}
3888
@end itemize
3889
 
3890
 
3891
@itemize @bullet
3892
@item int32x2_t vrsra_n_s32 (int32x2_t, int32x2_t, const int)
3893
@*@emph{Form of expected instruction(s):} @code{vrsra.s32 @var{d0}, @var{d0}, #@var{0}}
3894
@end itemize
3895
 
3896
 
3897
@itemize @bullet
3898
@item int16x4_t vrsra_n_s16 (int16x4_t, int16x4_t, const int)
3899
@*@emph{Form of expected instruction(s):} @code{vrsra.s16 @var{d0}, @var{d0}, #@var{0}}
3900
@end itemize
3901
 
3902
 
3903
@itemize @bullet
3904
@item int8x8_t vrsra_n_s8 (int8x8_t, int8x8_t, const int)
3905
@*@emph{Form of expected instruction(s):} @code{vrsra.s8 @var{d0}, @var{d0}, #@var{0}}
3906
@end itemize
3907
 
3908
 
3909
@itemize @bullet
3910
@item uint64x1_t vrsra_n_u64 (uint64x1_t, uint64x1_t, const int)
3911
@*@emph{Form of expected instruction(s):} @code{vrsra.u64 @var{d0}, @var{d0}, #@var{0}}
3912
@end itemize
3913
 
3914
 
3915
@itemize @bullet
3916
@item int64x1_t vrsra_n_s64 (int64x1_t, int64x1_t, const int)
3917
@*@emph{Form of expected instruction(s):} @code{vrsra.s64 @var{d0}, @var{d0}, #@var{0}}
3918
@end itemize
3919
 
3920
 
3921
@itemize @bullet
3922
@item uint32x4_t vrsraq_n_u32 (uint32x4_t, uint32x4_t, const int)
3923
@*@emph{Form of expected instruction(s):} @code{vrsra.u32 @var{q0}, @var{q0}, #@var{0}}
3924
@end itemize
3925
 
3926
 
3927
@itemize @bullet
3928
@item uint16x8_t vrsraq_n_u16 (uint16x8_t, uint16x8_t, const int)
3929
@*@emph{Form of expected instruction(s):} @code{vrsra.u16 @var{q0}, @var{q0}, #@var{0}}
3930
@end itemize
3931
 
3932
 
3933
@itemize @bullet
3934
@item uint8x16_t vrsraq_n_u8 (uint8x16_t, uint8x16_t, const int)
3935
@*@emph{Form of expected instruction(s):} @code{vrsra.u8 @var{q0}, @var{q0}, #@var{0}}
3936
@end itemize
3937
 
3938
 
3939
@itemize @bullet
3940
@item int32x4_t vrsraq_n_s32 (int32x4_t, int32x4_t, const int)
3941
@*@emph{Form of expected instruction(s):} @code{vrsra.s32 @var{q0}, @var{q0}, #@var{0}}
3942
@end itemize
3943
 
3944
 
3945
@itemize @bullet
3946
@item int16x8_t vrsraq_n_s16 (int16x8_t, int16x8_t, const int)
3947
@*@emph{Form of expected instruction(s):} @code{vrsra.s16 @var{q0}, @var{q0}, #@var{0}}
3948
@end itemize
3949
 
3950
 
3951
@itemize @bullet
3952
@item int8x16_t vrsraq_n_s8 (int8x16_t, int8x16_t, const int)
3953
@*@emph{Form of expected instruction(s):} @code{vrsra.s8 @var{q0}, @var{q0}, #@var{0}}
3954
@end itemize
3955
 
3956
 
3957
@itemize @bullet
3958
@item uint64x2_t vrsraq_n_u64 (uint64x2_t, uint64x2_t, const int)
3959
@*@emph{Form of expected instruction(s):} @code{vrsra.u64 @var{q0}, @var{q0}, #@var{0}}
3960
@end itemize
3961
 
3962
 
3963
@itemize @bullet
3964
@item int64x2_t vrsraq_n_s64 (int64x2_t, int64x2_t, const int)
3965
@*@emph{Form of expected instruction(s):} @code{vrsra.s64 @var{q0}, @var{q0}, #@var{0}}
3966
@end itemize
3967
 
3968
 
3969
 
3970
 
3971
@subsubsection Vector shift right and insert
3972
 
3973
@itemize @bullet
3974
@item uint32x2_t vsri_n_u32 (uint32x2_t, uint32x2_t, const int)
3975
@*@emph{Form of expected instruction(s):} @code{vsri.32 @var{d0}, @var{d0}, #@var{0}}
3976
@end itemize
3977
 
3978
 
3979
@itemize @bullet
3980
@item uint16x4_t vsri_n_u16 (uint16x4_t, uint16x4_t, const int)
3981
@*@emph{Form of expected instruction(s):} @code{vsri.16 @var{d0}, @var{d0}, #@var{0}}
3982
@end itemize
3983
 
3984
 
3985
@itemize @bullet
3986
@item uint8x8_t vsri_n_u8 (uint8x8_t, uint8x8_t, const int)
3987
@*@emph{Form of expected instruction(s):} @code{vsri.8 @var{d0}, @var{d0}, #@var{0}}
3988
@end itemize
3989
 
3990
 
3991
@itemize @bullet
3992
@item int32x2_t vsri_n_s32 (int32x2_t, int32x2_t, const int)
3993
@*@emph{Form of expected instruction(s):} @code{vsri.32 @var{d0}, @var{d0}, #@var{0}}
3994
@end itemize
3995
 
3996
 
3997
@itemize @bullet
3998
@item int16x4_t vsri_n_s16 (int16x4_t, int16x4_t, const int)
3999
@*@emph{Form of expected instruction(s):} @code{vsri.16 @var{d0}, @var{d0}, #@var{0}}
4000
@end itemize
4001
 
4002
 
4003
@itemize @bullet
4004
@item int8x8_t vsri_n_s8 (int8x8_t, int8x8_t, const int)
4005
@*@emph{Form of expected instruction(s):} @code{vsri.8 @var{d0}, @var{d0}, #@var{0}}
4006
@end itemize
4007
 
4008
 
4009
@itemize @bullet
4010
@item uint64x1_t vsri_n_u64 (uint64x1_t, uint64x1_t, const int)
4011
@*@emph{Form of expected instruction(s):} @code{vsri.64 @var{d0}, @var{d0}, #@var{0}}
4012
@end itemize
4013
 
4014
 
4015
@itemize @bullet
4016
@item int64x1_t vsri_n_s64 (int64x1_t, int64x1_t, const int)
4017
@*@emph{Form of expected instruction(s):} @code{vsri.64 @var{d0}, @var{d0}, #@var{0}}
4018
@end itemize
4019
 
4020
 
4021
@itemize @bullet
4022
@item poly16x4_t vsri_n_p16 (poly16x4_t, poly16x4_t, const int)
4023
@*@emph{Form of expected instruction(s):} @code{vsri.16 @var{d0}, @var{d0}, #@var{0}}
4024
@end itemize
4025
 
4026
 
4027
@itemize @bullet
4028
@item poly8x8_t vsri_n_p8 (poly8x8_t, poly8x8_t, const int)
4029
@*@emph{Form of expected instruction(s):} @code{vsri.8 @var{d0}, @var{d0}, #@var{0}}
4030
@end itemize
4031
 
4032
 
4033
@itemize @bullet
4034
@item uint32x4_t vsriq_n_u32 (uint32x4_t, uint32x4_t, const int)
4035
@*@emph{Form of expected instruction(s):} @code{vsri.32 @var{q0}, @var{q0}, #@var{0}}
4036
@end itemize
4037
 
4038
 
4039
@itemize @bullet
4040
@item uint16x8_t vsriq_n_u16 (uint16x8_t, uint16x8_t, const int)
4041
@*@emph{Form of expected instruction(s):} @code{vsri.16 @var{q0}, @var{q0}, #@var{0}}
4042
@end itemize
4043
 
4044
 
4045
@itemize @bullet
4046
@item uint8x16_t vsriq_n_u8 (uint8x16_t, uint8x16_t, const int)
4047
@*@emph{Form of expected instruction(s):} @code{vsri.8 @var{q0}, @var{q0}, #@var{0}}
4048
@end itemize
4049
 
4050
 
4051
@itemize @bullet
4052
@item int32x4_t vsriq_n_s32 (int32x4_t, int32x4_t, const int)
4053
@*@emph{Form of expected instruction(s):} @code{vsri.32 @var{q0}, @var{q0}, #@var{0}}
4054
@end itemize
4055
 
4056
 
4057
@itemize @bullet
4058
@item int16x8_t vsriq_n_s16 (int16x8_t, int16x8_t, const int)
4059
@*@emph{Form of expected instruction(s):} @code{vsri.16 @var{q0}, @var{q0}, #@var{0}}
4060
@end itemize
4061
 
4062
 
4063
@itemize @bullet
4064
@item int8x16_t vsriq_n_s8 (int8x16_t, int8x16_t, const int)
4065
@*@emph{Form of expected instruction(s):} @code{vsri.8 @var{q0}, @var{q0}, #@var{0}}
4066
@end itemize
4067
 
4068
 
4069
@itemize @bullet
4070
@item uint64x2_t vsriq_n_u64 (uint64x2_t, uint64x2_t, const int)
4071
@*@emph{Form of expected instruction(s):} @code{vsri.64 @var{q0}, @var{q0}, #@var{0}}
4072
@end itemize
4073
 
4074
 
4075
@itemize @bullet
4076
@item int64x2_t vsriq_n_s64 (int64x2_t, int64x2_t, const int)
4077
@*@emph{Form of expected instruction(s):} @code{vsri.64 @var{q0}, @var{q0}, #@var{0}}
4078
@end itemize
4079
 
4080
 
4081
@itemize @bullet
4082
@item poly16x8_t vsriq_n_p16 (poly16x8_t, poly16x8_t, const int)
4083
@*@emph{Form of expected instruction(s):} @code{vsri.16 @var{q0}, @var{q0}, #@var{0}}
4084
@end itemize
4085
 
4086
 
4087
@itemize @bullet
4088
@item poly8x16_t vsriq_n_p8 (poly8x16_t, poly8x16_t, const int)
4089
@*@emph{Form of expected instruction(s):} @code{vsri.8 @var{q0}, @var{q0}, #@var{0}}
4090
@end itemize
4091
 
4092
 
4093
 
4094
 
4095
@subsubsection Vector shift left and insert
4096
 
4097
@itemize @bullet
4098
@item uint32x2_t vsli_n_u32 (uint32x2_t, uint32x2_t, const int)
4099
@*@emph{Form of expected instruction(s):} @code{vsli.32 @var{d0}, @var{d0}, #@var{0}}
4100
@end itemize
4101
 
4102
 
4103
@itemize @bullet
4104
@item uint16x4_t vsli_n_u16 (uint16x4_t, uint16x4_t, const int)
4105
@*@emph{Form of expected instruction(s):} @code{vsli.16 @var{d0}, @var{d0}, #@var{0}}
4106
@end itemize
4107
 
4108
 
4109
@itemize @bullet
4110
@item uint8x8_t vsli_n_u8 (uint8x8_t, uint8x8_t, const int)
4111
@*@emph{Form of expected instruction(s):} @code{vsli.8 @var{d0}, @var{d0}, #@var{0}}
4112
@end itemize
4113
 
4114
 
4115
@itemize @bullet
4116
@item int32x2_t vsli_n_s32 (int32x2_t, int32x2_t, const int)
4117
@*@emph{Form of expected instruction(s):} @code{vsli.32 @var{d0}, @var{d0}, #@var{0}}
4118
@end itemize
4119
 
4120
 
4121
@itemize @bullet
4122
@item int16x4_t vsli_n_s16 (int16x4_t, int16x4_t, const int)
4123
@*@emph{Form of expected instruction(s):} @code{vsli.16 @var{d0}, @var{d0}, #@var{0}}
4124
@end itemize
4125
 
4126
 
4127
@itemize @bullet
4128
@item int8x8_t vsli_n_s8 (int8x8_t, int8x8_t, const int)
4129
@*@emph{Form of expected instruction(s):} @code{vsli.8 @var{d0}, @var{d0}, #@var{0}}
4130
@end itemize
4131
 
4132
 
4133
@itemize @bullet
4134
@item uint64x1_t vsli_n_u64 (uint64x1_t, uint64x1_t, const int)
4135
@*@emph{Form of expected instruction(s):} @code{vsli.64 @var{d0}, @var{d0}, #@var{0}}
4136
@end itemize
4137
 
4138
 
4139
@itemize @bullet
4140
@item int64x1_t vsli_n_s64 (int64x1_t, int64x1_t, const int)
4141
@*@emph{Form of expected instruction(s):} @code{vsli.64 @var{d0}, @var{d0}, #@var{0}}
4142
@end itemize
4143
 
4144
 
4145
@itemize @bullet
4146
@item poly16x4_t vsli_n_p16 (poly16x4_t, poly16x4_t, const int)
4147
@*@emph{Form of expected instruction(s):} @code{vsli.16 @var{d0}, @var{d0}, #@var{0}}
4148
@end itemize
4149
 
4150
 
4151
@itemize @bullet
4152
@item poly8x8_t vsli_n_p8 (poly8x8_t, poly8x8_t, const int)
4153
@*@emph{Form of expected instruction(s):} @code{vsli.8 @var{d0}, @var{d0}, #@var{0}}
4154
@end itemize
4155
 
4156
 
4157
@itemize @bullet
4158
@item uint32x4_t vsliq_n_u32 (uint32x4_t, uint32x4_t, const int)
4159
@*@emph{Form of expected instruction(s):} @code{vsli.32 @var{q0}, @var{q0}, #@var{0}}
4160
@end itemize
4161
 
4162
 
4163
@itemize @bullet
4164
@item uint16x8_t vsliq_n_u16 (uint16x8_t, uint16x8_t, const int)
4165
@*@emph{Form of expected instruction(s):} @code{vsli.16 @var{q0}, @var{q0}, #@var{0}}
4166
@end itemize
4167
 
4168
 
4169
@itemize @bullet
4170
@item uint8x16_t vsliq_n_u8 (uint8x16_t, uint8x16_t, const int)
4171
@*@emph{Form of expected instruction(s):} @code{vsli.8 @var{q0}, @var{q0}, #@var{0}}
4172
@end itemize
4173
 
4174
 
4175
@itemize @bullet
4176
@item int32x4_t vsliq_n_s32 (int32x4_t, int32x4_t, const int)
4177
@*@emph{Form of expected instruction(s):} @code{vsli.32 @var{q0}, @var{q0}, #@var{0}}
4178
@end itemize
4179
 
4180
 
4181
@itemize @bullet
4182
@item int16x8_t vsliq_n_s16 (int16x8_t, int16x8_t, const int)
4183
@*@emph{Form of expected instruction(s):} @code{vsli.16 @var{q0}, @var{q0}, #@var{0}}
4184
@end itemize
4185
 
4186
 
4187
@itemize @bullet
4188
@item int8x16_t vsliq_n_s8 (int8x16_t, int8x16_t, const int)
4189
@*@emph{Form of expected instruction(s):} @code{vsli.8 @var{q0}, @var{q0}, #@var{0}}
4190
@end itemize
4191
 
4192
 
4193
@itemize @bullet
4194
@item uint64x2_t vsliq_n_u64 (uint64x2_t, uint64x2_t, const int)
4195
@*@emph{Form of expected instruction(s):} @code{vsli.64 @var{q0}, @var{q0}, #@var{0}}
4196
@end itemize
4197
 
4198
 
4199
@itemize @bullet
4200
@item int64x2_t vsliq_n_s64 (int64x2_t, int64x2_t, const int)
4201
@*@emph{Form of expected instruction(s):} @code{vsli.64 @var{q0}, @var{q0}, #@var{0}}
4202
@end itemize
4203
 
4204
 
4205
@itemize @bullet
4206
@item poly16x8_t vsliq_n_p16 (poly16x8_t, poly16x8_t, const int)
4207
@*@emph{Form of expected instruction(s):} @code{vsli.16 @var{q0}, @var{q0}, #@var{0}}
4208
@end itemize
4209
 
4210
 
4211
@itemize @bullet
4212
@item poly8x16_t vsliq_n_p8 (poly8x16_t, poly8x16_t, const int)
4213
@*@emph{Form of expected instruction(s):} @code{vsli.8 @var{q0}, @var{q0}, #@var{0}}
4214
@end itemize
4215
 
4216
 
4217
 
4218
 
4219
@subsubsection Absolute value
4220
 
4221
@itemize @bullet
4222
@item float32x2_t vabs_f32 (float32x2_t)
4223
@*@emph{Form of expected instruction(s):} @code{vabs.f32 @var{d0}, @var{d0}}
4224
@end itemize
4225
 
4226
 
4227
@itemize @bullet
4228
@item int32x2_t vabs_s32 (int32x2_t)
4229
@*@emph{Form of expected instruction(s):} @code{vabs.s32 @var{d0}, @var{d0}}
4230
@end itemize
4231
 
4232
 
4233
@itemize @bullet
4234
@item int16x4_t vabs_s16 (int16x4_t)
4235
@*@emph{Form of expected instruction(s):} @code{vabs.s16 @var{d0}, @var{d0}}
4236
@end itemize
4237
 
4238
 
4239
@itemize @bullet
4240
@item int8x8_t vabs_s8 (int8x8_t)
4241
@*@emph{Form of expected instruction(s):} @code{vabs.s8 @var{d0}, @var{d0}}
4242
@end itemize
4243
 
4244
 
4245
@itemize @bullet
4246
@item float32x4_t vabsq_f32 (float32x4_t)
4247
@*@emph{Form of expected instruction(s):} @code{vabs.f32 @var{q0}, @var{q0}}
4248
@end itemize
4249
 
4250
 
4251
@itemize @bullet
4252
@item int32x4_t vabsq_s32 (int32x4_t)
4253
@*@emph{Form of expected instruction(s):} @code{vabs.s32 @var{q0}, @var{q0}}
4254
@end itemize
4255
 
4256
 
4257
@itemize @bullet
4258
@item int16x8_t vabsq_s16 (int16x8_t)
4259
@*@emph{Form of expected instruction(s):} @code{vabs.s16 @var{q0}, @var{q0}}
4260
@end itemize
4261
 
4262
 
4263
@itemize @bullet
4264
@item int8x16_t vabsq_s8 (int8x16_t)
4265
@*@emph{Form of expected instruction(s):} @code{vabs.s8 @var{q0}, @var{q0}}
4266
@end itemize
4267
 
4268
 
4269
@itemize @bullet
4270
@item int32x2_t vqabs_s32 (int32x2_t)
4271
@*@emph{Form of expected instruction(s):} @code{vqabs.s32 @var{d0}, @var{d0}}
4272
@end itemize
4273
 
4274
 
4275
@itemize @bullet
4276
@item int16x4_t vqabs_s16 (int16x4_t)
4277
@*@emph{Form of expected instruction(s):} @code{vqabs.s16 @var{d0}, @var{d0}}
4278
@end itemize
4279
 
4280
 
4281
@itemize @bullet
4282
@item int8x8_t vqabs_s8 (int8x8_t)
4283
@*@emph{Form of expected instruction(s):} @code{vqabs.s8 @var{d0}, @var{d0}}
4284
@end itemize
4285
 
4286
 
4287
@itemize @bullet
4288
@item int32x4_t vqabsq_s32 (int32x4_t)
4289
@*@emph{Form of expected instruction(s):} @code{vqabs.s32 @var{q0}, @var{q0}}
4290
@end itemize
4291
 
4292
 
4293
@itemize @bullet
4294
@item int16x8_t vqabsq_s16 (int16x8_t)
4295
@*@emph{Form of expected instruction(s):} @code{vqabs.s16 @var{q0}, @var{q0}}
4296
@end itemize
4297
 
4298
 
4299
@itemize @bullet
4300
@item int8x16_t vqabsq_s8 (int8x16_t)
4301
@*@emph{Form of expected instruction(s):} @code{vqabs.s8 @var{q0}, @var{q0}}
4302
@end itemize
4303
 
4304
 
4305
 
4306
 
4307
@subsubsection Negation
4308
 
4309
@itemize @bullet
4310
@item float32x2_t vneg_f32 (float32x2_t)
4311
@*@emph{Form of expected instruction(s):} @code{vneg.f32 @var{d0}, @var{d0}}
4312
@end itemize
4313
 
4314
 
4315
@itemize @bullet
4316
@item int32x2_t vneg_s32 (int32x2_t)
4317
@*@emph{Form of expected instruction(s):} @code{vneg.s32 @var{d0}, @var{d0}}
4318
@end itemize
4319
 
4320
 
4321
@itemize @bullet
4322
@item int16x4_t vneg_s16 (int16x4_t)
4323
@*@emph{Form of expected instruction(s):} @code{vneg.s16 @var{d0}, @var{d0}}
4324
@end itemize
4325
 
4326
 
4327
@itemize @bullet
4328
@item int8x8_t vneg_s8 (int8x8_t)
4329
@*@emph{Form of expected instruction(s):} @code{vneg.s8 @var{d0}, @var{d0}}
4330
@end itemize
4331
 
4332
 
4333
@itemize @bullet
4334
@item float32x4_t vnegq_f32 (float32x4_t)
4335
@*@emph{Form of expected instruction(s):} @code{vneg.f32 @var{q0}, @var{q0}}
4336
@end itemize
4337
 
4338
 
4339
@itemize @bullet
4340
@item int32x4_t vnegq_s32 (int32x4_t)
4341
@*@emph{Form of expected instruction(s):} @code{vneg.s32 @var{q0}, @var{q0}}
4342
@end itemize
4343
 
4344
 
4345
@itemize @bullet
4346
@item int16x8_t vnegq_s16 (int16x8_t)
4347
@*@emph{Form of expected instruction(s):} @code{vneg.s16 @var{q0}, @var{q0}}
4348
@end itemize
4349
 
4350
 
4351
@itemize @bullet
4352
@item int8x16_t vnegq_s8 (int8x16_t)
4353
@*@emph{Form of expected instruction(s):} @code{vneg.s8 @var{q0}, @var{q0}}
4354
@end itemize
4355
 
4356
 
4357
@itemize @bullet
4358
@item int32x2_t vqneg_s32 (int32x2_t)
4359
@*@emph{Form of expected instruction(s):} @code{vqneg.s32 @var{d0}, @var{d0}}
4360
@end itemize
4361
 
4362
 
4363
@itemize @bullet
4364
@item int16x4_t vqneg_s16 (int16x4_t)
4365
@*@emph{Form of expected instruction(s):} @code{vqneg.s16 @var{d0}, @var{d0}}
4366
@end itemize
4367
 
4368
 
4369
@itemize @bullet
4370
@item int8x8_t vqneg_s8 (int8x8_t)
4371
@*@emph{Form of expected instruction(s):} @code{vqneg.s8 @var{d0}, @var{d0}}
4372
@end itemize
4373
 
4374
 
4375
@itemize @bullet
4376
@item int32x4_t vqnegq_s32 (int32x4_t)
4377
@*@emph{Form of expected instruction(s):} @code{vqneg.s32 @var{q0}, @var{q0}}
4378
@end itemize
4379
 
4380
 
4381
@itemize @bullet
4382
@item int16x8_t vqnegq_s16 (int16x8_t)
4383
@*@emph{Form of expected instruction(s):} @code{vqneg.s16 @var{q0}, @var{q0}}
4384
@end itemize
4385
 
4386
 
4387
@itemize @bullet
4388
@item int8x16_t vqnegq_s8 (int8x16_t)
4389
@*@emph{Form of expected instruction(s):} @code{vqneg.s8 @var{q0}, @var{q0}}
4390
@end itemize
4391
 
4392
 
4393
 
4394
 
4395
@subsubsection Bitwise not
4396
 
4397
@itemize @bullet
4398
@item uint32x2_t vmvn_u32 (uint32x2_t)
4399
@*@emph{Form of expected instruction(s):} @code{vmvn @var{d0}, @var{d0}}
4400
@end itemize
4401
 
4402
 
4403
@itemize @bullet
4404
@item uint16x4_t vmvn_u16 (uint16x4_t)
4405
@*@emph{Form of expected instruction(s):} @code{vmvn @var{d0}, @var{d0}}
4406
@end itemize
4407
 
4408
 
4409
@itemize @bullet
4410
@item uint8x8_t vmvn_u8 (uint8x8_t)
4411
@*@emph{Form of expected instruction(s):} @code{vmvn @var{d0}, @var{d0}}
4412
@end itemize
4413
 
4414
 
4415
@itemize @bullet
4416
@item int32x2_t vmvn_s32 (int32x2_t)
4417
@*@emph{Form of expected instruction(s):} @code{vmvn @var{d0}, @var{d0}}
4418
@end itemize
4419
 
4420
 
4421
@itemize @bullet
4422
@item int16x4_t vmvn_s16 (int16x4_t)
4423
@*@emph{Form of expected instruction(s):} @code{vmvn @var{d0}, @var{d0}}
4424
@end itemize
4425
 
4426
 
4427
@itemize @bullet
4428
@item int8x8_t vmvn_s8 (int8x8_t)
4429
@*@emph{Form of expected instruction(s):} @code{vmvn @var{d0}, @var{d0}}
4430
@end itemize
4431
 
4432
 
4433
@itemize @bullet
4434
@item poly8x8_t vmvn_p8 (poly8x8_t)
4435
@*@emph{Form of expected instruction(s):} @code{vmvn @var{d0}, @var{d0}}
4436
@end itemize
4437
 
4438
 
4439
@itemize @bullet
4440
@item uint32x4_t vmvnq_u32 (uint32x4_t)
4441
@*@emph{Form of expected instruction(s):} @code{vmvn @var{q0}, @var{q0}}
4442
@end itemize
4443
 
4444
 
4445
@itemize @bullet
4446
@item uint16x8_t vmvnq_u16 (uint16x8_t)
4447
@*@emph{Form of expected instruction(s):} @code{vmvn @var{q0}, @var{q0}}
4448
@end itemize
4449
 
4450
 
4451
@itemize @bullet
4452
@item uint8x16_t vmvnq_u8 (uint8x16_t)
4453
@*@emph{Form of expected instruction(s):} @code{vmvn @var{q0}, @var{q0}}
4454
@end itemize
4455
 
4456
 
4457
@itemize @bullet
4458
@item int32x4_t vmvnq_s32 (int32x4_t)
4459
@*@emph{Form of expected instruction(s):} @code{vmvn @var{q0}, @var{q0}}
4460
@end itemize
4461
 
4462
 
4463
@itemize @bullet
4464
@item int16x8_t vmvnq_s16 (int16x8_t)
4465
@*@emph{Form of expected instruction(s):} @code{vmvn @var{q0}, @var{q0}}
4466
@end itemize
4467
 
4468
 
4469
@itemize @bullet
4470
@item int8x16_t vmvnq_s8 (int8x16_t)
4471
@*@emph{Form of expected instruction(s):} @code{vmvn @var{q0}, @var{q0}}
4472
@end itemize
4473
 
4474
 
4475
@itemize @bullet
4476
@item poly8x16_t vmvnq_p8 (poly8x16_t)
4477
@*@emph{Form of expected instruction(s):} @code{vmvn @var{q0}, @var{q0}}
4478
@end itemize
4479
 
4480
 
4481
 
4482
 
4483
@subsubsection Count leading sign bits
4484
 
4485
@itemize @bullet
4486
@item int32x2_t vcls_s32 (int32x2_t)
4487
@*@emph{Form of expected instruction(s):} @code{vcls.s32 @var{d0}, @var{d0}}
4488
@end itemize
4489
 
4490
 
4491
@itemize @bullet
4492
@item int16x4_t vcls_s16 (int16x4_t)
4493
@*@emph{Form of expected instruction(s):} @code{vcls.s16 @var{d0}, @var{d0}}
4494
@end itemize
4495
 
4496
 
4497
@itemize @bullet
4498
@item int8x8_t vcls_s8 (int8x8_t)
4499
@*@emph{Form of expected instruction(s):} @code{vcls.s8 @var{d0}, @var{d0}}
4500
@end itemize
4501
 
4502
 
4503
@itemize @bullet
4504
@item int32x4_t vclsq_s32 (int32x4_t)
4505
@*@emph{Form of expected instruction(s):} @code{vcls.s32 @var{q0}, @var{q0}}
4506
@end itemize
4507
 
4508
 
4509
@itemize @bullet
4510
@item int16x8_t vclsq_s16 (int16x8_t)
4511
@*@emph{Form of expected instruction(s):} @code{vcls.s16 @var{q0}, @var{q0}}
4512
@end itemize
4513
 
4514
 
4515
@itemize @bullet
4516
@item int8x16_t vclsq_s8 (int8x16_t)
4517
@*@emph{Form of expected instruction(s):} @code{vcls.s8 @var{q0}, @var{q0}}
4518
@end itemize
4519
 
4520
 
4521
 
4522
 
4523
@subsubsection Count leading zeros
4524
 
4525
@itemize @bullet
4526
@item uint32x2_t vclz_u32 (uint32x2_t)
4527
@*@emph{Form of expected instruction(s):} @code{vclz.i32 @var{d0}, @var{d0}}
4528
@end itemize
4529
 
4530
 
4531
@itemize @bullet
4532
@item uint16x4_t vclz_u16 (uint16x4_t)
4533
@*@emph{Form of expected instruction(s):} @code{vclz.i16 @var{d0}, @var{d0}}
4534
@end itemize
4535
 
4536
 
4537
@itemize @bullet
4538
@item uint8x8_t vclz_u8 (uint8x8_t)
4539
@*@emph{Form of expected instruction(s):} @code{vclz.i8 @var{d0}, @var{d0}}
4540
@end itemize
4541
 
4542
 
4543
@itemize @bullet
4544
@item int32x2_t vclz_s32 (int32x2_t)
4545
@*@emph{Form of expected instruction(s):} @code{vclz.i32 @var{d0}, @var{d0}}
4546
@end itemize
4547
 
4548
 
4549
@itemize @bullet
4550
@item int16x4_t vclz_s16 (int16x4_t)
4551
@*@emph{Form of expected instruction(s):} @code{vclz.i16 @var{d0}, @var{d0}}
4552
@end itemize
4553
 
4554
 
4555
@itemize @bullet
4556
@item int8x8_t vclz_s8 (int8x8_t)
4557
@*@emph{Form of expected instruction(s):} @code{vclz.i8 @var{d0}, @var{d0}}
4558
@end itemize
4559
 
4560
 
4561
@itemize @bullet
4562
@item uint32x4_t vclzq_u32 (uint32x4_t)
4563
@*@emph{Form of expected instruction(s):} @code{vclz.i32 @var{q0}, @var{q0}}
4564
@end itemize
4565
 
4566
 
4567
@itemize @bullet
4568
@item uint16x8_t vclzq_u16 (uint16x8_t)
4569
@*@emph{Form of expected instruction(s):} @code{vclz.i16 @var{q0}, @var{q0}}
4570
@end itemize
4571
 
4572
 
4573
@itemize @bullet
4574
@item uint8x16_t vclzq_u8 (uint8x16_t)
4575
@*@emph{Form of expected instruction(s):} @code{vclz.i8 @var{q0}, @var{q0}}
4576
@end itemize
4577
 
4578
 
4579
@itemize @bullet
4580
@item int32x4_t vclzq_s32 (int32x4_t)
4581
@*@emph{Form of expected instruction(s):} @code{vclz.i32 @var{q0}, @var{q0}}
4582
@end itemize
4583
 
4584
 
4585
@itemize @bullet
4586
@item int16x8_t vclzq_s16 (int16x8_t)
4587
@*@emph{Form of expected instruction(s):} @code{vclz.i16 @var{q0}, @var{q0}}
4588
@end itemize
4589
 
4590
 
4591
@itemize @bullet
4592
@item int8x16_t vclzq_s8 (int8x16_t)
4593
@*@emph{Form of expected instruction(s):} @code{vclz.i8 @var{q0}, @var{q0}}
4594
@end itemize
4595
 
4596
 
4597
 
4598
 
4599
@subsubsection Count number of set bits
4600
 
4601
@itemize @bullet
4602
@item uint8x8_t vcnt_u8 (uint8x8_t)
4603
@*@emph{Form of expected instruction(s):} @code{vcnt.8 @var{d0}, @var{d0}}
4604
@end itemize
4605
 
4606
 
4607
@itemize @bullet
4608
@item int8x8_t vcnt_s8 (int8x8_t)
4609
@*@emph{Form of expected instruction(s):} @code{vcnt.8 @var{d0}, @var{d0}}
4610
@end itemize
4611
 
4612
 
4613
@itemize @bullet
4614
@item poly8x8_t vcnt_p8 (poly8x8_t)
4615
@*@emph{Form of expected instruction(s):} @code{vcnt.8 @var{d0}, @var{d0}}
4616
@end itemize
4617
 
4618
 
4619
@itemize @bullet
4620
@item uint8x16_t vcntq_u8 (uint8x16_t)
4621
@*@emph{Form of expected instruction(s):} @code{vcnt.8 @var{q0}, @var{q0}}
4622
@end itemize
4623
 
4624
 
4625
@itemize @bullet
4626
@item int8x16_t vcntq_s8 (int8x16_t)
4627
@*@emph{Form of expected instruction(s):} @code{vcnt.8 @var{q0}, @var{q0}}
4628
@end itemize
4629
 
4630
 
4631
@itemize @bullet
4632
@item poly8x16_t vcntq_p8 (poly8x16_t)
4633
@*@emph{Form of expected instruction(s):} @code{vcnt.8 @var{q0}, @var{q0}}
4634
@end itemize
4635
 
4636
 
4637
 
4638
 
4639
@subsubsection Reciprocal estimate
4640
 
4641
@itemize @bullet
4642
@item float32x2_t vrecpe_f32 (float32x2_t)
4643
@*@emph{Form of expected instruction(s):} @code{vrecpe.f32 @var{d0}, @var{d0}}
4644
@end itemize
4645
 
4646
 
4647
@itemize @bullet
4648
@item uint32x2_t vrecpe_u32 (uint32x2_t)
4649
@*@emph{Form of expected instruction(s):} @code{vrecpe.u32 @var{d0}, @var{d0}}
4650
@end itemize
4651
 
4652
 
4653
@itemize @bullet
4654
@item float32x4_t vrecpeq_f32 (float32x4_t)
4655
@*@emph{Form of expected instruction(s):} @code{vrecpe.f32 @var{q0}, @var{q0}}
4656
@end itemize
4657
 
4658
 
4659
@itemize @bullet
4660
@item uint32x4_t vrecpeq_u32 (uint32x4_t)
4661
@*@emph{Form of expected instruction(s):} @code{vrecpe.u32 @var{q0}, @var{q0}}
4662
@end itemize
4663
 
4664
 
4665
 
4666
 
4667
@subsubsection Reciprocal square-root estimate
4668
 
4669
@itemize @bullet
4670
@item float32x2_t vrsqrte_f32 (float32x2_t)
4671
@*@emph{Form of expected instruction(s):} @code{vrsqrte.f32 @var{d0}, @var{d0}}
4672
@end itemize
4673
 
4674
 
4675
@itemize @bullet
4676
@item uint32x2_t vrsqrte_u32 (uint32x2_t)
4677
@*@emph{Form of expected instruction(s):} @code{vrsqrte.u32 @var{d0}, @var{d0}}
4678
@end itemize
4679
 
4680
 
4681
@itemize @bullet
4682
@item float32x4_t vrsqrteq_f32 (float32x4_t)
4683
@*@emph{Form of expected instruction(s):} @code{vrsqrte.f32 @var{q0}, @var{q0}}
4684
@end itemize
4685
 
4686
 
4687
@itemize @bullet
4688
@item uint32x4_t vrsqrteq_u32 (uint32x4_t)
4689
@*@emph{Form of expected instruction(s):} @code{vrsqrte.u32 @var{q0}, @var{q0}}
4690
@end itemize
4691
 
4692
 
4693
 
4694
 
4695
@subsubsection Get lanes from a vector
4696
 
4697
@itemize @bullet
4698
@item uint32_t vget_lane_u32 (uint32x2_t, const int)
4699
@*@emph{Form of expected instruction(s):} @code{vmov.32 @var{r0}, @var{d0}[@var{0}]}
4700
@end itemize
4701
 
4702
 
4703
@itemize @bullet
4704
@item uint16_t vget_lane_u16 (uint16x4_t, const int)
4705
@*@emph{Form of expected instruction(s):} @code{vmov.u16 @var{r0}, @var{d0}[@var{0}]}
4706
@end itemize
4707
 
4708
 
4709
@itemize @bullet
4710
@item uint8_t vget_lane_u8 (uint8x8_t, const int)
4711
@*@emph{Form of expected instruction(s):} @code{vmov.u8 @var{r0}, @var{d0}[@var{0}]}
4712
@end itemize
4713
 
4714
 
4715
@itemize @bullet
4716
@item int32_t vget_lane_s32 (int32x2_t, const int)
4717
@*@emph{Form of expected instruction(s):} @code{vmov.32 @var{r0}, @var{d0}[@var{0}]}
4718
@end itemize
4719
 
4720
 
4721
@itemize @bullet
4722
@item int16_t vget_lane_s16 (int16x4_t, const int)
4723
@*@emph{Form of expected instruction(s):} @code{vmov.s16 @var{r0}, @var{d0}[@var{0}]}
4724
@end itemize
4725
 
4726
 
4727
@itemize @bullet
4728
@item int8_t vget_lane_s8 (int8x8_t, const int)
4729
@*@emph{Form of expected instruction(s):} @code{vmov.s8 @var{r0}, @var{d0}[@var{0}]}
4730
@end itemize
4731
 
4732
 
4733
@itemize @bullet
4734
@item float32_t vget_lane_f32 (float32x2_t, const int)
4735
@*@emph{Form of expected instruction(s):} @code{vmov.32 @var{r0}, @var{d0}[@var{0}]}
4736
@end itemize
4737
 
4738
 
4739
@itemize @bullet
4740
@item poly16_t vget_lane_p16 (poly16x4_t, const int)
4741
@*@emph{Form of expected instruction(s):} @code{vmov.u16 @var{r0}, @var{d0}[@var{0}]}
4742
@end itemize
4743
 
4744
 
4745
@itemize @bullet
4746
@item poly8_t vget_lane_p8 (poly8x8_t, const int)
4747
@*@emph{Form of expected instruction(s):} @code{vmov.u8 @var{r0}, @var{d0}[@var{0}]}
4748
@end itemize
4749
 
4750
 
4751
@itemize @bullet
4752
@item uint64_t vget_lane_u64 (uint64x1_t, const int)
4753
@*@emph{Form of expected instruction(s):} @code{vmov @var{r0}, @var{r0}, @var{d0}}
4754
@end itemize
4755
 
4756
 
4757
@itemize @bullet
4758
@item int64_t vget_lane_s64 (int64x1_t, const int)
4759
@*@emph{Form of expected instruction(s):} @code{vmov @var{r0}, @var{r0}, @var{d0}}
4760
@end itemize
4761
 
4762
 
4763
@itemize @bullet
4764
@item uint32_t vgetq_lane_u32 (uint32x4_t, const int)
4765
@*@emph{Form of expected instruction(s):} @code{vmov.32 @var{r0}, @var{d0}[@var{0}]}
4766
@end itemize
4767
 
4768
 
4769
@itemize @bullet
4770
@item uint16_t vgetq_lane_u16 (uint16x8_t, const int)
4771
@*@emph{Form of expected instruction(s):} @code{vmov.u16 @var{r0}, @var{d0}[@var{0}]}
4772
@end itemize
4773
 
4774
 
4775
@itemize @bullet
4776
@item uint8_t vgetq_lane_u8 (uint8x16_t, const int)
4777
@*@emph{Form of expected instruction(s):} @code{vmov.u8 @var{r0}, @var{d0}[@var{0}]}
4778
@end itemize
4779
 
4780
 
4781
@itemize @bullet
4782
@item int32_t vgetq_lane_s32 (int32x4_t, const int)
4783
@*@emph{Form of expected instruction(s):} @code{vmov.32 @var{r0}, @var{d0}[@var{0}]}
4784
@end itemize
4785
 
4786
 
4787
@itemize @bullet
4788
@item int16_t vgetq_lane_s16 (int16x8_t, const int)
4789
@*@emph{Form of expected instruction(s):} @code{vmov.s16 @var{r0}, @var{d0}[@var{0}]}
4790
@end itemize
4791
 
4792
 
4793
@itemize @bullet
4794
@item int8_t vgetq_lane_s8 (int8x16_t, const int)
4795
@*@emph{Form of expected instruction(s):} @code{vmov.s8 @var{r0}, @var{d0}[@var{0}]}
4796
@end itemize
4797
 
4798
 
4799
@itemize @bullet
4800
@item float32_t vgetq_lane_f32 (float32x4_t, const int)
4801
@*@emph{Form of expected instruction(s):} @code{vmov.32 @var{r0}, @var{d0}[@var{0}]}
4802
@end itemize
4803
 
4804
 
4805
@itemize @bullet
4806
@item poly16_t vgetq_lane_p16 (poly16x8_t, const int)
4807
@*@emph{Form of expected instruction(s):} @code{vmov.u16 @var{r0}, @var{d0}[@var{0}]}
4808
@end itemize
4809
 
4810
 
4811
@itemize @bullet
4812
@item poly8_t vgetq_lane_p8 (poly8x16_t, const int)
4813
@*@emph{Form of expected instruction(s):} @code{vmov.u8 @var{r0}, @var{d0}[@var{0}]}
4814
@end itemize
4815
 
4816
 
4817
@itemize @bullet
4818
@item uint64_t vgetq_lane_u64 (uint64x2_t, const int)
4819
@*@emph{Form of expected instruction(s):} @code{vmov @var{r0}, @var{r0}, @var{d0}}
4820
@end itemize
4821
 
4822
 
4823
@itemize @bullet
4824
@item int64_t vgetq_lane_s64 (int64x2_t, const int)
4825
@*@emph{Form of expected instruction(s):} @code{vmov @var{r0}, @var{r0}, @var{d0}}
4826
@end itemize
4827
 
4828
 
4829
 
4830
 
4831
@subsubsection Set lanes in a vector
4832
 
4833
@itemize @bullet
4834
@item uint32x2_t vset_lane_u32 (uint32_t, uint32x2_t, const int)
4835
@*@emph{Form of expected instruction(s):} @code{vmov.32 @var{d0}[@var{0}], @var{r0}}
4836
@end itemize
4837
 
4838
 
4839
@itemize @bullet
4840
@item uint16x4_t vset_lane_u16 (uint16_t, uint16x4_t, const int)
4841
@*@emph{Form of expected instruction(s):} @code{vmov.16 @var{d0}[@var{0}], @var{r0}}
4842
@end itemize
4843
 
4844
 
4845
@itemize @bullet
4846
@item uint8x8_t vset_lane_u8 (uint8_t, uint8x8_t, const int)
4847
@*@emph{Form of expected instruction(s):} @code{vmov.8 @var{d0}[@var{0}], @var{r0}}
4848
@end itemize
4849
 
4850
 
4851
@itemize @bullet
4852
@item int32x2_t vset_lane_s32 (int32_t, int32x2_t, const int)
4853
@*@emph{Form of expected instruction(s):} @code{vmov.32 @var{d0}[@var{0}], @var{r0}}
4854
@end itemize
4855
 
4856
 
4857
@itemize @bullet
4858
@item int16x4_t vset_lane_s16 (int16_t, int16x4_t, const int)
4859
@*@emph{Form of expected instruction(s):} @code{vmov.16 @var{d0}[@var{0}], @var{r0}}
4860
@end itemize
4861
 
4862
 
4863
@itemize @bullet
4864
@item int8x8_t vset_lane_s8 (int8_t, int8x8_t, const int)
4865
@*@emph{Form of expected instruction(s):} @code{vmov.8 @var{d0}[@var{0}], @var{r0}}
4866
@end itemize
4867
 
4868
 
4869
@itemize @bullet
4870
@item float32x2_t vset_lane_f32 (float32_t, float32x2_t, const int)
4871
@*@emph{Form of expected instruction(s):} @code{vmov.32 @var{d0}[@var{0}], @var{r0}}
4872
@end itemize
4873
 
4874
 
4875
@itemize @bullet
4876
@item poly16x4_t vset_lane_p16 (poly16_t, poly16x4_t, const int)
4877
@*@emph{Form of expected instruction(s):} @code{vmov.16 @var{d0}[@var{0}], @var{r0}}
4878
@end itemize
4879
 
4880
 
4881
@itemize @bullet
4882
@item poly8x8_t vset_lane_p8 (poly8_t, poly8x8_t, const int)
4883
@*@emph{Form of expected instruction(s):} @code{vmov.8 @var{d0}[@var{0}], @var{r0}}
4884
@end itemize
4885
 
4886
 
4887
@itemize @bullet
4888
@item uint64x1_t vset_lane_u64 (uint64_t, uint64x1_t, const int)
4889
@*@emph{Form of expected instruction(s):} @code{vmov @var{d0}, @var{r0}, @var{r0}}
4890
@end itemize
4891
 
4892
 
4893
@itemize @bullet
4894
@item int64x1_t vset_lane_s64 (int64_t, int64x1_t, const int)
4895
@*@emph{Form of expected instruction(s):} @code{vmov @var{d0}, @var{r0}, @var{r0}}
4896
@end itemize
4897
 
4898
 
4899
@itemize @bullet
4900
@item uint32x4_t vsetq_lane_u32 (uint32_t, uint32x4_t, const int)
4901
@*@emph{Form of expected instruction(s):} @code{vmov.32 @var{d0}[@var{0}], @var{r0}}
4902
@end itemize
4903
 
4904
 
4905
@itemize @bullet
4906
@item uint16x8_t vsetq_lane_u16 (uint16_t, uint16x8_t, const int)
4907
@*@emph{Form of expected instruction(s):} @code{vmov.16 @var{d0}[@var{0}], @var{r0}}
4908
@end itemize
4909
 
4910
 
4911
@itemize @bullet
4912
@item uint8x16_t vsetq_lane_u8 (uint8_t, uint8x16_t, const int)
4913
@*@emph{Form of expected instruction(s):} @code{vmov.8 @var{d0}[@var{0}], @var{r0}}
4914
@end itemize
4915
 
4916
 
4917
@itemize @bullet
4918
@item int32x4_t vsetq_lane_s32 (int32_t, int32x4_t, const int)
4919
@*@emph{Form of expected instruction(s):} @code{vmov.32 @var{d0}[@var{0}], @var{r0}}
4920
@end itemize
4921
 
4922
 
4923
@itemize @bullet
4924
@item int16x8_t vsetq_lane_s16 (int16_t, int16x8_t, const int)
4925
@*@emph{Form of expected instruction(s):} @code{vmov.16 @var{d0}[@var{0}], @var{r0}}
4926
@end itemize
4927
 
4928
 
4929
@itemize @bullet
4930
@item int8x16_t vsetq_lane_s8 (int8_t, int8x16_t, const int)
4931
@*@emph{Form of expected instruction(s):} @code{vmov.8 @var{d0}[@var{0}], @var{r0}}
4932
@end itemize
4933
 
4934
 
4935
@itemize @bullet
4936
@item float32x4_t vsetq_lane_f32 (float32_t, float32x4_t, const int)
4937
@*@emph{Form of expected instruction(s):} @code{vmov.32 @var{d0}[@var{0}], @var{r0}}
4938
@end itemize
4939
 
4940
 
4941
@itemize @bullet
4942
@item poly16x8_t vsetq_lane_p16 (poly16_t, poly16x8_t, const int)
4943
@*@emph{Form of expected instruction(s):} @code{vmov.16 @var{d0}[@var{0}], @var{r0}}
4944
@end itemize
4945
 
4946
 
4947
@itemize @bullet
4948
@item poly8x16_t vsetq_lane_p8 (poly8_t, poly8x16_t, const int)
4949
@*@emph{Form of expected instruction(s):} @code{vmov.8 @var{d0}[@var{0}], @var{r0}}
4950
@end itemize
4951
 
4952
 
4953
@itemize @bullet
4954
@item uint64x2_t vsetq_lane_u64 (uint64_t, uint64x2_t, const int)
4955
@*@emph{Form of expected instruction(s):} @code{vmov @var{d0}, @var{r0}, @var{r0}}
4956
@end itemize
4957
 
4958
 
4959
@itemize @bullet
4960
@item int64x2_t vsetq_lane_s64 (int64_t, int64x2_t, const int)
4961
@*@emph{Form of expected instruction(s):} @code{vmov @var{d0}, @var{r0}, @var{r0}}
4962
@end itemize
4963
 
4964
 
4965
 
4966
 
4967
@subsubsection Create vector from literal bit pattern
4968
 
4969
@itemize @bullet
4970
@item uint32x2_t vcreate_u32 (uint64_t)
4971
@end itemize
4972
 
4973
 
4974
@itemize @bullet
4975
@item uint16x4_t vcreate_u16 (uint64_t)
4976
@end itemize
4977
 
4978
 
4979
@itemize @bullet
4980
@item uint8x8_t vcreate_u8 (uint64_t)
4981
@end itemize
4982
 
4983
 
4984
@itemize @bullet
4985
@item int32x2_t vcreate_s32 (uint64_t)
4986
@end itemize
4987
 
4988
 
4989
@itemize @bullet
4990
@item int16x4_t vcreate_s16 (uint64_t)
4991
@end itemize
4992
 
4993
 
4994
@itemize @bullet
4995
@item int8x8_t vcreate_s8 (uint64_t)
4996
@end itemize
4997
 
4998
 
4999
@itemize @bullet
5000
@item uint64x1_t vcreate_u64 (uint64_t)
5001
@end itemize
5002
 
5003
 
5004
@itemize @bullet
5005
@item int64x1_t vcreate_s64 (uint64_t)
5006
@end itemize
5007
 
5008
 
5009
@itemize @bullet
5010
@item float32x2_t vcreate_f32 (uint64_t)
5011
@end itemize
5012
 
5013
 
5014
@itemize @bullet
5015
@item poly16x4_t vcreate_p16 (uint64_t)
5016
@end itemize
5017
 
5018
 
5019
@itemize @bullet
5020
@item poly8x8_t vcreate_p8 (uint64_t)
5021
@end itemize
5022
 
5023
 
5024
 
5025
 
5026
@subsubsection Set all lanes to the same value
5027
 
5028
@itemize @bullet
5029
@item uint32x2_t vdup_n_u32 (uint32_t)
5030
@*@emph{Form of expected instruction(s):} @code{vdup.32 @var{d0}, @var{r0}}
5031
@end itemize
5032
 
5033
 
5034
@itemize @bullet
5035
@item uint16x4_t vdup_n_u16 (uint16_t)
5036
@*@emph{Form of expected instruction(s):} @code{vdup.16 @var{d0}, @var{r0}}
5037
@end itemize
5038
 
5039
 
5040
@itemize @bullet
5041
@item uint8x8_t vdup_n_u8 (uint8_t)
5042
@*@emph{Form of expected instruction(s):} @code{vdup.8 @var{d0}, @var{r0}}
5043
@end itemize
5044
 
5045
 
5046
@itemize @bullet
5047
@item int32x2_t vdup_n_s32 (int32_t)
5048
@*@emph{Form of expected instruction(s):} @code{vdup.32 @var{d0}, @var{r0}}
5049
@end itemize
5050
 
5051
 
5052
@itemize @bullet
5053
@item int16x4_t vdup_n_s16 (int16_t)
5054
@*@emph{Form of expected instruction(s):} @code{vdup.16 @var{d0}, @var{r0}}
5055
@end itemize
5056
 
5057
 
5058
@itemize @bullet
5059
@item int8x8_t vdup_n_s8 (int8_t)
5060
@*@emph{Form of expected instruction(s):} @code{vdup.8 @var{d0}, @var{r0}}
5061
@end itemize
5062
 
5063
 
5064
@itemize @bullet
5065
@item float32x2_t vdup_n_f32 (float32_t)
5066
@*@emph{Form of expected instruction(s):} @code{vdup.32 @var{d0}, @var{r0}}
5067
@end itemize
5068
 
5069
 
5070
@itemize @bullet
5071
@item poly16x4_t vdup_n_p16 (poly16_t)
5072
@*@emph{Form of expected instruction(s):} @code{vdup.16 @var{d0}, @var{r0}}
5073
@end itemize
5074
 
5075
 
5076
@itemize @bullet
5077
@item poly8x8_t vdup_n_p8 (poly8_t)
5078
@*@emph{Form of expected instruction(s):} @code{vdup.8 @var{d0}, @var{r0}}
5079
@end itemize
5080
 
5081
 
5082
@itemize @bullet
5083
@item uint64x1_t vdup_n_u64 (uint64_t)
5084
@*@emph{Form of expected instruction(s):} @code{vmov @var{d0}, @var{r0}, @var{r0}}
5085
@end itemize
5086
 
5087
 
5088
@itemize @bullet
5089
@item int64x1_t vdup_n_s64 (int64_t)
5090
@*@emph{Form of expected instruction(s):} @code{vmov @var{d0}, @var{r0}, @var{r0}}
5091
@end itemize
5092
 
5093
 
5094
@itemize @bullet
5095
@item uint32x4_t vdupq_n_u32 (uint32_t)
5096
@*@emph{Form of expected instruction(s):} @code{vdup.32 @var{q0}, @var{r0}}
5097
@end itemize
5098
 
5099
 
5100
@itemize @bullet
5101
@item uint16x8_t vdupq_n_u16 (uint16_t)
5102
@*@emph{Form of expected instruction(s):} @code{vdup.16 @var{q0}, @var{r0}}
5103
@end itemize
5104
 
5105
 
5106
@itemize @bullet
5107
@item uint8x16_t vdupq_n_u8 (uint8_t)
5108
@*@emph{Form of expected instruction(s):} @code{vdup.8 @var{q0}, @var{r0}}
5109
@end itemize
5110
 
5111
 
5112
@itemize @bullet
5113
@item int32x4_t vdupq_n_s32 (int32_t)
5114
@*@emph{Form of expected instruction(s):} @code{vdup.32 @var{q0}, @var{r0}}
5115
@end itemize
5116
 
5117
 
5118
@itemize @bullet
5119
@item int16x8_t vdupq_n_s16 (int16_t)
5120
@*@emph{Form of expected instruction(s):} @code{vdup.16 @var{q0}, @var{r0}}
5121
@end itemize
5122
 
5123
 
5124
@itemize @bullet
5125
@item int8x16_t vdupq_n_s8 (int8_t)
5126
@*@emph{Form of expected instruction(s):} @code{vdup.8 @var{q0}, @var{r0}}
5127
@end itemize
5128
 
5129
 
5130
@itemize @bullet
5131
@item float32x4_t vdupq_n_f32 (float32_t)
5132
@*@emph{Form of expected instruction(s):} @code{vdup.32 @var{q0}, @var{r0}}
5133
@end itemize
5134
 
5135
 
5136
@itemize @bullet
5137
@item poly16x8_t vdupq_n_p16 (poly16_t)
5138
@*@emph{Form of expected instruction(s):} @code{vdup.16 @var{q0}, @var{r0}}
5139
@end itemize
5140
 
5141
 
5142
@itemize @bullet
5143
@item poly8x16_t vdupq_n_p8 (poly8_t)
5144
@*@emph{Form of expected instruction(s):} @code{vdup.8 @var{q0}, @var{r0}}
5145
@end itemize
5146
 
5147
 
5148
@itemize @bullet
5149
@item uint64x2_t vdupq_n_u64 (uint64_t)
5150
@*@emph{Form of expected instruction(s):} @code{vmov @var{d0}, @var{r0}, @var{r0}}
5151
@end itemize
5152
 
5153
 
5154
@itemize @bullet
5155
@item int64x2_t vdupq_n_s64 (int64_t)
5156
@*@emph{Form of expected instruction(s):} @code{vmov @var{d0}, @var{r0}, @var{r0}}
5157
@end itemize
5158
 
5159
 
5160
@itemize @bullet
5161
@item uint32x2_t vmov_n_u32 (uint32_t)
5162
@*@emph{Form of expected instruction(s):} @code{vdup.32 @var{d0}, @var{r0}}
5163
@end itemize
5164
 
5165
 
5166
@itemize @bullet
5167
@item uint16x4_t vmov_n_u16 (uint16_t)
5168
@*@emph{Form of expected instruction(s):} @code{vdup.16 @var{d0}, @var{r0}}
5169
@end itemize
5170
 
5171
 
5172
@itemize @bullet
5173
@item uint8x8_t vmov_n_u8 (uint8_t)
5174
@*@emph{Form of expected instruction(s):} @code{vdup.8 @var{d0}, @var{r0}}
5175
@end itemize
5176
 
5177
 
5178
@itemize @bullet
5179
@item int32x2_t vmov_n_s32 (int32_t)
5180
@*@emph{Form of expected instruction(s):} @code{vdup.32 @var{d0}, @var{r0}}
5181
@end itemize
5182
 
5183
 
5184
@itemize @bullet
5185
@item int16x4_t vmov_n_s16 (int16_t)
5186
@*@emph{Form of expected instruction(s):} @code{vdup.16 @var{d0}, @var{r0}}
5187
@end itemize
5188
 
5189
 
5190
@itemize @bullet
5191
@item int8x8_t vmov_n_s8 (int8_t)
5192
@*@emph{Form of expected instruction(s):} @code{vdup.8 @var{d0}, @var{r0}}
5193
@end itemize
5194
 
5195
 
5196
@itemize @bullet
5197
@item float32x2_t vmov_n_f32 (float32_t)
5198
@*@emph{Form of expected instruction(s):} @code{vdup.32 @var{d0}, @var{r0}}
5199
@end itemize
5200
 
5201
 
5202
@itemize @bullet
5203
@item poly16x4_t vmov_n_p16 (poly16_t)
5204
@*@emph{Form of expected instruction(s):} @code{vdup.16 @var{d0}, @var{r0}}
5205
@end itemize
5206
 
5207
 
5208
@itemize @bullet
5209
@item poly8x8_t vmov_n_p8 (poly8_t)
5210
@*@emph{Form of expected instruction(s):} @code{vdup.8 @var{d0}, @var{r0}}
5211
@end itemize
5212
 
5213
 
5214
@itemize @bullet
5215
@item uint64x1_t vmov_n_u64 (uint64_t)
5216
@*@emph{Form of expected instruction(s):} @code{vmov @var{d0}, @var{r0}, @var{r0}}
5217
@end itemize
5218
 
5219
 
5220
@itemize @bullet
5221
@item int64x1_t vmov_n_s64 (int64_t)
5222
@*@emph{Form of expected instruction(s):} @code{vmov @var{d0}, @var{r0}, @var{r0}}
5223
@end itemize
5224
 
5225
 
5226
@itemize @bullet
5227
@item uint32x4_t vmovq_n_u32 (uint32_t)
5228
@*@emph{Form of expected instruction(s):} @code{vdup.32 @var{q0}, @var{r0}}
5229
@end itemize
5230
 
5231
 
5232
@itemize @bullet
5233
@item uint16x8_t vmovq_n_u16 (uint16_t)
5234
@*@emph{Form of expected instruction(s):} @code{vdup.16 @var{q0}, @var{r0}}
5235
@end itemize
5236
 
5237
 
5238
@itemize @bullet
5239
@item uint8x16_t vmovq_n_u8 (uint8_t)
5240
@*@emph{Form of expected instruction(s):} @code{vdup.8 @var{q0}, @var{r0}}
5241
@end itemize
5242
 
5243
 
5244
@itemize @bullet
5245
@item int32x4_t vmovq_n_s32 (int32_t)
5246
@*@emph{Form of expected instruction(s):} @code{vdup.32 @var{q0}, @var{r0}}
5247
@end itemize
5248
 
5249
 
5250
@itemize @bullet
5251
@item int16x8_t vmovq_n_s16 (int16_t)
5252
@*@emph{Form of expected instruction(s):} @code{vdup.16 @var{q0}, @var{r0}}
5253
@end itemize
5254
 
5255
 
5256
@itemize @bullet
5257
@item int8x16_t vmovq_n_s8 (int8_t)
5258
@*@emph{Form of expected instruction(s):} @code{vdup.8 @var{q0}, @var{r0}}
5259
@end itemize
5260
 
5261
 
5262
@itemize @bullet
5263
@item float32x4_t vmovq_n_f32 (float32_t)
5264
@*@emph{Form of expected instruction(s):} @code{vdup.32 @var{q0}, @var{r0}}
5265
@end itemize
5266
 
5267
 
5268
@itemize @bullet
5269
@item poly16x8_t vmovq_n_p16 (poly16_t)
5270
@*@emph{Form of expected instruction(s):} @code{vdup.16 @var{q0}, @var{r0}}
5271
@end itemize
5272
 
5273
 
5274
@itemize @bullet
5275
@item poly8x16_t vmovq_n_p8 (poly8_t)
5276
@*@emph{Form of expected instruction(s):} @code{vdup.8 @var{q0}, @var{r0}}
5277
@end itemize
5278
 
5279
 
5280
@itemize @bullet
5281
@item uint64x2_t vmovq_n_u64 (uint64_t)
5282
@*@emph{Form of expected instruction(s):} @code{vmov @var{d0}, @var{r0}, @var{r0}}
5283
@end itemize
5284
 
5285
 
5286
@itemize @bullet
5287
@item int64x2_t vmovq_n_s64 (int64_t)
5288
@*@emph{Form of expected instruction(s):} @code{vmov @var{d0}, @var{r0}, @var{r0}}
5289
@end itemize
5290
 
5291
 
5292
@itemize @bullet
5293
@item uint32x2_t vdup_lane_u32 (uint32x2_t, const int)
5294
@*@emph{Form of expected instruction(s):} @code{vdup.32 @var{d0}, @var{d0}[@var{0}]}
5295
@end itemize
5296
 
5297
 
5298
@itemize @bullet
5299
@item uint16x4_t vdup_lane_u16 (uint16x4_t, const int)
5300
@*@emph{Form of expected instruction(s):} @code{vdup.16 @var{d0}, @var{d0}[@var{0}]}
5301
@end itemize
5302
 
5303
 
5304
@itemize @bullet
5305
@item uint8x8_t vdup_lane_u8 (uint8x8_t, const int)
5306
@*@emph{Form of expected instruction(s):} @code{vdup.8 @var{d0}, @var{d0}[@var{0}]}
5307
@end itemize
5308
 
5309
 
5310
@itemize @bullet
5311
@item int32x2_t vdup_lane_s32 (int32x2_t, const int)
5312
@*@emph{Form of expected instruction(s):} @code{vdup.32 @var{d0}, @var{d0}[@var{0}]}
5313
@end itemize
5314
 
5315
 
5316
@itemize @bullet
5317
@item int16x4_t vdup_lane_s16 (int16x4_t, const int)
5318
@*@emph{Form of expected instruction(s):} @code{vdup.16 @var{d0}, @var{d0}[@var{0}]}
5319
@end itemize
5320
 
5321
 
5322
@itemize @bullet
5323
@item int8x8_t vdup_lane_s8 (int8x8_t, const int)
5324
@*@emph{Form of expected instruction(s):} @code{vdup.8 @var{d0}, @var{d0}[@var{0}]}
5325
@end itemize
5326
 
5327
 
5328
@itemize @bullet
5329
@item float32x2_t vdup_lane_f32 (float32x2_t, const int)
5330
@*@emph{Form of expected instruction(s):} @code{vdup.32 @var{d0}, @var{d0}[@var{0}]}
5331
@end itemize
5332
 
5333
 
5334
@itemize @bullet
5335
@item poly16x4_t vdup_lane_p16 (poly16x4_t, const int)
5336
@*@emph{Form of expected instruction(s):} @code{vdup.16 @var{d0}, @var{d0}[@var{0}]}
5337
@end itemize
5338
 
5339
 
5340
@itemize @bullet
5341
@item poly8x8_t vdup_lane_p8 (poly8x8_t, const int)
5342
@*@emph{Form of expected instruction(s):} @code{vdup.8 @var{d0}, @var{d0}[@var{0}]}
5343
@end itemize
5344
 
5345
 
5346
@itemize @bullet
5347
@item uint64x1_t vdup_lane_u64 (uint64x1_t, const int)
5348
@end itemize
5349
 
5350
 
5351
@itemize @bullet
5352
@item int64x1_t vdup_lane_s64 (int64x1_t, const int)
5353
@end itemize
5354
 
5355
 
5356
@itemize @bullet
5357
@item uint32x4_t vdupq_lane_u32 (uint32x2_t, const int)
5358
@*@emph{Form of expected instruction(s):} @code{vdup.32 @var{q0}, @var{d0}[@var{0}]}
5359
@end itemize
5360
 
5361
 
5362
@itemize @bullet
5363
@item uint16x8_t vdupq_lane_u16 (uint16x4_t, const int)
5364
@*@emph{Form of expected instruction(s):} @code{vdup.16 @var{q0}, @var{d0}[@var{0}]}
5365
@end itemize
5366
 
5367
 
5368
@itemize @bullet
5369
@item uint8x16_t vdupq_lane_u8 (uint8x8_t, const int)
5370
@*@emph{Form of expected instruction(s):} @code{vdup.8 @var{q0}, @var{d0}[@var{0}]}
5371
@end itemize
5372
 
5373
 
5374
@itemize @bullet
5375
@item int32x4_t vdupq_lane_s32 (int32x2_t, const int)
5376
@*@emph{Form of expected instruction(s):} @code{vdup.32 @var{q0}, @var{d0}[@var{0}]}
5377
@end itemize
5378
 
5379
 
5380
@itemize @bullet
5381
@item int16x8_t vdupq_lane_s16 (int16x4_t, const int)
5382
@*@emph{Form of expected instruction(s):} @code{vdup.16 @var{q0}, @var{d0}[@var{0}]}
5383
@end itemize
5384
 
5385
 
5386
@itemize @bullet
5387
@item int8x16_t vdupq_lane_s8 (int8x8_t, const int)
5388
@*@emph{Form of expected instruction(s):} @code{vdup.8 @var{q0}, @var{d0}[@var{0}]}
5389
@end itemize
5390
 
5391
 
5392
@itemize @bullet
5393
@item float32x4_t vdupq_lane_f32 (float32x2_t, const int)
5394
@*@emph{Form of expected instruction(s):} @code{vdup.32 @var{q0}, @var{d0}[@var{0}]}
5395
@end itemize
5396
 
5397
 
5398
@itemize @bullet
5399
@item poly16x8_t vdupq_lane_p16 (poly16x4_t, const int)
5400
@*@emph{Form of expected instruction(s):} @code{vdup.16 @var{q0}, @var{d0}[@var{0}]}
5401
@end itemize
5402
 
5403
 
5404
@itemize @bullet
5405
@item poly8x16_t vdupq_lane_p8 (poly8x8_t, const int)
5406
@*@emph{Form of expected instruction(s):} @code{vdup.8 @var{q0}, @var{d0}[@var{0}]}
5407
@end itemize
5408
 
5409
 
5410
@itemize @bullet
5411
@item uint64x2_t vdupq_lane_u64 (uint64x1_t, const int)
5412
@end itemize
5413
 
5414
 
5415
@itemize @bullet
5416
@item int64x2_t vdupq_lane_s64 (int64x1_t, const int)
5417
@end itemize
5418
 
5419
 
5420
 
5421
 
5422
@subsubsection Combining vectors
5423
 
5424
@itemize @bullet
5425
@item uint32x4_t vcombine_u32 (uint32x2_t, uint32x2_t)
5426
@end itemize
5427
 
5428
 
5429
@itemize @bullet
5430
@item uint16x8_t vcombine_u16 (uint16x4_t, uint16x4_t)
5431
@end itemize
5432
 
5433
 
5434
@itemize @bullet
5435
@item uint8x16_t vcombine_u8 (uint8x8_t, uint8x8_t)
5436
@end itemize
5437
 
5438
 
5439
@itemize @bullet
5440
@item int32x4_t vcombine_s32 (int32x2_t, int32x2_t)
5441
@end itemize
5442
 
5443
 
5444
@itemize @bullet
5445
@item int16x8_t vcombine_s16 (int16x4_t, int16x4_t)
5446
@end itemize
5447
 
5448
 
5449
@itemize @bullet
5450
@item int8x16_t vcombine_s8 (int8x8_t, int8x8_t)
5451
@end itemize
5452
 
5453
 
5454
@itemize @bullet
5455
@item uint64x2_t vcombine_u64 (uint64x1_t, uint64x1_t)
5456
@end itemize
5457
 
5458
 
5459
@itemize @bullet
5460
@item int64x2_t vcombine_s64 (int64x1_t, int64x1_t)
5461
@end itemize
5462
 
5463
 
5464
@itemize @bullet
5465
@item float32x4_t vcombine_f32 (float32x2_t, float32x2_t)
5466
@end itemize
5467
 
5468
 
5469
@itemize @bullet
5470
@item poly16x8_t vcombine_p16 (poly16x4_t, poly16x4_t)
5471
@end itemize
5472
 
5473
 
5474
@itemize @bullet
5475
@item poly8x16_t vcombine_p8 (poly8x8_t, poly8x8_t)
5476
@end itemize
5477
 
5478
 
5479
 
5480
 
5481
@subsubsection Splitting vectors
5482
 
5483
@itemize @bullet
5484
@item uint32x2_t vget_high_u32 (uint32x4_t)
5485
@end itemize
5486
 
5487
 
5488
@itemize @bullet
5489
@item uint16x4_t vget_high_u16 (uint16x8_t)
5490
@end itemize
5491
 
5492
 
5493
@itemize @bullet
5494
@item uint8x8_t vget_high_u8 (uint8x16_t)
5495
@end itemize
5496
 
5497
 
5498
@itemize @bullet
5499
@item int32x2_t vget_high_s32 (int32x4_t)
5500
@end itemize
5501
 
5502
 
5503
@itemize @bullet
5504
@item int16x4_t vget_high_s16 (int16x8_t)
5505
@end itemize
5506
 
5507
 
5508
@itemize @bullet
5509
@item int8x8_t vget_high_s8 (int8x16_t)
5510
@end itemize
5511
 
5512
 
5513
@itemize @bullet
5514
@item uint64x1_t vget_high_u64 (uint64x2_t)
5515
@end itemize
5516
 
5517
 
5518
@itemize @bullet
5519
@item int64x1_t vget_high_s64 (int64x2_t)
5520
@end itemize
5521
 
5522
 
5523
@itemize @bullet
5524
@item float32x2_t vget_high_f32 (float32x4_t)
5525
@end itemize
5526
 
5527
 
5528
@itemize @bullet
5529
@item poly16x4_t vget_high_p16 (poly16x8_t)
5530
@end itemize
5531
 
5532
 
5533
@itemize @bullet
5534
@item poly8x8_t vget_high_p8 (poly8x16_t)
5535
@end itemize
5536
 
5537
 
5538
@itemize @bullet
5539
@item uint32x2_t vget_low_u32 (uint32x4_t)
5540
@*@emph{Form of expected instruction(s):} @code{vmov @var{d0}, @var{d0}}
5541
@end itemize
5542
 
5543
 
5544
@itemize @bullet
5545
@item uint16x4_t vget_low_u16 (uint16x8_t)
5546
@*@emph{Form of expected instruction(s):} @code{vmov @var{d0}, @var{d0}}
5547
@end itemize
5548
 
5549
 
5550
@itemize @bullet
5551
@item uint8x8_t vget_low_u8 (uint8x16_t)
5552
@*@emph{Form of expected instruction(s):} @code{vmov @var{d0}, @var{d0}}
5553
@end itemize
5554
 
5555
 
5556
@itemize @bullet
5557
@item int32x2_t vget_low_s32 (int32x4_t)
5558
@*@emph{Form of expected instruction(s):} @code{vmov @var{d0}, @var{d0}}
5559
@end itemize
5560
 
5561
 
5562
@itemize @bullet
5563
@item int16x4_t vget_low_s16 (int16x8_t)
5564
@*@emph{Form of expected instruction(s):} @code{vmov @var{d0}, @var{d0}}
5565
@end itemize
5566
 
5567
 
5568
@itemize @bullet
5569
@item int8x8_t vget_low_s8 (int8x16_t)
5570
@*@emph{Form of expected instruction(s):} @code{vmov @var{d0}, @var{d0}}
5571
@end itemize
5572
 
5573
 
5574
@itemize @bullet
5575
@item uint64x1_t vget_low_u64 (uint64x2_t)
5576
@*@emph{Form of expected instruction(s):} @code{vmov @var{d0}, @var{d0}}
5577
@end itemize
5578
 
5579
 
5580
@itemize @bullet
5581
@item int64x1_t vget_low_s64 (int64x2_t)
5582
@*@emph{Form of expected instruction(s):} @code{vmov @var{d0}, @var{d0}}
5583
@end itemize
5584
 
5585
 
5586
@itemize @bullet
5587
@item float32x2_t vget_low_f32 (float32x4_t)
5588
@*@emph{Form of expected instruction(s):} @code{vmov @var{d0}, @var{d0}}
5589
@end itemize
5590
 
5591
 
5592
@itemize @bullet
5593
@item poly16x4_t vget_low_p16 (poly16x8_t)
5594
@*@emph{Form of expected instruction(s):} @code{vmov @var{d0}, @var{d0}}
5595
@end itemize
5596
 
5597
 
5598
@itemize @bullet
5599
@item poly8x8_t vget_low_p8 (poly8x16_t)
5600
@*@emph{Form of expected instruction(s):} @code{vmov @var{d0}, @var{d0}}
5601
@end itemize
5602
 
5603
 
5604
 
5605
 
5606
@subsubsection Conversions
5607
 
5608
@itemize @bullet
5609
@item float32x2_t vcvt_f32_u32 (uint32x2_t)
5610
@*@emph{Form of expected instruction(s):} @code{vcvt.f32.u32 @var{d0}, @var{d0}}
5611
@end itemize
5612
 
5613
 
5614
@itemize @bullet
5615
@item float32x2_t vcvt_f32_s32 (int32x2_t)
5616
@*@emph{Form of expected instruction(s):} @code{vcvt.f32.s32 @var{d0}, @var{d0}}
5617
@end itemize
5618
 
5619
 
5620
@itemize @bullet
5621
@item uint32x2_t vcvt_u32_f32 (float32x2_t)
5622
@*@emph{Form of expected instruction(s):} @code{vcvt.u32.f32 @var{d0}, @var{d0}}
5623
@end itemize
5624
 
5625
 
5626
@itemize @bullet
5627
@item int32x2_t vcvt_s32_f32 (float32x2_t)
5628
@*@emph{Form of expected instruction(s):} @code{vcvt.s32.f32 @var{d0}, @var{d0}}
5629
@end itemize
5630
 
5631
 
5632
@itemize @bullet
5633
@item float32x4_t vcvtq_f32_u32 (uint32x4_t)
5634
@*@emph{Form of expected instruction(s):} @code{vcvt.f32.u32 @var{q0}, @var{q0}}
5635
@end itemize
5636
 
5637
 
5638
@itemize @bullet
5639
@item float32x4_t vcvtq_f32_s32 (int32x4_t)
5640
@*@emph{Form of expected instruction(s):} @code{vcvt.f32.s32 @var{q0}, @var{q0}}
5641
@end itemize
5642
 
5643
 
5644
@itemize @bullet
5645
@item uint32x4_t vcvtq_u32_f32 (float32x4_t)
5646
@*@emph{Form of expected instruction(s):} @code{vcvt.u32.f32 @var{q0}, @var{q0}}
5647
@end itemize
5648
 
5649
 
5650
@itemize @bullet
5651
@item int32x4_t vcvtq_s32_f32 (float32x4_t)
5652
@*@emph{Form of expected instruction(s):} @code{vcvt.s32.f32 @var{q0}, @var{q0}}
5653
@end itemize
5654
 
5655
 
5656
@itemize @bullet
5657
@item float32x2_t vcvt_n_f32_u32 (uint32x2_t, const int)
5658
@*@emph{Form of expected instruction(s):} @code{vcvt.f32.u32 @var{d0}, @var{d0}, #@var{0}}
5659
@end itemize
5660
 
5661
 
5662
@itemize @bullet
5663
@item float32x2_t vcvt_n_f32_s32 (int32x2_t, const int)
5664
@*@emph{Form of expected instruction(s):} @code{vcvt.f32.s32 @var{d0}, @var{d0}, #@var{0}}
5665
@end itemize
5666
 
5667
 
5668
@itemize @bullet
5669
@item uint32x2_t vcvt_n_u32_f32 (float32x2_t, const int)
5670
@*@emph{Form of expected instruction(s):} @code{vcvt.u32.f32 @var{d0}, @var{d0}, #@var{0}}
5671
@end itemize
5672
 
5673
 
5674
@itemize @bullet
5675
@item int32x2_t vcvt_n_s32_f32 (float32x2_t, const int)
5676
@*@emph{Form of expected instruction(s):} @code{vcvt.s32.f32 @var{d0}, @var{d0}, #@var{0}}
5677
@end itemize
5678
 
5679
 
5680
@itemize @bullet
5681
@item float32x4_t vcvtq_n_f32_u32 (uint32x4_t, const int)
5682
@*@emph{Form of expected instruction(s):} @code{vcvt.f32.u32 @var{q0}, @var{q0}, #@var{0}}
5683
@end itemize
5684
 
5685
 
5686
@itemize @bullet
5687
@item float32x4_t vcvtq_n_f32_s32 (int32x4_t, const int)
5688
@*@emph{Form of expected instruction(s):} @code{vcvt.f32.s32 @var{q0}, @var{q0}, #@var{0}}
5689
@end itemize
5690
 
5691
 
5692
@itemize @bullet
5693
@item uint32x4_t vcvtq_n_u32_f32 (float32x4_t, const int)
5694
@*@emph{Form of expected instruction(s):} @code{vcvt.u32.f32 @var{q0}, @var{q0}, #@var{0}}
5695
@end itemize
5696
 
5697
 
5698
@itemize @bullet
5699
@item int32x4_t vcvtq_n_s32_f32 (float32x4_t, const int)
5700
@*@emph{Form of expected instruction(s):} @code{vcvt.s32.f32 @var{q0}, @var{q0}, #@var{0}}
5701
@end itemize
5702
 
5703
 
5704
 
5705
 
5706
@subsubsection Move, single_opcode narrowing
5707
 
5708
@itemize @bullet
5709
@item uint32x2_t vmovn_u64 (uint64x2_t)
5710
@*@emph{Form of expected instruction(s):} @code{vmovn.i64 @var{d0}, @var{q0}}
5711
@end itemize
5712
 
5713
 
5714
@itemize @bullet
5715
@item uint16x4_t vmovn_u32 (uint32x4_t)
5716
@*@emph{Form of expected instruction(s):} @code{vmovn.i32 @var{d0}, @var{q0}}
5717
@end itemize
5718
 
5719
 
5720
@itemize @bullet
5721
@item uint8x8_t vmovn_u16 (uint16x8_t)
5722
@*@emph{Form of expected instruction(s):} @code{vmovn.i16 @var{d0}, @var{q0}}
5723
@end itemize
5724
 
5725
 
5726
@itemize @bullet
5727
@item int32x2_t vmovn_s64 (int64x2_t)
5728
@*@emph{Form of expected instruction(s):} @code{vmovn.i64 @var{d0}, @var{q0}}
5729
@end itemize
5730
 
5731
 
5732
@itemize @bullet
5733
@item int16x4_t vmovn_s32 (int32x4_t)
5734
@*@emph{Form of expected instruction(s):} @code{vmovn.i32 @var{d0}, @var{q0}}
5735
@end itemize
5736
 
5737
 
5738
@itemize @bullet
5739
@item int8x8_t vmovn_s16 (int16x8_t)
5740
@*@emph{Form of expected instruction(s):} @code{vmovn.i16 @var{d0}, @var{q0}}
5741
@end itemize
5742
 
5743
 
5744
@itemize @bullet
5745
@item uint32x2_t vqmovn_u64 (uint64x2_t)
5746
@*@emph{Form of expected instruction(s):} @code{vqmovn.u64 @var{d0}, @var{q0}}
5747
@end itemize
5748
 
5749
 
5750
@itemize @bullet
5751
@item uint16x4_t vqmovn_u32 (uint32x4_t)
5752
@*@emph{Form of expected instruction(s):} @code{vqmovn.u32 @var{d0}, @var{q0}}
5753
@end itemize
5754
 
5755
 
5756
@itemize @bullet
5757
@item uint8x8_t vqmovn_u16 (uint16x8_t)
5758
@*@emph{Form of expected instruction(s):} @code{vqmovn.u16 @var{d0}, @var{q0}}
5759
@end itemize
5760
 
5761
 
5762
@itemize @bullet
5763
@item int32x2_t vqmovn_s64 (int64x2_t)
5764
@*@emph{Form of expected instruction(s):} @code{vqmovn.s64 @var{d0}, @var{q0}}
5765
@end itemize
5766
 
5767
 
5768
@itemize @bullet
5769
@item int16x4_t vqmovn_s32 (int32x4_t)
5770
@*@emph{Form of expected instruction(s):} @code{vqmovn.s32 @var{d0}, @var{q0}}
5771
@end itemize
5772
 
5773
 
5774
@itemize @bullet
5775
@item int8x8_t vqmovn_s16 (int16x8_t)
5776
@*@emph{Form of expected instruction(s):} @code{vqmovn.s16 @var{d0}, @var{q0}}
5777
@end itemize
5778
 
5779
 
5780
@itemize @bullet
5781
@item uint32x2_t vqmovun_s64 (int64x2_t)
5782
@*@emph{Form of expected instruction(s):} @code{vqmovun.s64 @var{d0}, @var{q0}}
5783
@end itemize
5784
 
5785
 
5786
@itemize @bullet
5787
@item uint16x4_t vqmovun_s32 (int32x4_t)
5788
@*@emph{Form of expected instruction(s):} @code{vqmovun.s32 @var{d0}, @var{q0}}
5789
@end itemize
5790
 
5791
 
5792
@itemize @bullet
5793
@item uint8x8_t vqmovun_s16 (int16x8_t)
5794
@*@emph{Form of expected instruction(s):} @code{vqmovun.s16 @var{d0}, @var{q0}}
5795
@end itemize
5796
 
5797
 
5798
 
5799
 
5800
@subsubsection Move, single_opcode long
5801
 
5802
@itemize @bullet
5803
@item uint64x2_t vmovl_u32 (uint32x2_t)
5804
@*@emph{Form of expected instruction(s):} @code{vmovl.u32 @var{q0}, @var{d0}}
5805
@end itemize
5806
 
5807
 
5808
@itemize @bullet
5809
@item uint32x4_t vmovl_u16 (uint16x4_t)
5810
@*@emph{Form of expected instruction(s):} @code{vmovl.u16 @var{q0}, @var{d0}}
5811
@end itemize
5812
 
5813
 
5814
@itemize @bullet
5815
@item uint16x8_t vmovl_u8 (uint8x8_t)
5816
@*@emph{Form of expected instruction(s):} @code{vmovl.u8 @var{q0}, @var{d0}}
5817
@end itemize
5818
 
5819
 
5820
@itemize @bullet
5821
@item int64x2_t vmovl_s32 (int32x2_t)
5822
@*@emph{Form of expected instruction(s):} @code{vmovl.s32 @var{q0}, @var{d0}}
5823
@end itemize
5824
 
5825
 
5826
@itemize @bullet
5827
@item int32x4_t vmovl_s16 (int16x4_t)
5828
@*@emph{Form of expected instruction(s):} @code{vmovl.s16 @var{q0}, @var{d0}}
5829
@end itemize
5830
 
5831
 
5832
@itemize @bullet
5833
@item int16x8_t vmovl_s8 (int8x8_t)
5834
@*@emph{Form of expected instruction(s):} @code{vmovl.s8 @var{q0}, @var{d0}}
5835
@end itemize
5836
 
5837
 
5838
 
5839
 
5840
@subsubsection Table lookup
5841
 
5842
@itemize @bullet
5843
@item poly8x8_t vtbl1_p8 (poly8x8_t, uint8x8_t)
5844
@*@emph{Form of expected instruction(s):} @code{vtbl.8 @var{d0}, @{@var{d0}@}, @var{d0}}
5845
@end itemize
5846
 
5847
 
5848
@itemize @bullet
5849
@item int8x8_t vtbl1_s8 (int8x8_t, int8x8_t)
5850
@*@emph{Form of expected instruction(s):} @code{vtbl.8 @var{d0}, @{@var{d0}@}, @var{d0}}
5851
@end itemize
5852
 
5853
 
5854
@itemize @bullet
5855
@item uint8x8_t vtbl1_u8 (uint8x8_t, uint8x8_t)
5856
@*@emph{Form of expected instruction(s):} @code{vtbl.8 @var{d0}, @{@var{d0}@}, @var{d0}}
5857
@end itemize
5858
 
5859
 
5860
@itemize @bullet
5861
@item poly8x8_t vtbl2_p8 (poly8x8x2_t, uint8x8_t)
5862
@*@emph{Form of expected instruction(s):} @code{vtbl.8 @var{d0}, @{@var{d0}, @var{d1}@}, @var{d0}}
5863
@end itemize
5864
 
5865
 
5866
@itemize @bullet
5867
@item int8x8_t vtbl2_s8 (int8x8x2_t, int8x8_t)
5868
@*@emph{Form of expected instruction(s):} @code{vtbl.8 @var{d0}, @{@var{d0}, @var{d1}@}, @var{d0}}
5869
@end itemize
5870
 
5871
 
5872
@itemize @bullet
5873
@item uint8x8_t vtbl2_u8 (uint8x8x2_t, uint8x8_t)
5874
@*@emph{Form of expected instruction(s):} @code{vtbl.8 @var{d0}, @{@var{d0}, @var{d1}@}, @var{d0}}
5875
@end itemize
5876
 
5877
 
5878
@itemize @bullet
5879
@item poly8x8_t vtbl3_p8 (poly8x8x3_t, uint8x8_t)
5880
@*@emph{Form of expected instruction(s):} @code{vtbl.8 @var{d0}, @{@var{d0}, @var{d1}, @var{d2}@}, @var{d0}}
5881
@end itemize
5882
 
5883
 
5884
@itemize @bullet
5885
@item int8x8_t vtbl3_s8 (int8x8x3_t, int8x8_t)
5886
@*@emph{Form of expected instruction(s):} @code{vtbl.8 @var{d0}, @{@var{d0}, @var{d1}, @var{d2}@}, @var{d0}}
5887
@end itemize
5888
 
5889
 
5890
@itemize @bullet
5891
@item uint8x8_t vtbl3_u8 (uint8x8x3_t, uint8x8_t)
5892
@*@emph{Form of expected instruction(s):} @code{vtbl.8 @var{d0}, @{@var{d0}, @var{d1}, @var{d2}@}, @var{d0}}
5893
@end itemize
5894
 
5895
 
5896
@itemize @bullet
5897
@item poly8x8_t vtbl4_p8 (poly8x8x4_t, uint8x8_t)
5898
@*@emph{Form of expected instruction(s):} @code{vtbl.8 @var{d0}, @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, @var{d0}}
5899
@end itemize
5900
 
5901
 
5902
@itemize @bullet
5903
@item int8x8_t vtbl4_s8 (int8x8x4_t, int8x8_t)
5904
@*@emph{Form of expected instruction(s):} @code{vtbl.8 @var{d0}, @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, @var{d0}}
5905
@end itemize
5906
 
5907
 
5908
@itemize @bullet
5909
@item uint8x8_t vtbl4_u8 (uint8x8x4_t, uint8x8_t)
5910
@*@emph{Form of expected instruction(s):} @code{vtbl.8 @var{d0}, @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, @var{d0}}
5911
@end itemize
5912
 
5913
 
5914
 
5915
 
5916
@subsubsection Extended table lookup
5917
 
5918
@itemize @bullet
5919
@item poly8x8_t vtbx1_p8 (poly8x8_t, poly8x8_t, uint8x8_t)
5920
@*@emph{Form of expected instruction(s):} @code{vtbx.8 @var{d0}, @{@var{d0}@}, @var{d0}}
5921
@end itemize
5922
 
5923
 
5924
@itemize @bullet
5925
@item int8x8_t vtbx1_s8 (int8x8_t, int8x8_t, int8x8_t)
5926
@*@emph{Form of expected instruction(s):} @code{vtbx.8 @var{d0}, @{@var{d0}@}, @var{d0}}
5927
@end itemize
5928
 
5929
 
5930
@itemize @bullet
5931
@item uint8x8_t vtbx1_u8 (uint8x8_t, uint8x8_t, uint8x8_t)
5932
@*@emph{Form of expected instruction(s):} @code{vtbx.8 @var{d0}, @{@var{d0}@}, @var{d0}}
5933
@end itemize
5934
 
5935
 
5936
@itemize @bullet
5937
@item poly8x8_t vtbx2_p8 (poly8x8_t, poly8x8x2_t, uint8x8_t)
5938
@*@emph{Form of expected instruction(s):} @code{vtbx.8 @var{d0}, @{@var{d0}, @var{d1}@}, @var{d0}}
5939
@end itemize
5940
 
5941
 
5942
@itemize @bullet
5943
@item int8x8_t vtbx2_s8 (int8x8_t, int8x8x2_t, int8x8_t)
5944
@*@emph{Form of expected instruction(s):} @code{vtbx.8 @var{d0}, @{@var{d0}, @var{d1}@}, @var{d0}}
5945
@end itemize
5946
 
5947
 
5948
@itemize @bullet
5949
@item uint8x8_t vtbx2_u8 (uint8x8_t, uint8x8x2_t, uint8x8_t)
5950
@*@emph{Form of expected instruction(s):} @code{vtbx.8 @var{d0}, @{@var{d0}, @var{d1}@}, @var{d0}}
5951
@end itemize
5952
 
5953
 
5954
@itemize @bullet
5955
@item poly8x8_t vtbx3_p8 (poly8x8_t, poly8x8x3_t, uint8x8_t)
5956
@*@emph{Form of expected instruction(s):} @code{vtbx.8 @var{d0}, @{@var{d0}, @var{d1}, @var{d2}@}, @var{d0}}
5957
@end itemize
5958
 
5959
 
5960
@itemize @bullet
5961
@item int8x8_t vtbx3_s8 (int8x8_t, int8x8x3_t, int8x8_t)
5962
@*@emph{Form of expected instruction(s):} @code{vtbx.8 @var{d0}, @{@var{d0}, @var{d1}, @var{d2}@}, @var{d0}}
5963
@end itemize
5964
 
5965
 
5966
@itemize @bullet
5967
@item uint8x8_t vtbx3_u8 (uint8x8_t, uint8x8x3_t, uint8x8_t)
5968
@*@emph{Form of expected instruction(s):} @code{vtbx.8 @var{d0}, @{@var{d0}, @var{d1}, @var{d2}@}, @var{d0}}
5969
@end itemize
5970
 
5971
 
5972
@itemize @bullet
5973
@item poly8x8_t vtbx4_p8 (poly8x8_t, poly8x8x4_t, uint8x8_t)
5974
@*@emph{Form of expected instruction(s):} @code{vtbx.8 @var{d0}, @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, @var{d0}}
5975
@end itemize
5976
 
5977
 
5978
@itemize @bullet
5979
@item int8x8_t vtbx4_s8 (int8x8_t, int8x8x4_t, int8x8_t)
5980
@*@emph{Form of expected instruction(s):} @code{vtbx.8 @var{d0}, @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, @var{d0}}
5981
@end itemize
5982
 
5983
 
5984
@itemize @bullet
5985
@item uint8x8_t vtbx4_u8 (uint8x8_t, uint8x8x4_t, uint8x8_t)
5986
@*@emph{Form of expected instruction(s):} @code{vtbx.8 @var{d0}, @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, @var{d0}}
5987
@end itemize
5988
 
5989
 
5990
 
5991
 
5992
@subsubsection Multiply, lane
5993
 
5994
@itemize @bullet
5995
@item float32x2_t vmul_lane_f32 (float32x2_t, float32x2_t, const int)
5996
@*@emph{Form of expected instruction(s):} @code{vmul.f32 @var{d0}, @var{d0}, @var{d0}[@var{0}]}
5997
@end itemize
5998
 
5999
 
6000
@itemize @bullet
6001
@item uint32x2_t vmul_lane_u32 (uint32x2_t, uint32x2_t, const int)
6002
@*@emph{Form of expected instruction(s):} @code{vmul.i32 @var{d0}, @var{d0}, @var{d0}[@var{0}]}
6003
@end itemize
6004
 
6005
 
6006
@itemize @bullet
6007
@item uint16x4_t vmul_lane_u16 (uint16x4_t, uint16x4_t, const int)
6008
@*@emph{Form of expected instruction(s):} @code{vmul.i16 @var{d0}, @var{d0}, @var{d0}[@var{0}]}
6009
@end itemize
6010
 
6011
 
6012
@itemize @bullet
6013
@item int32x2_t vmul_lane_s32 (int32x2_t, int32x2_t, const int)
6014
@*@emph{Form of expected instruction(s):} @code{vmul.i32 @var{d0}, @var{d0}, @var{d0}[@var{0}]}
6015
@end itemize
6016
 
6017
 
6018
@itemize @bullet
6019
@item int16x4_t vmul_lane_s16 (int16x4_t, int16x4_t, const int)
6020
@*@emph{Form of expected instruction(s):} @code{vmul.i16 @var{d0}, @var{d0}, @var{d0}[@var{0}]}
6021
@end itemize
6022
 
6023
 
6024
@itemize @bullet
6025
@item float32x4_t vmulq_lane_f32 (float32x4_t, float32x2_t, const int)
6026
@*@emph{Form of expected instruction(s):} @code{vmul.f32 @var{q0}, @var{q0}, @var{d0}[@var{0}]}
6027
@end itemize
6028
 
6029
 
6030
@itemize @bullet
6031
@item uint32x4_t vmulq_lane_u32 (uint32x4_t, uint32x2_t, const int)
6032
@*@emph{Form of expected instruction(s):} @code{vmul.i32 @var{q0}, @var{q0}, @var{d0}[@var{0}]}
6033
@end itemize
6034
 
6035
 
6036
@itemize @bullet
6037
@item uint16x8_t vmulq_lane_u16 (uint16x8_t, uint16x4_t, const int)
6038
@*@emph{Form of expected instruction(s):} @code{vmul.i16 @var{q0}, @var{q0}, @var{d0}[@var{0}]}
6039
@end itemize
6040
 
6041
 
6042
@itemize @bullet
6043
@item int32x4_t vmulq_lane_s32 (int32x4_t, int32x2_t, const int)
6044
@*@emph{Form of expected instruction(s):} @code{vmul.i32 @var{q0}, @var{q0}, @var{d0}[@var{0}]}
6045
@end itemize
6046
 
6047
 
6048
@itemize @bullet
6049
@item int16x8_t vmulq_lane_s16 (int16x8_t, int16x4_t, const int)
6050
@*@emph{Form of expected instruction(s):} @code{vmul.i16 @var{q0}, @var{q0}, @var{d0}[@var{0}]}
6051
@end itemize
6052
 
6053
 
6054
 
6055
 
6056
@subsubsection Long multiply, lane
6057
 
6058
@itemize @bullet
6059
@item uint64x2_t vmull_lane_u32 (uint32x2_t, uint32x2_t, const int)
6060
@*@emph{Form of expected instruction(s):} @code{vmull.u32 @var{q0}, @var{d0}, @var{d0}[@var{0}]}
6061
@end itemize
6062
 
6063
 
6064
@itemize @bullet
6065
@item uint32x4_t vmull_lane_u16 (uint16x4_t, uint16x4_t, const int)
6066
@*@emph{Form of expected instruction(s):} @code{vmull.u16 @var{q0}, @var{d0}, @var{d0}[@var{0}]}
6067
@end itemize
6068
 
6069
 
6070
@itemize @bullet
6071
@item int64x2_t vmull_lane_s32 (int32x2_t, int32x2_t, const int)
6072
@*@emph{Form of expected instruction(s):} @code{vmull.s32 @var{q0}, @var{d0}, @var{d0}[@var{0}]}
6073
@end itemize
6074
 
6075
 
6076
@itemize @bullet
6077
@item int32x4_t vmull_lane_s16 (int16x4_t, int16x4_t, const int)
6078
@*@emph{Form of expected instruction(s):} @code{vmull.s16 @var{q0}, @var{d0}, @var{d0}[@var{0}]}
6079
@end itemize
6080
 
6081
 
6082
 
6083
 
6084
@subsubsection Saturating doubling long multiply, lane
6085
 
6086
@itemize @bullet
6087
@item int64x2_t vqdmull_lane_s32 (int32x2_t, int32x2_t, const int)
6088
@*@emph{Form of expected instruction(s):} @code{vqdmull.s32 @var{q0}, @var{d0}, @var{d0}[@var{0}]}
6089
@end itemize
6090
 
6091
 
6092
@itemize @bullet
6093
@item int32x4_t vqdmull_lane_s16 (int16x4_t, int16x4_t, const int)
6094
@*@emph{Form of expected instruction(s):} @code{vqdmull.s16 @var{q0}, @var{d0}, @var{d0}[@var{0}]}
6095
@end itemize
6096
 
6097
 
6098
 
6099
 
6100
@subsubsection Saturating doubling multiply high, lane
6101
 
6102
@itemize @bullet
6103
@item int32x4_t vqdmulhq_lane_s32 (int32x4_t, int32x2_t, const int)
6104
@*@emph{Form of expected instruction(s):} @code{vqdmulh.s32 @var{q0}, @var{q0}, @var{d0}[@var{0}]}
6105
@end itemize
6106
 
6107
 
6108
@itemize @bullet
6109
@item int16x8_t vqdmulhq_lane_s16 (int16x8_t, int16x4_t, const int)
6110
@*@emph{Form of expected instruction(s):} @code{vqdmulh.s16 @var{q0}, @var{q0}, @var{d0}[@var{0}]}
6111
@end itemize
6112
 
6113
 
6114
@itemize @bullet
6115
@item int32x2_t vqdmulh_lane_s32 (int32x2_t, int32x2_t, const int)
6116
@*@emph{Form of expected instruction(s):} @code{vqdmulh.s32 @var{d0}, @var{d0}, @var{d0}[@var{0}]}
6117
@end itemize
6118
 
6119
 
6120
@itemize @bullet
6121
@item int16x4_t vqdmulh_lane_s16 (int16x4_t, int16x4_t, const int)
6122
@*@emph{Form of expected instruction(s):} @code{vqdmulh.s16 @var{d0}, @var{d0}, @var{d0}[@var{0}]}
6123
@end itemize
6124
 
6125
 
6126
@itemize @bullet
6127
@item int32x4_t vqrdmulhq_lane_s32 (int32x4_t, int32x2_t, const int)
6128
@*@emph{Form of expected instruction(s):} @code{vqrdmulh.s32 @var{q0}, @var{q0}, @var{d0}[@var{0}]}
6129
@end itemize
6130
 
6131
 
6132
@itemize @bullet
6133
@item int16x8_t vqrdmulhq_lane_s16 (int16x8_t, int16x4_t, const int)
6134
@*@emph{Form of expected instruction(s):} @code{vqrdmulh.s16 @var{q0}, @var{q0}, @var{d0}[@var{0}]}
6135
@end itemize
6136
 
6137
 
6138
@itemize @bullet
6139
@item int32x2_t vqrdmulh_lane_s32 (int32x2_t, int32x2_t, const int)
6140
@*@emph{Form of expected instruction(s):} @code{vqrdmulh.s32 @var{d0}, @var{d0}, @var{d0}[@var{0}]}
6141
@end itemize
6142
 
6143
 
6144
@itemize @bullet
6145
@item int16x4_t vqrdmulh_lane_s16 (int16x4_t, int16x4_t, const int)
6146
@*@emph{Form of expected instruction(s):} @code{vqrdmulh.s16 @var{d0}, @var{d0}, @var{d0}[@var{0}]}
6147
@end itemize
6148
 
6149
 
6150
 
6151
 
6152
@subsubsection Multiply-accumulate, lane
6153
 
6154
@itemize @bullet
6155
@item float32x2_t vmla_lane_f32 (float32x2_t, float32x2_t, float32x2_t, const int)
6156
@*@emph{Form of expected instruction(s):} @code{vmla.f32 @var{d0}, @var{d0}, @var{d0}[@var{0}]}
6157
@end itemize
6158
 
6159
 
6160
@itemize @bullet
6161
@item uint32x2_t vmla_lane_u32 (uint32x2_t, uint32x2_t, uint32x2_t, const int)
6162
@*@emph{Form of expected instruction(s):} @code{vmla.i32 @var{d0}, @var{d0}, @var{d0}[@var{0}]}
6163
@end itemize
6164
 
6165
 
6166
@itemize @bullet
6167
@item uint16x4_t vmla_lane_u16 (uint16x4_t, uint16x4_t, uint16x4_t, const int)
6168
@*@emph{Form of expected instruction(s):} @code{vmla.i16 @var{d0}, @var{d0}, @var{d0}[@var{0}]}
6169
@end itemize
6170
 
6171
 
6172
@itemize @bullet
6173
@item int32x2_t vmla_lane_s32 (int32x2_t, int32x2_t, int32x2_t, const int)
6174
@*@emph{Form of expected instruction(s):} @code{vmla.i32 @var{d0}, @var{d0}, @var{d0}[@var{0}]}
6175
@end itemize
6176
 
6177
 
6178
@itemize @bullet
6179
@item int16x4_t vmla_lane_s16 (int16x4_t, int16x4_t, int16x4_t, const int)
6180
@*@emph{Form of expected instruction(s):} @code{vmla.i16 @var{d0}, @var{d0}, @var{d0}[@var{0}]}
6181
@end itemize
6182
 
6183
 
6184
@itemize @bullet
6185
@item float32x4_t vmlaq_lane_f32 (float32x4_t, float32x4_t, float32x2_t, const int)
6186
@*@emph{Form of expected instruction(s):} @code{vmla.f32 @var{q0}, @var{q0}, @var{d0}[@var{0}]}
6187
@end itemize
6188
 
6189
 
6190
@itemize @bullet
6191
@item uint32x4_t vmlaq_lane_u32 (uint32x4_t, uint32x4_t, uint32x2_t, const int)
6192
@*@emph{Form of expected instruction(s):} @code{vmla.i32 @var{q0}, @var{q0}, @var{d0}[@var{0}]}
6193
@end itemize
6194
 
6195
 
6196
@itemize @bullet
6197
@item uint16x8_t vmlaq_lane_u16 (uint16x8_t, uint16x8_t, uint16x4_t, const int)
6198
@*@emph{Form of expected instruction(s):} @code{vmla.i16 @var{q0}, @var{q0}, @var{d0}[@var{0}]}
6199
@end itemize
6200
 
6201
 
6202
@itemize @bullet
6203
@item int32x4_t vmlaq_lane_s32 (int32x4_t, int32x4_t, int32x2_t, const int)
6204
@*@emph{Form of expected instruction(s):} @code{vmla.i32 @var{q0}, @var{q0}, @var{d0}[@var{0}]}
6205
@end itemize
6206
 
6207
 
6208
@itemize @bullet
6209
@item int16x8_t vmlaq_lane_s16 (int16x8_t, int16x8_t, int16x4_t, const int)
6210
@*@emph{Form of expected instruction(s):} @code{vmla.i16 @var{q0}, @var{q0}, @var{d0}[@var{0}]}
6211
@end itemize
6212
 
6213
 
6214
@itemize @bullet
6215
@item uint64x2_t vmlal_lane_u32 (uint64x2_t, uint32x2_t, uint32x2_t, const int)
6216
@*@emph{Form of expected instruction(s):} @code{vmlal.u32 @var{q0}, @var{d0}, @var{d0}[@var{0}]}
6217
@end itemize
6218
 
6219
 
6220
@itemize @bullet
6221
@item uint32x4_t vmlal_lane_u16 (uint32x4_t, uint16x4_t, uint16x4_t, const int)
6222
@*@emph{Form of expected instruction(s):} @code{vmlal.u16 @var{q0}, @var{d0}, @var{d0}[@var{0}]}
6223
@end itemize
6224
 
6225
 
6226
@itemize @bullet
6227
@item int64x2_t vmlal_lane_s32 (int64x2_t, int32x2_t, int32x2_t, const int)
6228
@*@emph{Form of expected instruction(s):} @code{vmlal.s32 @var{q0}, @var{d0}, @var{d0}[@var{0}]}
6229
@end itemize
6230
 
6231
 
6232
@itemize @bullet
6233
@item int32x4_t vmlal_lane_s16 (int32x4_t, int16x4_t, int16x4_t, const int)
6234
@*@emph{Form of expected instruction(s):} @code{vmlal.s16 @var{q0}, @var{d0}, @var{d0}[@var{0}]}
6235
@end itemize
6236
 
6237
 
6238
@itemize @bullet
6239
@item int64x2_t vqdmlal_lane_s32 (int64x2_t, int32x2_t, int32x2_t, const int)
6240
@*@emph{Form of expected instruction(s):} @code{vqdmlal.s32 @var{q0}, @var{d0}, @var{d0}[@var{0}]}
6241
@end itemize
6242
 
6243
 
6244
@itemize @bullet
6245
@item int32x4_t vqdmlal_lane_s16 (int32x4_t, int16x4_t, int16x4_t, const int)
6246
@*@emph{Form of expected instruction(s):} @code{vqdmlal.s16 @var{q0}, @var{d0}, @var{d0}[@var{0}]}
6247
@end itemize
6248
 
6249
 
6250
 
6251
 
6252
@subsubsection Multiply-subtract, lane
6253
 
6254
@itemize @bullet
6255
@item float32x2_t vmls_lane_f32 (float32x2_t, float32x2_t, float32x2_t, const int)
6256
@*@emph{Form of expected instruction(s):} @code{vmls.f32 @var{d0}, @var{d0}, @var{d0}[@var{0}]}
6257
@end itemize
6258
 
6259
 
6260
@itemize @bullet
6261
@item uint32x2_t vmls_lane_u32 (uint32x2_t, uint32x2_t, uint32x2_t, const int)
6262
@*@emph{Form of expected instruction(s):} @code{vmls.i32 @var{d0}, @var{d0}, @var{d0}[@var{0}]}
6263
@end itemize
6264
 
6265
 
6266
@itemize @bullet
6267
@item uint16x4_t vmls_lane_u16 (uint16x4_t, uint16x4_t, uint16x4_t, const int)
6268
@*@emph{Form of expected instruction(s):} @code{vmls.i16 @var{d0}, @var{d0}, @var{d0}[@var{0}]}
6269
@end itemize
6270
 
6271
 
6272
@itemize @bullet
6273
@item int32x2_t vmls_lane_s32 (int32x2_t, int32x2_t, int32x2_t, const int)
6274
@*@emph{Form of expected instruction(s):} @code{vmls.i32 @var{d0}, @var{d0}, @var{d0}[@var{0}]}
6275
@end itemize
6276
 
6277
 
6278
@itemize @bullet
6279
@item int16x4_t vmls_lane_s16 (int16x4_t, int16x4_t, int16x4_t, const int)
6280
@*@emph{Form of expected instruction(s):} @code{vmls.i16 @var{d0}, @var{d0}, @var{d0}[@var{0}]}
6281
@end itemize
6282
 
6283
 
6284
@itemize @bullet
6285
@item float32x4_t vmlsq_lane_f32 (float32x4_t, float32x4_t, float32x2_t, const int)
6286
@*@emph{Form of expected instruction(s):} @code{vmls.f32 @var{q0}, @var{q0}, @var{d0}[@var{0}]}
6287
@end itemize
6288
 
6289
 
6290
@itemize @bullet
6291
@item uint32x4_t vmlsq_lane_u32 (uint32x4_t, uint32x4_t, uint32x2_t, const int)
6292
@*@emph{Form of expected instruction(s):} @code{vmls.i32 @var{q0}, @var{q0}, @var{d0}[@var{0}]}
6293
@end itemize
6294
 
6295
 
6296
@itemize @bullet
6297
@item uint16x8_t vmlsq_lane_u16 (uint16x8_t, uint16x8_t, uint16x4_t, const int)
6298
@*@emph{Form of expected instruction(s):} @code{vmls.i16 @var{q0}, @var{q0}, @var{d0}[@var{0}]}
6299
@end itemize
6300
 
6301
 
6302
@itemize @bullet
6303
@item int32x4_t vmlsq_lane_s32 (int32x4_t, int32x4_t, int32x2_t, const int)
6304
@*@emph{Form of expected instruction(s):} @code{vmls.i32 @var{q0}, @var{q0}, @var{d0}[@var{0}]}
6305
@end itemize
6306
 
6307
 
6308
@itemize @bullet
6309
@item int16x8_t vmlsq_lane_s16 (int16x8_t, int16x8_t, int16x4_t, const int)
6310
@*@emph{Form of expected instruction(s):} @code{vmls.i16 @var{q0}, @var{q0}, @var{d0}[@var{0}]}
6311
@end itemize
6312
 
6313
 
6314
@itemize @bullet
6315
@item uint64x2_t vmlsl_lane_u32 (uint64x2_t, uint32x2_t, uint32x2_t, const int)
6316
@*@emph{Form of expected instruction(s):} @code{vmlsl.u32 @var{q0}, @var{d0}, @var{d0}[@var{0}]}
6317
@end itemize
6318
 
6319
 
6320
@itemize @bullet
6321
@item uint32x4_t vmlsl_lane_u16 (uint32x4_t, uint16x4_t, uint16x4_t, const int)
6322
@*@emph{Form of expected instruction(s):} @code{vmlsl.u16 @var{q0}, @var{d0}, @var{d0}[@var{0}]}
6323
@end itemize
6324
 
6325
 
6326
@itemize @bullet
6327
@item int64x2_t vmlsl_lane_s32 (int64x2_t, int32x2_t, int32x2_t, const int)
6328
@*@emph{Form of expected instruction(s):} @code{vmlsl.s32 @var{q0}, @var{d0}, @var{d0}[@var{0}]}
6329
@end itemize
6330
 
6331
 
6332
@itemize @bullet
6333
@item int32x4_t vmlsl_lane_s16 (int32x4_t, int16x4_t, int16x4_t, const int)
6334
@*@emph{Form of expected instruction(s):} @code{vmlsl.s16 @var{q0}, @var{d0}, @var{d0}[@var{0}]}
6335
@end itemize
6336
 
6337
 
6338
@itemize @bullet
6339
@item int64x2_t vqdmlsl_lane_s32 (int64x2_t, int32x2_t, int32x2_t, const int)
6340
@*@emph{Form of expected instruction(s):} @code{vqdmlsl.s32 @var{q0}, @var{d0}, @var{d0}[@var{0}]}
6341
@end itemize
6342
 
6343
 
6344
@itemize @bullet
6345
@item int32x4_t vqdmlsl_lane_s16 (int32x4_t, int16x4_t, int16x4_t, const int)
6346
@*@emph{Form of expected instruction(s):} @code{vqdmlsl.s16 @var{q0}, @var{d0}, @var{d0}[@var{0}]}
6347
@end itemize
6348
 
6349
 
6350
 
6351
 
6352
@subsubsection Vector multiply by scalar
6353
 
6354
@itemize @bullet
6355
@item float32x2_t vmul_n_f32 (float32x2_t, float32_t)
6356
@*@emph{Form of expected instruction(s):} @code{vmul.f32 @var{d0}, @var{d0}, @var{d0}[@var{0}]}
6357
@end itemize
6358
 
6359
 
6360
@itemize @bullet
6361
@item uint32x2_t vmul_n_u32 (uint32x2_t, uint32_t)
6362
@*@emph{Form of expected instruction(s):} @code{vmul.i32 @var{d0}, @var{d0}, @var{d0}[@var{0}]}
6363
@end itemize
6364
 
6365
 
6366
@itemize @bullet
6367
@item uint16x4_t vmul_n_u16 (uint16x4_t, uint16_t)
6368
@*@emph{Form of expected instruction(s):} @code{vmul.i16 @var{d0}, @var{d0}, @var{d0}[@var{0}]}
6369
@end itemize
6370
 
6371
 
6372
@itemize @bullet
6373
@item int32x2_t vmul_n_s32 (int32x2_t, int32_t)
6374
@*@emph{Form of expected instruction(s):} @code{vmul.i32 @var{d0}, @var{d0}, @var{d0}[@var{0}]}
6375
@end itemize
6376
 
6377
 
6378
@itemize @bullet
6379
@item int16x4_t vmul_n_s16 (int16x4_t, int16_t)
6380
@*@emph{Form of expected instruction(s):} @code{vmul.i16 @var{d0}, @var{d0}, @var{d0}[@var{0}]}
6381
@end itemize
6382
 
6383
 
6384
@itemize @bullet
6385
@item float32x4_t vmulq_n_f32 (float32x4_t, float32_t)
6386
@*@emph{Form of expected instruction(s):} @code{vmul.f32 @var{q0}, @var{q0}, @var{d0}[@var{0}]}
6387
@end itemize
6388
 
6389
 
6390
@itemize @bullet
6391
@item uint32x4_t vmulq_n_u32 (uint32x4_t, uint32_t)
6392
@*@emph{Form of expected instruction(s):} @code{vmul.i32 @var{q0}, @var{q0}, @var{d0}[@var{0}]}
6393
@end itemize
6394
 
6395
 
6396
@itemize @bullet
6397
@item uint16x8_t vmulq_n_u16 (uint16x8_t, uint16_t)
6398
@*@emph{Form of expected instruction(s):} @code{vmul.i16 @var{q0}, @var{q0}, @var{d0}[@var{0}]}
6399
@end itemize
6400
 
6401
 
6402
@itemize @bullet
6403
@item int32x4_t vmulq_n_s32 (int32x4_t, int32_t)
6404
@*@emph{Form of expected instruction(s):} @code{vmul.i32 @var{q0}, @var{q0}, @var{d0}[@var{0}]}
6405
@end itemize
6406
 
6407
 
6408
@itemize @bullet
6409
@item int16x8_t vmulq_n_s16 (int16x8_t, int16_t)
6410
@*@emph{Form of expected instruction(s):} @code{vmul.i16 @var{q0}, @var{q0}, @var{d0}[@var{0}]}
6411
@end itemize
6412
 
6413
 
6414
 
6415
 
6416
@subsubsection Vector long multiply by scalar
6417
 
6418
@itemize @bullet
6419
@item uint64x2_t vmull_n_u32 (uint32x2_t, uint32_t)
6420
@*@emph{Form of expected instruction(s):} @code{vmull.u32 @var{q0}, @var{d0}, @var{d0}[@var{0}]}
6421
@end itemize
6422
 
6423
 
6424
@itemize @bullet
6425
@item uint32x4_t vmull_n_u16 (uint16x4_t, uint16_t)
6426
@*@emph{Form of expected instruction(s):} @code{vmull.u16 @var{q0}, @var{d0}, @var{d0}[@var{0}]}
6427
@end itemize
6428
 
6429
 
6430
@itemize @bullet
6431
@item int64x2_t vmull_n_s32 (int32x2_t, int32_t)
6432
@*@emph{Form of expected instruction(s):} @code{vmull.s32 @var{q0}, @var{d0}, @var{d0}[@var{0}]}
6433
@end itemize
6434
 
6435
 
6436
@itemize @bullet
6437
@item int32x4_t vmull_n_s16 (int16x4_t, int16_t)
6438
@*@emph{Form of expected instruction(s):} @code{vmull.s16 @var{q0}, @var{d0}, @var{d0}[@var{0}]}
6439
@end itemize
6440
 
6441
 
6442
 
6443
 
6444
@subsubsection Vector saturating doubling long multiply by scalar
6445
 
6446
@itemize @bullet
6447
@item int64x2_t vqdmull_n_s32 (int32x2_t, int32_t)
6448
@*@emph{Form of expected instruction(s):} @code{vqdmull.s32 @var{q0}, @var{d0}, @var{d0}[@var{0}]}
6449
@end itemize
6450
 
6451
 
6452
@itemize @bullet
6453
@item int32x4_t vqdmull_n_s16 (int16x4_t, int16_t)
6454
@*@emph{Form of expected instruction(s):} @code{vqdmull.s16 @var{q0}, @var{d0}, @var{d0}[@var{0}]}
6455
@end itemize
6456
 
6457
 
6458
 
6459
 
6460
@subsubsection Vector saturating doubling multiply high by scalar
6461
 
6462
@itemize @bullet
6463
@item int32x4_t vqdmulhq_n_s32 (int32x4_t, int32_t)
6464
@*@emph{Form of expected instruction(s):} @code{vqdmulh.s32 @var{q0}, @var{q0}, @var{d0}[@var{0}]}
6465
@end itemize
6466
 
6467
 
6468
@itemize @bullet
6469
@item int16x8_t vqdmulhq_n_s16 (int16x8_t, int16_t)
6470
@*@emph{Form of expected instruction(s):} @code{vqdmulh.s16 @var{q0}, @var{q0}, @var{d0}[@var{0}]}
6471
@end itemize
6472
 
6473
 
6474
@itemize @bullet
6475
@item int32x2_t vqdmulh_n_s32 (int32x2_t, int32_t)
6476
@*@emph{Form of expected instruction(s):} @code{vqdmulh.s32 @var{d0}, @var{d0}, @var{d0}[@var{0}]}
6477
@end itemize
6478
 
6479
 
6480
@itemize @bullet
6481
@item int16x4_t vqdmulh_n_s16 (int16x4_t, int16_t)
6482
@*@emph{Form of expected instruction(s):} @code{vqdmulh.s16 @var{d0}, @var{d0}, @var{d0}[@var{0}]}
6483
@end itemize
6484
 
6485
 
6486
@itemize @bullet
6487
@item int32x4_t vqrdmulhq_n_s32 (int32x4_t, int32_t)
6488
@*@emph{Form of expected instruction(s):} @code{vqrdmulh.s32 @var{q0}, @var{q0}, @var{d0}[@var{0}]}
6489
@end itemize
6490
 
6491
 
6492
@itemize @bullet
6493
@item int16x8_t vqrdmulhq_n_s16 (int16x8_t, int16_t)
6494
@*@emph{Form of expected instruction(s):} @code{vqrdmulh.s16 @var{q0}, @var{q0}, @var{d0}[@var{0}]}
6495
@end itemize
6496
 
6497
 
6498
@itemize @bullet
6499
@item int32x2_t vqrdmulh_n_s32 (int32x2_t, int32_t)
6500
@*@emph{Form of expected instruction(s):} @code{vqrdmulh.s32 @var{d0}, @var{d0}, @var{d0}[@var{0}]}
6501
@end itemize
6502
 
6503
 
6504
@itemize @bullet
6505
@item int16x4_t vqrdmulh_n_s16 (int16x4_t, int16_t)
6506
@*@emph{Form of expected instruction(s):} @code{vqrdmulh.s16 @var{d0}, @var{d0}, @var{d0}[@var{0}]}
6507
@end itemize
6508
 
6509
 
6510
 
6511
 
6512
@subsubsection Vector multiply-accumulate by scalar
6513
 
6514
@itemize @bullet
6515
@item float32x2_t vmla_n_f32 (float32x2_t, float32x2_t, float32_t)
6516
@*@emph{Form of expected instruction(s):} @code{vmla.f32 @var{d0}, @var{d0}, @var{d0}[@var{0}]}
6517
@end itemize
6518
 
6519
 
6520
@itemize @bullet
6521
@item uint32x2_t vmla_n_u32 (uint32x2_t, uint32x2_t, uint32_t)
6522
@*@emph{Form of expected instruction(s):} @code{vmla.i32 @var{d0}, @var{d0}, @var{d0}[@var{0}]}
6523
@end itemize
6524
 
6525
 
6526
@itemize @bullet
6527
@item uint16x4_t vmla_n_u16 (uint16x4_t, uint16x4_t, uint16_t)
6528
@*@emph{Form of expected instruction(s):} @code{vmla.i16 @var{d0}, @var{d0}, @var{d0}[@var{0}]}
6529
@end itemize
6530
 
6531
 
6532
@itemize @bullet
6533
@item int32x2_t vmla_n_s32 (int32x2_t, int32x2_t, int32_t)
6534
@*@emph{Form of expected instruction(s):} @code{vmla.i32 @var{d0}, @var{d0}, @var{d0}[@var{0}]}
6535
@end itemize
6536
 
6537
 
6538
@itemize @bullet
6539
@item int16x4_t vmla_n_s16 (int16x4_t, int16x4_t, int16_t)
6540
@*@emph{Form of expected instruction(s):} @code{vmla.i16 @var{d0}, @var{d0}, @var{d0}[@var{0}]}
6541
@end itemize
6542
 
6543
 
6544
@itemize @bullet
6545
@item float32x4_t vmlaq_n_f32 (float32x4_t, float32x4_t, float32_t)
6546
@*@emph{Form of expected instruction(s):} @code{vmla.f32 @var{q0}, @var{q0}, @var{d0}[@var{0}]}
6547
@end itemize
6548
 
6549
 
6550
@itemize @bullet
6551
@item uint32x4_t vmlaq_n_u32 (uint32x4_t, uint32x4_t, uint32_t)
6552
@*@emph{Form of expected instruction(s):} @code{vmla.i32 @var{q0}, @var{q0}, @var{d0}[@var{0}]}
6553
@end itemize
6554
 
6555
 
6556
@itemize @bullet
6557
@item uint16x8_t vmlaq_n_u16 (uint16x8_t, uint16x8_t, uint16_t)
6558
@*@emph{Form of expected instruction(s):} @code{vmla.i16 @var{q0}, @var{q0}, @var{d0}[@var{0}]}
6559
@end itemize
6560
 
6561
 
6562
@itemize @bullet
6563
@item int32x4_t vmlaq_n_s32 (int32x4_t, int32x4_t, int32_t)
6564
@*@emph{Form of expected instruction(s):} @code{vmla.i32 @var{q0}, @var{q0}, @var{d0}[@var{0}]}
6565
@end itemize
6566
 
6567
 
6568
@itemize @bullet
6569
@item int16x8_t vmlaq_n_s16 (int16x8_t, int16x8_t, int16_t)
6570
@*@emph{Form of expected instruction(s):} @code{vmla.i16 @var{q0}, @var{q0}, @var{d0}[@var{0}]}
6571
@end itemize
6572
 
6573
 
6574
@itemize @bullet
6575
@item uint64x2_t vmlal_n_u32 (uint64x2_t, uint32x2_t, uint32_t)
6576
@*@emph{Form of expected instruction(s):} @code{vmlal.u32 @var{q0}, @var{d0}, @var{d0}[@var{0}]}
6577
@end itemize
6578
 
6579
 
6580
@itemize @bullet
6581
@item uint32x4_t vmlal_n_u16 (uint32x4_t, uint16x4_t, uint16_t)
6582
@*@emph{Form of expected instruction(s):} @code{vmlal.u16 @var{q0}, @var{d0}, @var{d0}[@var{0}]}
6583
@end itemize
6584
 
6585
 
6586
@itemize @bullet
6587
@item int64x2_t vmlal_n_s32 (int64x2_t, int32x2_t, int32_t)
6588
@*@emph{Form of expected instruction(s):} @code{vmlal.s32 @var{q0}, @var{d0}, @var{d0}[@var{0}]}
6589
@end itemize
6590
 
6591
 
6592
@itemize @bullet
6593
@item int32x4_t vmlal_n_s16 (int32x4_t, int16x4_t, int16_t)
6594
@*@emph{Form of expected instruction(s):} @code{vmlal.s16 @var{q0}, @var{d0}, @var{d0}[@var{0}]}
6595
@end itemize
6596
 
6597
 
6598
@itemize @bullet
6599
@item int64x2_t vqdmlal_n_s32 (int64x2_t, int32x2_t, int32_t)
6600
@*@emph{Form of expected instruction(s):} @code{vqdmlal.s32 @var{q0}, @var{d0}, @var{d0}[@var{0}]}
6601
@end itemize
6602
 
6603
 
6604
@itemize @bullet
6605
@item int32x4_t vqdmlal_n_s16 (int32x4_t, int16x4_t, int16_t)
6606
@*@emph{Form of expected instruction(s):} @code{vqdmlal.s16 @var{q0}, @var{d0}, @var{d0}[@var{0}]}
6607
@end itemize
6608
 
6609
 
6610
 
6611
 
6612
@subsubsection Vector multiply-subtract by scalar
6613
 
6614
@itemize @bullet
6615
@item float32x2_t vmls_n_f32 (float32x2_t, float32x2_t, float32_t)
6616
@*@emph{Form of expected instruction(s):} @code{vmls.f32 @var{d0}, @var{d0}, @var{d0}[@var{0}]}
6617
@end itemize
6618
 
6619
 
6620
@itemize @bullet
6621
@item uint32x2_t vmls_n_u32 (uint32x2_t, uint32x2_t, uint32_t)
6622
@*@emph{Form of expected instruction(s):} @code{vmls.i32 @var{d0}, @var{d0}, @var{d0}[@var{0}]}
6623
@end itemize
6624
 
6625
 
6626
@itemize @bullet
6627
@item uint16x4_t vmls_n_u16 (uint16x4_t, uint16x4_t, uint16_t)
6628
@*@emph{Form of expected instruction(s):} @code{vmls.i16 @var{d0}, @var{d0}, @var{d0}[@var{0}]}
6629
@end itemize
6630
 
6631
 
6632
@itemize @bullet
6633
@item int32x2_t vmls_n_s32 (int32x2_t, int32x2_t, int32_t)
6634
@*@emph{Form of expected instruction(s):} @code{vmls.i32 @var{d0}, @var{d0}, @var{d0}[@var{0}]}
6635
@end itemize
6636
 
6637
 
6638
@itemize @bullet
6639
@item int16x4_t vmls_n_s16 (int16x4_t, int16x4_t, int16_t)
6640
@*@emph{Form of expected instruction(s):} @code{vmls.i16 @var{d0}, @var{d0}, @var{d0}[@var{0}]}
6641
@end itemize
6642
 
6643
 
6644
@itemize @bullet
6645
@item float32x4_t vmlsq_n_f32 (float32x4_t, float32x4_t, float32_t)
6646
@*@emph{Form of expected instruction(s):} @code{vmls.f32 @var{q0}, @var{q0}, @var{d0}[@var{0}]}
6647
@end itemize
6648
 
6649
 
6650
@itemize @bullet
6651
@item uint32x4_t vmlsq_n_u32 (uint32x4_t, uint32x4_t, uint32_t)
6652
@*@emph{Form of expected instruction(s):} @code{vmls.i32 @var{q0}, @var{q0}, @var{d0}[@var{0}]}
6653
@end itemize
6654
 
6655
 
6656
@itemize @bullet
6657
@item uint16x8_t vmlsq_n_u16 (uint16x8_t, uint16x8_t, uint16_t)
6658
@*@emph{Form of expected instruction(s):} @code{vmls.i16 @var{q0}, @var{q0}, @var{d0}[@var{0}]}
6659
@end itemize
6660
 
6661
 
6662
@itemize @bullet
6663
@item int32x4_t vmlsq_n_s32 (int32x4_t, int32x4_t, int32_t)
6664
@*@emph{Form of expected instruction(s):} @code{vmls.i32 @var{q0}, @var{q0}, @var{d0}[@var{0}]}
6665
@end itemize
6666
 
6667
 
6668
@itemize @bullet
6669
@item int16x8_t vmlsq_n_s16 (int16x8_t, int16x8_t, int16_t)
6670
@*@emph{Form of expected instruction(s):} @code{vmls.i16 @var{q0}, @var{q0}, @var{d0}[@var{0}]}
6671
@end itemize
6672
 
6673
 
6674
@itemize @bullet
6675
@item uint64x2_t vmlsl_n_u32 (uint64x2_t, uint32x2_t, uint32_t)
6676
@*@emph{Form of expected instruction(s):} @code{vmlsl.u32 @var{q0}, @var{d0}, @var{d0}[@var{0}]}
6677
@end itemize
6678
 
6679
 
6680
@itemize @bullet
6681
@item uint32x4_t vmlsl_n_u16 (uint32x4_t, uint16x4_t, uint16_t)
6682
@*@emph{Form of expected instruction(s):} @code{vmlsl.u16 @var{q0}, @var{d0}, @var{d0}[@var{0}]}
6683
@end itemize
6684
 
6685
 
6686
@itemize @bullet
6687
@item int64x2_t vmlsl_n_s32 (int64x2_t, int32x2_t, int32_t)
6688
@*@emph{Form of expected instruction(s):} @code{vmlsl.s32 @var{q0}, @var{d0}, @var{d0}[@var{0}]}
6689
@end itemize
6690
 
6691
 
6692
@itemize @bullet
6693
@item int32x4_t vmlsl_n_s16 (int32x4_t, int16x4_t, int16_t)
6694
@*@emph{Form of expected instruction(s):} @code{vmlsl.s16 @var{q0}, @var{d0}, @var{d0}[@var{0}]}
6695
@end itemize
6696
 
6697
 
6698
@itemize @bullet
6699
@item int64x2_t vqdmlsl_n_s32 (int64x2_t, int32x2_t, int32_t)
6700
@*@emph{Form of expected instruction(s):} @code{vqdmlsl.s32 @var{q0}, @var{d0}, @var{d0}[@var{0}]}
6701
@end itemize
6702
 
6703
 
6704
@itemize @bullet
6705
@item int32x4_t vqdmlsl_n_s16 (int32x4_t, int16x4_t, int16_t)
6706
@*@emph{Form of expected instruction(s):} @code{vqdmlsl.s16 @var{q0}, @var{d0}, @var{d0}[@var{0}]}
6707
@end itemize
6708
 
6709
 
6710
 
6711
 
6712
@subsubsection Vector extract
6713
 
6714
@itemize @bullet
6715
@item uint32x2_t vext_u32 (uint32x2_t, uint32x2_t, const int)
6716
@*@emph{Form of expected instruction(s):} @code{vext.32 @var{d0}, @var{d0}, @var{d0}, #@var{0}}
6717
@end itemize
6718
 
6719
 
6720
@itemize @bullet
6721
@item uint16x4_t vext_u16 (uint16x4_t, uint16x4_t, const int)
6722
@*@emph{Form of expected instruction(s):} @code{vext.16 @var{d0}, @var{d0}, @var{d0}, #@var{0}}
6723
@end itemize
6724
 
6725
 
6726
@itemize @bullet
6727
@item uint8x8_t vext_u8 (uint8x8_t, uint8x8_t, const int)
6728
@*@emph{Form of expected instruction(s):} @code{vext.8 @var{d0}, @var{d0}, @var{d0}, #@var{0}}
6729
@end itemize
6730
 
6731
 
6732
@itemize @bullet
6733
@item int32x2_t vext_s32 (int32x2_t, int32x2_t, const int)
6734
@*@emph{Form of expected instruction(s):} @code{vext.32 @var{d0}, @var{d0}, @var{d0}, #@var{0}}
6735
@end itemize
6736
 
6737
 
6738
@itemize @bullet
6739
@item int16x4_t vext_s16 (int16x4_t, int16x4_t, const int)
6740
@*@emph{Form of expected instruction(s):} @code{vext.16 @var{d0}, @var{d0}, @var{d0}, #@var{0}}
6741
@end itemize
6742
 
6743
 
6744
@itemize @bullet
6745
@item int8x8_t vext_s8 (int8x8_t, int8x8_t, const int)
6746
@*@emph{Form of expected instruction(s):} @code{vext.8 @var{d0}, @var{d0}, @var{d0}, #@var{0}}
6747
@end itemize
6748
 
6749
 
6750
@itemize @bullet
6751
@item uint64x1_t vext_u64 (uint64x1_t, uint64x1_t, const int)
6752
@*@emph{Form of expected instruction(s):} @code{vext.64 @var{d0}, @var{d0}, @var{d0}, #@var{0}}
6753
@end itemize
6754
 
6755
 
6756
@itemize @bullet
6757
@item int64x1_t vext_s64 (int64x1_t, int64x1_t, const int)
6758
@*@emph{Form of expected instruction(s):} @code{vext.64 @var{d0}, @var{d0}, @var{d0}, #@var{0}}
6759
@end itemize
6760
 
6761
 
6762
@itemize @bullet
6763
@item float32x2_t vext_f32 (float32x2_t, float32x2_t, const int)
6764
@*@emph{Form of expected instruction(s):} @code{vext.32 @var{d0}, @var{d0}, @var{d0}, #@var{0}}
6765
@end itemize
6766
 
6767
 
6768
@itemize @bullet
6769
@item poly16x4_t vext_p16 (poly16x4_t, poly16x4_t, const int)
6770
@*@emph{Form of expected instruction(s):} @code{vext.16 @var{d0}, @var{d0}, @var{d0}, #@var{0}}
6771
@end itemize
6772
 
6773
 
6774
@itemize @bullet
6775
@item poly8x8_t vext_p8 (poly8x8_t, poly8x8_t, const int)
6776
@*@emph{Form of expected instruction(s):} @code{vext.8 @var{d0}, @var{d0}, @var{d0}, #@var{0}}
6777
@end itemize
6778
 
6779
 
6780
@itemize @bullet
6781
@item uint32x4_t vextq_u32 (uint32x4_t, uint32x4_t, const int)
6782
@*@emph{Form of expected instruction(s):} @code{vext.32 @var{q0}, @var{q0}, @var{q0}, #@var{0}}
6783
@end itemize
6784
 
6785
 
6786
@itemize @bullet
6787
@item uint16x8_t vextq_u16 (uint16x8_t, uint16x8_t, const int)
6788
@*@emph{Form of expected instruction(s):} @code{vext.16 @var{q0}, @var{q0}, @var{q0}, #@var{0}}
6789
@end itemize
6790
 
6791
 
6792
@itemize @bullet
6793
@item uint8x16_t vextq_u8 (uint8x16_t, uint8x16_t, const int)
6794
@*@emph{Form of expected instruction(s):} @code{vext.8 @var{q0}, @var{q0}, @var{q0}, #@var{0}}
6795
@end itemize
6796
 
6797
 
6798
@itemize @bullet
6799
@item int32x4_t vextq_s32 (int32x4_t, int32x4_t, const int)
6800
@*@emph{Form of expected instruction(s):} @code{vext.32 @var{q0}, @var{q0}, @var{q0}, #@var{0}}
6801
@end itemize
6802
 
6803
 
6804
@itemize @bullet
6805
@item int16x8_t vextq_s16 (int16x8_t, int16x8_t, const int)
6806
@*@emph{Form of expected instruction(s):} @code{vext.16 @var{q0}, @var{q0}, @var{q0}, #@var{0}}
6807
@end itemize
6808
 
6809
 
6810
@itemize @bullet
6811
@item int8x16_t vextq_s8 (int8x16_t, int8x16_t, const int)
6812
@*@emph{Form of expected instruction(s):} @code{vext.8 @var{q0}, @var{q0}, @var{q0}, #@var{0}}
6813
@end itemize
6814
 
6815
 
6816
@itemize @bullet
6817
@item uint64x2_t vextq_u64 (uint64x2_t, uint64x2_t, const int)
6818
@*@emph{Form of expected instruction(s):} @code{vext.64 @var{q0}, @var{q0}, @var{q0}, #@var{0}}
6819
@end itemize
6820
 
6821
 
6822
@itemize @bullet
6823
@item int64x2_t vextq_s64 (int64x2_t, int64x2_t, const int)
6824
@*@emph{Form of expected instruction(s):} @code{vext.64 @var{q0}, @var{q0}, @var{q0}, #@var{0}}
6825
@end itemize
6826
 
6827
 
6828
@itemize @bullet
6829
@item float32x4_t vextq_f32 (float32x4_t, float32x4_t, const int)
6830
@*@emph{Form of expected instruction(s):} @code{vext.32 @var{q0}, @var{q0}, @var{q0}, #@var{0}}
6831
@end itemize
6832
 
6833
 
6834
@itemize @bullet
6835
@item poly16x8_t vextq_p16 (poly16x8_t, poly16x8_t, const int)
6836
@*@emph{Form of expected instruction(s):} @code{vext.16 @var{q0}, @var{q0}, @var{q0}, #@var{0}}
6837
@end itemize
6838
 
6839
 
6840
@itemize @bullet
6841
@item poly8x16_t vextq_p8 (poly8x16_t, poly8x16_t, const int)
6842
@*@emph{Form of expected instruction(s):} @code{vext.8 @var{q0}, @var{q0}, @var{q0}, #@var{0}}
6843
@end itemize
6844
 
6845
 
6846
 
6847
 
6848
@subsubsection Reverse elements
6849
 
6850
@itemize @bullet
6851
@item uint32x2_t vrev64_u32 (uint32x2_t)
6852
@*@emph{Form of expected instruction(s):} @code{vrev64.32 @var{d0}, @var{d0}}
6853
@end itemize
6854
 
6855
 
6856
@itemize @bullet
6857
@item uint16x4_t vrev64_u16 (uint16x4_t)
6858
@*@emph{Form of expected instruction(s):} @code{vrev64.16 @var{d0}, @var{d0}}
6859
@end itemize
6860
 
6861
 
6862
@itemize @bullet
6863
@item uint8x8_t vrev64_u8 (uint8x8_t)
6864
@*@emph{Form of expected instruction(s):} @code{vrev64.8 @var{d0}, @var{d0}}
6865
@end itemize
6866
 
6867
 
6868
@itemize @bullet
6869
@item int32x2_t vrev64_s32 (int32x2_t)
6870
@*@emph{Form of expected instruction(s):} @code{vrev64.32 @var{d0}, @var{d0}}
6871
@end itemize
6872
 
6873
 
6874
@itemize @bullet
6875
@item int16x4_t vrev64_s16 (int16x4_t)
6876
@*@emph{Form of expected instruction(s):} @code{vrev64.16 @var{d0}, @var{d0}}
6877
@end itemize
6878
 
6879
 
6880
@itemize @bullet
6881
@item int8x8_t vrev64_s8 (int8x8_t)
6882
@*@emph{Form of expected instruction(s):} @code{vrev64.8 @var{d0}, @var{d0}}
6883
@end itemize
6884
 
6885
 
6886
@itemize @bullet
6887
@item float32x2_t vrev64_f32 (float32x2_t)
6888
@*@emph{Form of expected instruction(s):} @code{vrev64.32 @var{d0}, @var{d0}}
6889
@end itemize
6890
 
6891
 
6892
@itemize @bullet
6893
@item poly16x4_t vrev64_p16 (poly16x4_t)
6894
@*@emph{Form of expected instruction(s):} @code{vrev64.16 @var{d0}, @var{d0}}
6895
@end itemize
6896
 
6897
 
6898
@itemize @bullet
6899
@item poly8x8_t vrev64_p8 (poly8x8_t)
6900
@*@emph{Form of expected instruction(s):} @code{vrev64.8 @var{d0}, @var{d0}}
6901
@end itemize
6902
 
6903
 
6904
@itemize @bullet
6905
@item uint32x4_t vrev64q_u32 (uint32x4_t)
6906
@*@emph{Form of expected instruction(s):} @code{vrev64.32 @var{q0}, @var{q0}}
6907
@end itemize
6908
 
6909
 
6910
@itemize @bullet
6911
@item uint16x8_t vrev64q_u16 (uint16x8_t)
6912
@*@emph{Form of expected instruction(s):} @code{vrev64.16 @var{q0}, @var{q0}}
6913
@end itemize
6914
 
6915
 
6916
@itemize @bullet
6917
@item uint8x16_t vrev64q_u8 (uint8x16_t)
6918
@*@emph{Form of expected instruction(s):} @code{vrev64.8 @var{q0}, @var{q0}}
6919
@end itemize
6920
 
6921
 
6922
@itemize @bullet
6923
@item int32x4_t vrev64q_s32 (int32x4_t)
6924
@*@emph{Form of expected instruction(s):} @code{vrev64.32 @var{q0}, @var{q0}}
6925
@end itemize
6926
 
6927
 
6928
@itemize @bullet
6929
@item int16x8_t vrev64q_s16 (int16x8_t)
6930
@*@emph{Form of expected instruction(s):} @code{vrev64.16 @var{q0}, @var{q0}}
6931
@end itemize
6932
 
6933
 
6934
@itemize @bullet
6935
@item int8x16_t vrev64q_s8 (int8x16_t)
6936
@*@emph{Form of expected instruction(s):} @code{vrev64.8 @var{q0}, @var{q0}}
6937
@end itemize
6938
 
6939
 
6940
@itemize @bullet
6941
@item float32x4_t vrev64q_f32 (float32x4_t)
6942
@*@emph{Form of expected instruction(s):} @code{vrev64.32 @var{q0}, @var{q0}}
6943
@end itemize
6944
 
6945
 
6946
@itemize @bullet
6947
@item poly16x8_t vrev64q_p16 (poly16x8_t)
6948
@*@emph{Form of expected instruction(s):} @code{vrev64.16 @var{q0}, @var{q0}}
6949
@end itemize
6950
 
6951
 
6952
@itemize @bullet
6953
@item poly8x16_t vrev64q_p8 (poly8x16_t)
6954
@*@emph{Form of expected instruction(s):} @code{vrev64.8 @var{q0}, @var{q0}}
6955
@end itemize
6956
 
6957
 
6958
@itemize @bullet
6959
@item uint16x4_t vrev32_u16 (uint16x4_t)
6960
@*@emph{Form of expected instruction(s):} @code{vrev32.16 @var{d0}, @var{d0}}
6961
@end itemize
6962
 
6963
 
6964
@itemize @bullet
6965
@item int16x4_t vrev32_s16 (int16x4_t)
6966
@*@emph{Form of expected instruction(s):} @code{vrev32.16 @var{d0}, @var{d0}}
6967
@end itemize
6968
 
6969
 
6970
@itemize @bullet
6971
@item uint8x8_t vrev32_u8 (uint8x8_t)
6972
@*@emph{Form of expected instruction(s):} @code{vrev32.8 @var{d0}, @var{d0}}
6973
@end itemize
6974
 
6975
 
6976
@itemize @bullet
6977
@item int8x8_t vrev32_s8 (int8x8_t)
6978
@*@emph{Form of expected instruction(s):} @code{vrev32.8 @var{d0}, @var{d0}}
6979
@end itemize
6980
 
6981
 
6982
@itemize @bullet
6983
@item poly16x4_t vrev32_p16 (poly16x4_t)
6984
@*@emph{Form of expected instruction(s):} @code{vrev32.16 @var{d0}, @var{d0}}
6985
@end itemize
6986
 
6987
 
6988
@itemize @bullet
6989
@item poly8x8_t vrev32_p8 (poly8x8_t)
6990
@*@emph{Form of expected instruction(s):} @code{vrev32.8 @var{d0}, @var{d0}}
6991
@end itemize
6992
 
6993
 
6994
@itemize @bullet
6995
@item uint16x8_t vrev32q_u16 (uint16x8_t)
6996
@*@emph{Form of expected instruction(s):} @code{vrev32.16 @var{q0}, @var{q0}}
6997
@end itemize
6998
 
6999
 
7000
@itemize @bullet
7001
@item int16x8_t vrev32q_s16 (int16x8_t)
7002
@*@emph{Form of expected instruction(s):} @code{vrev32.16 @var{q0}, @var{q0}}
7003
@end itemize
7004
 
7005
 
7006
@itemize @bullet
7007
@item uint8x16_t vrev32q_u8 (uint8x16_t)
7008
@*@emph{Form of expected instruction(s):} @code{vrev32.8 @var{q0}, @var{q0}}
7009
@end itemize
7010
 
7011
 
7012
@itemize @bullet
7013
@item int8x16_t vrev32q_s8 (int8x16_t)
7014
@*@emph{Form of expected instruction(s):} @code{vrev32.8 @var{q0}, @var{q0}}
7015
@end itemize
7016
 
7017
 
7018
@itemize @bullet
7019
@item poly16x8_t vrev32q_p16 (poly16x8_t)
7020
@*@emph{Form of expected instruction(s):} @code{vrev32.16 @var{q0}, @var{q0}}
7021
@end itemize
7022
 
7023
 
7024
@itemize @bullet
7025
@item poly8x16_t vrev32q_p8 (poly8x16_t)
7026
@*@emph{Form of expected instruction(s):} @code{vrev32.8 @var{q0}, @var{q0}}
7027
@end itemize
7028
 
7029
 
7030
@itemize @bullet
7031
@item uint8x8_t vrev16_u8 (uint8x8_t)
7032
@*@emph{Form of expected instruction(s):} @code{vrev16.8 @var{d0}, @var{d0}}
7033
@end itemize
7034
 
7035
 
7036
@itemize @bullet
7037
@item int8x8_t vrev16_s8 (int8x8_t)
7038
@*@emph{Form of expected instruction(s):} @code{vrev16.8 @var{d0}, @var{d0}}
7039
@end itemize
7040
 
7041
 
7042
@itemize @bullet
7043
@item poly8x8_t vrev16_p8 (poly8x8_t)
7044
@*@emph{Form of expected instruction(s):} @code{vrev16.8 @var{d0}, @var{d0}}
7045
@end itemize
7046
 
7047
 
7048
@itemize @bullet
7049
@item uint8x16_t vrev16q_u8 (uint8x16_t)
7050
@*@emph{Form of expected instruction(s):} @code{vrev16.8 @var{q0}, @var{q0}}
7051
@end itemize
7052
 
7053
 
7054
@itemize @bullet
7055
@item int8x16_t vrev16q_s8 (int8x16_t)
7056
@*@emph{Form of expected instruction(s):} @code{vrev16.8 @var{q0}, @var{q0}}
7057
@end itemize
7058
 
7059
 
7060
@itemize @bullet
7061
@item poly8x16_t vrev16q_p8 (poly8x16_t)
7062
@*@emph{Form of expected instruction(s):} @code{vrev16.8 @var{q0}, @var{q0}}
7063
@end itemize
7064
 
7065
 
7066
 
7067
 
7068
@subsubsection Bit selection
7069
 
7070
@itemize @bullet
7071
@item uint32x2_t vbsl_u32 (uint32x2_t, uint32x2_t, uint32x2_t)
7072
@*@emph{Form of expected instruction(s):} @code{vbsl @var{d0}, @var{d0}, @var{d0}} @emph{or} @code{vbit @var{d0}, @var{d0}, @var{d0}} @emph{or} @code{vbif @var{d0}, @var{d0}, @var{d0}}
7073
@end itemize
7074
 
7075
 
7076
@itemize @bullet
7077
@item uint16x4_t vbsl_u16 (uint16x4_t, uint16x4_t, uint16x4_t)
7078
@*@emph{Form of expected instruction(s):} @code{vbsl @var{d0}, @var{d0}, @var{d0}} @emph{or} @code{vbit @var{d0}, @var{d0}, @var{d0}} @emph{or} @code{vbif @var{d0}, @var{d0}, @var{d0}}
7079
@end itemize
7080
 
7081
 
7082
@itemize @bullet
7083
@item uint8x8_t vbsl_u8 (uint8x8_t, uint8x8_t, uint8x8_t)
7084
@*@emph{Form of expected instruction(s):} @code{vbsl @var{d0}, @var{d0}, @var{d0}} @emph{or} @code{vbit @var{d0}, @var{d0}, @var{d0}} @emph{or} @code{vbif @var{d0}, @var{d0}, @var{d0}}
7085
@end itemize
7086
 
7087
 
7088
@itemize @bullet
7089
@item int32x2_t vbsl_s32 (uint32x2_t, int32x2_t, int32x2_t)
7090
@*@emph{Form of expected instruction(s):} @code{vbsl @var{d0}, @var{d0}, @var{d0}} @emph{or} @code{vbit @var{d0}, @var{d0}, @var{d0}} @emph{or} @code{vbif @var{d0}, @var{d0}, @var{d0}}
7091
@end itemize
7092
 
7093
 
7094
@itemize @bullet
7095
@item int16x4_t vbsl_s16 (uint16x4_t, int16x4_t, int16x4_t)
7096
@*@emph{Form of expected instruction(s):} @code{vbsl @var{d0}, @var{d0}, @var{d0}} @emph{or} @code{vbit @var{d0}, @var{d0}, @var{d0}} @emph{or} @code{vbif @var{d0}, @var{d0}, @var{d0}}
7097
@end itemize
7098
 
7099
 
7100
@itemize @bullet
7101
@item int8x8_t vbsl_s8 (uint8x8_t, int8x8_t, int8x8_t)
7102
@*@emph{Form of expected instruction(s):} @code{vbsl @var{d0}, @var{d0}, @var{d0}} @emph{or} @code{vbit @var{d0}, @var{d0}, @var{d0}} @emph{or} @code{vbif @var{d0}, @var{d0}, @var{d0}}
7103
@end itemize
7104
 
7105
 
7106
@itemize @bullet
7107
@item uint64x1_t vbsl_u64 (uint64x1_t, uint64x1_t, uint64x1_t)
7108
@*@emph{Form of expected instruction(s):} @code{vbsl @var{d0}, @var{d0}, @var{d0}} @emph{or} @code{vbit @var{d0}, @var{d0}, @var{d0}} @emph{or} @code{vbif @var{d0}, @var{d0}, @var{d0}}
7109
@end itemize
7110
 
7111
 
7112
@itemize @bullet
7113
@item int64x1_t vbsl_s64 (uint64x1_t, int64x1_t, int64x1_t)
7114
@*@emph{Form of expected instruction(s):} @code{vbsl @var{d0}, @var{d0}, @var{d0}} @emph{or} @code{vbit @var{d0}, @var{d0}, @var{d0}} @emph{or} @code{vbif @var{d0}, @var{d0}, @var{d0}}
7115
@end itemize
7116
 
7117
 
7118
@itemize @bullet
7119
@item float32x2_t vbsl_f32 (uint32x2_t, float32x2_t, float32x2_t)
7120
@*@emph{Form of expected instruction(s):} @code{vbsl @var{d0}, @var{d0}, @var{d0}} @emph{or} @code{vbit @var{d0}, @var{d0}, @var{d0}} @emph{or} @code{vbif @var{d0}, @var{d0}, @var{d0}}
7121
@end itemize
7122
 
7123
 
7124
@itemize @bullet
7125
@item poly16x4_t vbsl_p16 (uint16x4_t, poly16x4_t, poly16x4_t)
7126
@*@emph{Form of expected instruction(s):} @code{vbsl @var{d0}, @var{d0}, @var{d0}} @emph{or} @code{vbit @var{d0}, @var{d0}, @var{d0}} @emph{or} @code{vbif @var{d0}, @var{d0}, @var{d0}}
7127
@end itemize
7128
 
7129
 
7130
@itemize @bullet
7131
@item poly8x8_t vbsl_p8 (uint8x8_t, poly8x8_t, poly8x8_t)
7132
@*@emph{Form of expected instruction(s):} @code{vbsl @var{d0}, @var{d0}, @var{d0}} @emph{or} @code{vbit @var{d0}, @var{d0}, @var{d0}} @emph{or} @code{vbif @var{d0}, @var{d0}, @var{d0}}
7133
@end itemize
7134
 
7135
 
7136
@itemize @bullet
7137
@item uint32x4_t vbslq_u32 (uint32x4_t, uint32x4_t, uint32x4_t)
7138
@*@emph{Form of expected instruction(s):} @code{vbsl @var{q0}, @var{q0}, @var{q0}} @emph{or} @code{vbit @var{q0}, @var{q0}, @var{q0}} @emph{or} @code{vbif @var{q0}, @var{q0}, @var{q0}}
7139
@end itemize
7140
 
7141
 
7142
@itemize @bullet
7143
@item uint16x8_t vbslq_u16 (uint16x8_t, uint16x8_t, uint16x8_t)
7144
@*@emph{Form of expected instruction(s):} @code{vbsl @var{q0}, @var{q0}, @var{q0}} @emph{or} @code{vbit @var{q0}, @var{q0}, @var{q0}} @emph{or} @code{vbif @var{q0}, @var{q0}, @var{q0}}
7145
@end itemize
7146
 
7147
 
7148
@itemize @bullet
7149
@item uint8x16_t vbslq_u8 (uint8x16_t, uint8x16_t, uint8x16_t)
7150
@*@emph{Form of expected instruction(s):} @code{vbsl @var{q0}, @var{q0}, @var{q0}} @emph{or} @code{vbit @var{q0}, @var{q0}, @var{q0}} @emph{or} @code{vbif @var{q0}, @var{q0}, @var{q0}}
7151
@end itemize
7152
 
7153
 
7154
@itemize @bullet
7155
@item int32x4_t vbslq_s32 (uint32x4_t, int32x4_t, int32x4_t)
7156
@*@emph{Form of expected instruction(s):} @code{vbsl @var{q0}, @var{q0}, @var{q0}} @emph{or} @code{vbit @var{q0}, @var{q0}, @var{q0}} @emph{or} @code{vbif @var{q0}, @var{q0}, @var{q0}}
7157
@end itemize
7158
 
7159
 
7160
@itemize @bullet
7161
@item int16x8_t vbslq_s16 (uint16x8_t, int16x8_t, int16x8_t)
7162
@*@emph{Form of expected instruction(s):} @code{vbsl @var{q0}, @var{q0}, @var{q0}} @emph{or} @code{vbit @var{q0}, @var{q0}, @var{q0}} @emph{or} @code{vbif @var{q0}, @var{q0}, @var{q0}}
7163
@end itemize
7164
 
7165
 
7166
@itemize @bullet
7167
@item int8x16_t vbslq_s8 (uint8x16_t, int8x16_t, int8x16_t)
7168
@*@emph{Form of expected instruction(s):} @code{vbsl @var{q0}, @var{q0}, @var{q0}} @emph{or} @code{vbit @var{q0}, @var{q0}, @var{q0}} @emph{or} @code{vbif @var{q0}, @var{q0}, @var{q0}}
7169
@end itemize
7170
 
7171
 
7172
@itemize @bullet
7173
@item uint64x2_t vbslq_u64 (uint64x2_t, uint64x2_t, uint64x2_t)
7174
@*@emph{Form of expected instruction(s):} @code{vbsl @var{q0}, @var{q0}, @var{q0}} @emph{or} @code{vbit @var{q0}, @var{q0}, @var{q0}} @emph{or} @code{vbif @var{q0}, @var{q0}, @var{q0}}
7175
@end itemize
7176
 
7177
 
7178
@itemize @bullet
7179
@item int64x2_t vbslq_s64 (uint64x2_t, int64x2_t, int64x2_t)
7180
@*@emph{Form of expected instruction(s):} @code{vbsl @var{q0}, @var{q0}, @var{q0}} @emph{or} @code{vbit @var{q0}, @var{q0}, @var{q0}} @emph{or} @code{vbif @var{q0}, @var{q0}, @var{q0}}
7181
@end itemize
7182
 
7183
 
7184
@itemize @bullet
7185
@item float32x4_t vbslq_f32 (uint32x4_t, float32x4_t, float32x4_t)
7186
@*@emph{Form of expected instruction(s):} @code{vbsl @var{q0}, @var{q0}, @var{q0}} @emph{or} @code{vbit @var{q0}, @var{q0}, @var{q0}} @emph{or} @code{vbif @var{q0}, @var{q0}, @var{q0}}
7187
@end itemize
7188
 
7189
 
7190
@itemize @bullet
7191
@item poly16x8_t vbslq_p16 (uint16x8_t, poly16x8_t, poly16x8_t)
7192
@*@emph{Form of expected instruction(s):} @code{vbsl @var{q0}, @var{q0}, @var{q0}} @emph{or} @code{vbit @var{q0}, @var{q0}, @var{q0}} @emph{or} @code{vbif @var{q0}, @var{q0}, @var{q0}}
7193
@end itemize
7194
 
7195
 
7196
@itemize @bullet
7197
@item poly8x16_t vbslq_p8 (uint8x16_t, poly8x16_t, poly8x16_t)
7198
@*@emph{Form of expected instruction(s):} @code{vbsl @var{q0}, @var{q0}, @var{q0}} @emph{or} @code{vbit @var{q0}, @var{q0}, @var{q0}} @emph{or} @code{vbif @var{q0}, @var{q0}, @var{q0}}
7199
@end itemize
7200
 
7201
 
7202
 
7203
 
7204
@subsubsection Transpose elements
7205
 
7206
@itemize @bullet
7207
@item uint32x2x2_t vtrn_u32 (uint32x2_t, uint32x2_t)
7208
@*@emph{Form of expected instruction(s):} @code{vtrn.32 @var{d0}, @var{d1}}
7209
@end itemize
7210
 
7211
 
7212
@itemize @bullet
7213
@item uint16x4x2_t vtrn_u16 (uint16x4_t, uint16x4_t)
7214
@*@emph{Form of expected instruction(s):} @code{vtrn.16 @var{d0}, @var{d1}}
7215
@end itemize
7216
 
7217
 
7218
@itemize @bullet
7219
@item uint8x8x2_t vtrn_u8 (uint8x8_t, uint8x8_t)
7220
@*@emph{Form of expected instruction(s):} @code{vtrn.8 @var{d0}, @var{d1}}
7221
@end itemize
7222
 
7223
 
7224
@itemize @bullet
7225
@item int32x2x2_t vtrn_s32 (int32x2_t, int32x2_t)
7226
@*@emph{Form of expected instruction(s):} @code{vtrn.32 @var{d0}, @var{d1}}
7227
@end itemize
7228
 
7229
 
7230
@itemize @bullet
7231
@item int16x4x2_t vtrn_s16 (int16x4_t, int16x4_t)
7232
@*@emph{Form of expected instruction(s):} @code{vtrn.16 @var{d0}, @var{d1}}
7233
@end itemize
7234
 
7235
 
7236
@itemize @bullet
7237
@item int8x8x2_t vtrn_s8 (int8x8_t, int8x8_t)
7238
@*@emph{Form of expected instruction(s):} @code{vtrn.8 @var{d0}, @var{d1}}
7239
@end itemize
7240
 
7241
 
7242
@itemize @bullet
7243
@item float32x2x2_t vtrn_f32 (float32x2_t, float32x2_t)
7244
@*@emph{Form of expected instruction(s):} @code{vtrn.32 @var{d0}, @var{d1}}
7245
@end itemize
7246
 
7247
 
7248
@itemize @bullet
7249
@item poly16x4x2_t vtrn_p16 (poly16x4_t, poly16x4_t)
7250
@*@emph{Form of expected instruction(s):} @code{vtrn.16 @var{d0}, @var{d1}}
7251
@end itemize
7252
 
7253
 
7254
@itemize @bullet
7255
@item poly8x8x2_t vtrn_p8 (poly8x8_t, poly8x8_t)
7256
@*@emph{Form of expected instruction(s):} @code{vtrn.8 @var{d0}, @var{d1}}
7257
@end itemize
7258
 
7259
 
7260
@itemize @bullet
7261
@item uint32x4x2_t vtrnq_u32 (uint32x4_t, uint32x4_t)
7262
@*@emph{Form of expected instruction(s):} @code{vtrn.32 @var{q0}, @var{q1}}
7263
@end itemize
7264
 
7265
 
7266
@itemize @bullet
7267
@item uint16x8x2_t vtrnq_u16 (uint16x8_t, uint16x8_t)
7268
@*@emph{Form of expected instruction(s):} @code{vtrn.16 @var{q0}, @var{q1}}
7269
@end itemize
7270
 
7271
 
7272
@itemize @bullet
7273
@item uint8x16x2_t vtrnq_u8 (uint8x16_t, uint8x16_t)
7274
@*@emph{Form of expected instruction(s):} @code{vtrn.8 @var{q0}, @var{q1}}
7275
@end itemize
7276
 
7277
 
7278
@itemize @bullet
7279
@item int32x4x2_t vtrnq_s32 (int32x4_t, int32x4_t)
7280
@*@emph{Form of expected instruction(s):} @code{vtrn.32 @var{q0}, @var{q1}}
7281
@end itemize
7282
 
7283
 
7284
@itemize @bullet
7285
@item int16x8x2_t vtrnq_s16 (int16x8_t, int16x8_t)
7286
@*@emph{Form of expected instruction(s):} @code{vtrn.16 @var{q0}, @var{q1}}
7287
@end itemize
7288
 
7289
 
7290
@itemize @bullet
7291
@item int8x16x2_t vtrnq_s8 (int8x16_t, int8x16_t)
7292
@*@emph{Form of expected instruction(s):} @code{vtrn.8 @var{q0}, @var{q1}}
7293
@end itemize
7294
 
7295
 
7296
@itemize @bullet
7297
@item float32x4x2_t vtrnq_f32 (float32x4_t, float32x4_t)
7298
@*@emph{Form of expected instruction(s):} @code{vtrn.32 @var{q0}, @var{q1}}
7299
@end itemize
7300
 
7301
 
7302
@itemize @bullet
7303
@item poly16x8x2_t vtrnq_p16 (poly16x8_t, poly16x8_t)
7304
@*@emph{Form of expected instruction(s):} @code{vtrn.16 @var{q0}, @var{q1}}
7305
@end itemize
7306
 
7307
 
7308
@itemize @bullet
7309
@item poly8x16x2_t vtrnq_p8 (poly8x16_t, poly8x16_t)
7310
@*@emph{Form of expected instruction(s):} @code{vtrn.8 @var{q0}, @var{q1}}
7311
@end itemize
7312
 
7313
 
7314
 
7315
 
7316
@subsubsection Zip elements
7317
 
7318
@itemize @bullet
7319
@item uint32x2x2_t vzip_u32 (uint32x2_t, uint32x2_t)
7320
@*@emph{Form of expected instruction(s):} @code{vzip.32 @var{d0}, @var{d1}}
7321
@end itemize
7322
 
7323
 
7324
@itemize @bullet
7325
@item uint16x4x2_t vzip_u16 (uint16x4_t, uint16x4_t)
7326
@*@emph{Form of expected instruction(s):} @code{vzip.16 @var{d0}, @var{d1}}
7327
@end itemize
7328
 
7329
 
7330
@itemize @bullet
7331
@item uint8x8x2_t vzip_u8 (uint8x8_t, uint8x8_t)
7332
@*@emph{Form of expected instruction(s):} @code{vzip.8 @var{d0}, @var{d1}}
7333
@end itemize
7334
 
7335
 
7336
@itemize @bullet
7337
@item int32x2x2_t vzip_s32 (int32x2_t, int32x2_t)
7338
@*@emph{Form of expected instruction(s):} @code{vzip.32 @var{d0}, @var{d1}}
7339
@end itemize
7340
 
7341
 
7342
@itemize @bullet
7343
@item int16x4x2_t vzip_s16 (int16x4_t, int16x4_t)
7344
@*@emph{Form of expected instruction(s):} @code{vzip.16 @var{d0}, @var{d1}}
7345
@end itemize
7346
 
7347
 
7348
@itemize @bullet
7349
@item int8x8x2_t vzip_s8 (int8x8_t, int8x8_t)
7350
@*@emph{Form of expected instruction(s):} @code{vzip.8 @var{d0}, @var{d1}}
7351
@end itemize
7352
 
7353
 
7354
@itemize @bullet
7355
@item float32x2x2_t vzip_f32 (float32x2_t, float32x2_t)
7356
@*@emph{Form of expected instruction(s):} @code{vzip.32 @var{d0}, @var{d1}}
7357
@end itemize
7358
 
7359
 
7360
@itemize @bullet
7361
@item poly16x4x2_t vzip_p16 (poly16x4_t, poly16x4_t)
7362
@*@emph{Form of expected instruction(s):} @code{vzip.16 @var{d0}, @var{d1}}
7363
@end itemize
7364
 
7365
 
7366
@itemize @bullet
7367
@item poly8x8x2_t vzip_p8 (poly8x8_t, poly8x8_t)
7368
@*@emph{Form of expected instruction(s):} @code{vzip.8 @var{d0}, @var{d1}}
7369
@end itemize
7370
 
7371
 
7372
@itemize @bullet
7373
@item uint32x4x2_t vzipq_u32 (uint32x4_t, uint32x4_t)
7374
@*@emph{Form of expected instruction(s):} @code{vzip.32 @var{q0}, @var{q1}}
7375
@end itemize
7376
 
7377
 
7378
@itemize @bullet
7379
@item uint16x8x2_t vzipq_u16 (uint16x8_t, uint16x8_t)
7380
@*@emph{Form of expected instruction(s):} @code{vzip.16 @var{q0}, @var{q1}}
7381
@end itemize
7382
 
7383
 
7384
@itemize @bullet
7385
@item uint8x16x2_t vzipq_u8 (uint8x16_t, uint8x16_t)
7386
@*@emph{Form of expected instruction(s):} @code{vzip.8 @var{q0}, @var{q1}}
7387
@end itemize
7388
 
7389
 
7390
@itemize @bullet
7391
@item int32x4x2_t vzipq_s32 (int32x4_t, int32x4_t)
7392
@*@emph{Form of expected instruction(s):} @code{vzip.32 @var{q0}, @var{q1}}
7393
@end itemize
7394
 
7395
 
7396
@itemize @bullet
7397
@item int16x8x2_t vzipq_s16 (int16x8_t, int16x8_t)
7398
@*@emph{Form of expected instruction(s):} @code{vzip.16 @var{q0}, @var{q1}}
7399
@end itemize
7400
 
7401
 
7402
@itemize @bullet
7403
@item int8x16x2_t vzipq_s8 (int8x16_t, int8x16_t)
7404
@*@emph{Form of expected instruction(s):} @code{vzip.8 @var{q0}, @var{q1}}
7405
@end itemize
7406
 
7407
 
7408
@itemize @bullet
7409
@item float32x4x2_t vzipq_f32 (float32x4_t, float32x4_t)
7410
@*@emph{Form of expected instruction(s):} @code{vzip.32 @var{q0}, @var{q1}}
7411
@end itemize
7412
 
7413
 
7414
@itemize @bullet
7415
@item poly16x8x2_t vzipq_p16 (poly16x8_t, poly16x8_t)
7416
@*@emph{Form of expected instruction(s):} @code{vzip.16 @var{q0}, @var{q1}}
7417
@end itemize
7418
 
7419
 
7420
@itemize @bullet
7421
@item poly8x16x2_t vzipq_p8 (poly8x16_t, poly8x16_t)
7422
@*@emph{Form of expected instruction(s):} @code{vzip.8 @var{q0}, @var{q1}}
7423
@end itemize
7424
 
7425
 
7426
 
7427
 
7428
@subsubsection Unzip elements
7429
 
7430
@itemize @bullet
7431
@item uint32x2x2_t vuzp_u32 (uint32x2_t, uint32x2_t)
7432
@*@emph{Form of expected instruction(s):} @code{vuzp.32 @var{d0}, @var{d1}}
7433
@end itemize
7434
 
7435
 
7436
@itemize @bullet
7437
@item uint16x4x2_t vuzp_u16 (uint16x4_t, uint16x4_t)
7438
@*@emph{Form of expected instruction(s):} @code{vuzp.16 @var{d0}, @var{d1}}
7439
@end itemize
7440
 
7441
 
7442
@itemize @bullet
7443
@item uint8x8x2_t vuzp_u8 (uint8x8_t, uint8x8_t)
7444
@*@emph{Form of expected instruction(s):} @code{vuzp.8 @var{d0}, @var{d1}}
7445
@end itemize
7446
 
7447
 
7448
@itemize @bullet
7449
@item int32x2x2_t vuzp_s32 (int32x2_t, int32x2_t)
7450
@*@emph{Form of expected instruction(s):} @code{vuzp.32 @var{d0}, @var{d1}}
7451
@end itemize
7452
 
7453
 
7454
@itemize @bullet
7455
@item int16x4x2_t vuzp_s16 (int16x4_t, int16x4_t)
7456
@*@emph{Form of expected instruction(s):} @code{vuzp.16 @var{d0}, @var{d1}}
7457
@end itemize
7458
 
7459
 
7460
@itemize @bullet
7461
@item int8x8x2_t vuzp_s8 (int8x8_t, int8x8_t)
7462
@*@emph{Form of expected instruction(s):} @code{vuzp.8 @var{d0}, @var{d1}}
7463
@end itemize
7464
 
7465
 
7466
@itemize @bullet
7467
@item float32x2x2_t vuzp_f32 (float32x2_t, float32x2_t)
7468
@*@emph{Form of expected instruction(s):} @code{vuzp.32 @var{d0}, @var{d1}}
7469
@end itemize
7470
 
7471
 
7472
@itemize @bullet
7473
@item poly16x4x2_t vuzp_p16 (poly16x4_t, poly16x4_t)
7474
@*@emph{Form of expected instruction(s):} @code{vuzp.16 @var{d0}, @var{d1}}
7475
@end itemize
7476
 
7477
 
7478
@itemize @bullet
7479
@item poly8x8x2_t vuzp_p8 (poly8x8_t, poly8x8_t)
7480
@*@emph{Form of expected instruction(s):} @code{vuzp.8 @var{d0}, @var{d1}}
7481
@end itemize
7482
 
7483
 
7484
@itemize @bullet
7485
@item uint32x4x2_t vuzpq_u32 (uint32x4_t, uint32x4_t)
7486
@*@emph{Form of expected instruction(s):} @code{vuzp.32 @var{q0}, @var{q1}}
7487
@end itemize
7488
 
7489
 
7490
@itemize @bullet
7491
@item uint16x8x2_t vuzpq_u16 (uint16x8_t, uint16x8_t)
7492
@*@emph{Form of expected instruction(s):} @code{vuzp.16 @var{q0}, @var{q1}}
7493
@end itemize
7494
 
7495
 
7496
@itemize @bullet
7497
@item uint8x16x2_t vuzpq_u8 (uint8x16_t, uint8x16_t)
7498
@*@emph{Form of expected instruction(s):} @code{vuzp.8 @var{q0}, @var{q1}}
7499
@end itemize
7500
 
7501
 
7502
@itemize @bullet
7503
@item int32x4x2_t vuzpq_s32 (int32x4_t, int32x4_t)
7504
@*@emph{Form of expected instruction(s):} @code{vuzp.32 @var{q0}, @var{q1}}
7505
@end itemize
7506
 
7507
 
7508
@itemize @bullet
7509
@item int16x8x2_t vuzpq_s16 (int16x8_t, int16x8_t)
7510
@*@emph{Form of expected instruction(s):} @code{vuzp.16 @var{q0}, @var{q1}}
7511
@end itemize
7512
 
7513
 
7514
@itemize @bullet
7515
@item int8x16x2_t vuzpq_s8 (int8x16_t, int8x16_t)
7516
@*@emph{Form of expected instruction(s):} @code{vuzp.8 @var{q0}, @var{q1}}
7517
@end itemize
7518
 
7519
 
7520
@itemize @bullet
7521
@item float32x4x2_t vuzpq_f32 (float32x4_t, float32x4_t)
7522
@*@emph{Form of expected instruction(s):} @code{vuzp.32 @var{q0}, @var{q1}}
7523
@end itemize
7524
 
7525
 
7526
@itemize @bullet
7527
@item poly16x8x2_t vuzpq_p16 (poly16x8_t, poly16x8_t)
7528
@*@emph{Form of expected instruction(s):} @code{vuzp.16 @var{q0}, @var{q1}}
7529
@end itemize
7530
 
7531
 
7532
@itemize @bullet
7533
@item poly8x16x2_t vuzpq_p8 (poly8x16_t, poly8x16_t)
7534
@*@emph{Form of expected instruction(s):} @code{vuzp.8 @var{q0}, @var{q1}}
7535
@end itemize
7536
 
7537
 
7538
 
7539
 
7540
@subsubsection Element/structure loads, VLD1 variants
7541
 
7542
@itemize @bullet
7543
@item uint32x2_t vld1_u32 (const uint32_t *)
7544
@*@emph{Form of expected instruction(s):} @code{vld1.32 @{@var{d0}@}, [@var{r0}]}
7545
@end itemize
7546
 
7547
 
7548
@itemize @bullet
7549
@item uint16x4_t vld1_u16 (const uint16_t *)
7550
@*@emph{Form of expected instruction(s):} @code{vld1.16 @{@var{d0}@}, [@var{r0}]}
7551
@end itemize
7552
 
7553
 
7554
@itemize @bullet
7555
@item uint8x8_t vld1_u8 (const uint8_t *)
7556
@*@emph{Form of expected instruction(s):} @code{vld1.8 @{@var{d0}@}, [@var{r0}]}
7557
@end itemize
7558
 
7559
 
7560
@itemize @bullet
7561
@item int32x2_t vld1_s32 (const int32_t *)
7562
@*@emph{Form of expected instruction(s):} @code{vld1.32 @{@var{d0}@}, [@var{r0}]}
7563
@end itemize
7564
 
7565
 
7566
@itemize @bullet
7567
@item int16x4_t vld1_s16 (const int16_t *)
7568
@*@emph{Form of expected instruction(s):} @code{vld1.16 @{@var{d0}@}, [@var{r0}]}
7569
@end itemize
7570
 
7571
 
7572
@itemize @bullet
7573
@item int8x8_t vld1_s8 (const int8_t *)
7574
@*@emph{Form of expected instruction(s):} @code{vld1.8 @{@var{d0}@}, [@var{r0}]}
7575
@end itemize
7576
 
7577
 
7578
@itemize @bullet
7579
@item uint64x1_t vld1_u64 (const uint64_t *)
7580
@*@emph{Form of expected instruction(s):} @code{vld1.64 @{@var{d0}@}, [@var{r0}]}
7581
@end itemize
7582
 
7583
 
7584
@itemize @bullet
7585
@item int64x1_t vld1_s64 (const int64_t *)
7586
@*@emph{Form of expected instruction(s):} @code{vld1.64 @{@var{d0}@}, [@var{r0}]}
7587
@end itemize
7588
 
7589
 
7590
@itemize @bullet
7591
@item float32x2_t vld1_f32 (const float32_t *)
7592
@*@emph{Form of expected instruction(s):} @code{vld1.32 @{@var{d0}@}, [@var{r0}]}
7593
@end itemize
7594
 
7595
 
7596
@itemize @bullet
7597
@item poly16x4_t vld1_p16 (const poly16_t *)
7598
@*@emph{Form of expected instruction(s):} @code{vld1.16 @{@var{d0}@}, [@var{r0}]}
7599
@end itemize
7600
 
7601
 
7602
@itemize @bullet
7603
@item poly8x8_t vld1_p8 (const poly8_t *)
7604
@*@emph{Form of expected instruction(s):} @code{vld1.8 @{@var{d0}@}, [@var{r0}]}
7605
@end itemize
7606
 
7607
 
7608
@itemize @bullet
7609
@item uint32x4_t vld1q_u32 (const uint32_t *)
7610
@*@emph{Form of expected instruction(s):} @code{vld1.32 @{@var{d0}, @var{d1}@}, [@var{r0}]}
7611
@end itemize
7612
 
7613
 
7614
@itemize @bullet
7615
@item uint16x8_t vld1q_u16 (const uint16_t *)
7616
@*@emph{Form of expected instruction(s):} @code{vld1.16 @{@var{d0}, @var{d1}@}, [@var{r0}]}
7617
@end itemize
7618
 
7619
 
7620
@itemize @bullet
7621
@item uint8x16_t vld1q_u8 (const uint8_t *)
7622
@*@emph{Form of expected instruction(s):} @code{vld1.8 @{@var{d0}, @var{d1}@}, [@var{r0}]}
7623
@end itemize
7624
 
7625
 
7626
@itemize @bullet
7627
@item int32x4_t vld1q_s32 (const int32_t *)
7628
@*@emph{Form of expected instruction(s):} @code{vld1.32 @{@var{d0}, @var{d1}@}, [@var{r0}]}
7629
@end itemize
7630
 
7631
 
7632
@itemize @bullet
7633
@item int16x8_t vld1q_s16 (const int16_t *)
7634
@*@emph{Form of expected instruction(s):} @code{vld1.16 @{@var{d0}, @var{d1}@}, [@var{r0}]}
7635
@end itemize
7636
 
7637
 
7638
@itemize @bullet
7639
@item int8x16_t vld1q_s8 (const int8_t *)
7640
@*@emph{Form of expected instruction(s):} @code{vld1.8 @{@var{d0}, @var{d1}@}, [@var{r0}]}
7641
@end itemize
7642
 
7643
 
7644
@itemize @bullet
7645
@item uint64x2_t vld1q_u64 (const uint64_t *)
7646
@*@emph{Form of expected instruction(s):} @code{vld1.64 @{@var{d0}, @var{d1}@}, [@var{r0}]}
7647
@end itemize
7648
 
7649
 
7650
@itemize @bullet
7651
@item int64x2_t vld1q_s64 (const int64_t *)
7652
@*@emph{Form of expected instruction(s):} @code{vld1.64 @{@var{d0}, @var{d1}@}, [@var{r0}]}
7653
@end itemize
7654
 
7655
 
7656
@itemize @bullet
7657
@item float32x4_t vld1q_f32 (const float32_t *)
7658
@*@emph{Form of expected instruction(s):} @code{vld1.32 @{@var{d0}, @var{d1}@}, [@var{r0}]}
7659
@end itemize
7660
 
7661
 
7662
@itemize @bullet
7663
@item poly16x8_t vld1q_p16 (const poly16_t *)
7664
@*@emph{Form of expected instruction(s):} @code{vld1.16 @{@var{d0}, @var{d1}@}, [@var{r0}]}
7665
@end itemize
7666
 
7667
 
7668
@itemize @bullet
7669
@item poly8x16_t vld1q_p8 (const poly8_t *)
7670
@*@emph{Form of expected instruction(s):} @code{vld1.8 @{@var{d0}, @var{d1}@}, [@var{r0}]}
7671
@end itemize
7672
 
7673
 
7674
@itemize @bullet
7675
@item uint32x2_t vld1_lane_u32 (const uint32_t *, uint32x2_t, const int)
7676
@*@emph{Form of expected instruction(s):} @code{vld1.32 @{@var{d0}[@var{0}]@}, [@var{r0}]}
7677
@end itemize
7678
 
7679
 
7680
@itemize @bullet
7681
@item uint16x4_t vld1_lane_u16 (const uint16_t *, uint16x4_t, const int)
7682
@*@emph{Form of expected instruction(s):} @code{vld1.16 @{@var{d0}[@var{0}]@}, [@var{r0}]}
7683
@end itemize
7684
 
7685
 
7686
@itemize @bullet
7687
@item uint8x8_t vld1_lane_u8 (const uint8_t *, uint8x8_t, const int)
7688
@*@emph{Form of expected instruction(s):} @code{vld1.8 @{@var{d0}[@var{0}]@}, [@var{r0}]}
7689
@end itemize
7690
 
7691
 
7692
@itemize @bullet
7693
@item int32x2_t vld1_lane_s32 (const int32_t *, int32x2_t, const int)
7694
@*@emph{Form of expected instruction(s):} @code{vld1.32 @{@var{d0}[@var{0}]@}, [@var{r0}]}
7695
@end itemize
7696
 
7697
 
7698
@itemize @bullet
7699
@item int16x4_t vld1_lane_s16 (const int16_t *, int16x4_t, const int)
7700
@*@emph{Form of expected instruction(s):} @code{vld1.16 @{@var{d0}[@var{0}]@}, [@var{r0}]}
7701
@end itemize
7702
 
7703
 
7704
@itemize @bullet
7705
@item int8x8_t vld1_lane_s8 (const int8_t *, int8x8_t, const int)
7706
@*@emph{Form of expected instruction(s):} @code{vld1.8 @{@var{d0}[@var{0}]@}, [@var{r0}]}
7707
@end itemize
7708
 
7709
 
7710
@itemize @bullet
7711
@item float32x2_t vld1_lane_f32 (const float32_t *, float32x2_t, const int)
7712
@*@emph{Form of expected instruction(s):} @code{vld1.32 @{@var{d0}[@var{0}]@}, [@var{r0}]}
7713
@end itemize
7714
 
7715
 
7716
@itemize @bullet
7717
@item poly16x4_t vld1_lane_p16 (const poly16_t *, poly16x4_t, const int)
7718
@*@emph{Form of expected instruction(s):} @code{vld1.16 @{@var{d0}[@var{0}]@}, [@var{r0}]}
7719
@end itemize
7720
 
7721
 
7722
@itemize @bullet
7723
@item poly8x8_t vld1_lane_p8 (const poly8_t *, poly8x8_t, const int)
7724
@*@emph{Form of expected instruction(s):} @code{vld1.8 @{@var{d0}[@var{0}]@}, [@var{r0}]}
7725
@end itemize
7726
 
7727
 
7728
@itemize @bullet
7729
@item uint64x1_t vld1_lane_u64 (const uint64_t *, uint64x1_t, const int)
7730
@*@emph{Form of expected instruction(s):} @code{vld1.64 @{@var{d0}@}, [@var{r0}]}
7731
@end itemize
7732
 
7733
 
7734
@itemize @bullet
7735
@item int64x1_t vld1_lane_s64 (const int64_t *, int64x1_t, const int)
7736
@*@emph{Form of expected instruction(s):} @code{vld1.64 @{@var{d0}@}, [@var{r0}]}
7737
@end itemize
7738
 
7739
 
7740
@itemize @bullet
7741
@item uint32x4_t vld1q_lane_u32 (const uint32_t *, uint32x4_t, const int)
7742
@*@emph{Form of expected instruction(s):} @code{vld1.32 @{@var{d0}[@var{0}]@}, [@var{r0}]}
7743
@end itemize
7744
 
7745
 
7746
@itemize @bullet
7747
@item uint16x8_t vld1q_lane_u16 (const uint16_t *, uint16x8_t, const int)
7748
@*@emph{Form of expected instruction(s):} @code{vld1.16 @{@var{d0}[@var{0}]@}, [@var{r0}]}
7749
@end itemize
7750
 
7751
 
7752
@itemize @bullet
7753
@item uint8x16_t vld1q_lane_u8 (const uint8_t *, uint8x16_t, const int)
7754
@*@emph{Form of expected instruction(s):} @code{vld1.8 @{@var{d0}[@var{0}]@}, [@var{r0}]}
7755
@end itemize
7756
 
7757
 
7758
@itemize @bullet
7759
@item int32x4_t vld1q_lane_s32 (const int32_t *, int32x4_t, const int)
7760
@*@emph{Form of expected instruction(s):} @code{vld1.32 @{@var{d0}[@var{0}]@}, [@var{r0}]}
7761
@end itemize
7762
 
7763
 
7764
@itemize @bullet
7765
@item int16x8_t vld1q_lane_s16 (const int16_t *, int16x8_t, const int)
7766
@*@emph{Form of expected instruction(s):} @code{vld1.16 @{@var{d0}[@var{0}]@}, [@var{r0}]}
7767
@end itemize
7768
 
7769
 
7770
@itemize @bullet
7771
@item int8x16_t vld1q_lane_s8 (const int8_t *, int8x16_t, const int)
7772
@*@emph{Form of expected instruction(s):} @code{vld1.8 @{@var{d0}[@var{0}]@}, [@var{r0}]}
7773
@end itemize
7774
 
7775
 
7776
@itemize @bullet
7777
@item float32x4_t vld1q_lane_f32 (const float32_t *, float32x4_t, const int)
7778
@*@emph{Form of expected instruction(s):} @code{vld1.32 @{@var{d0}[@var{0}]@}, [@var{r0}]}
7779
@end itemize
7780
 
7781
 
7782
@itemize @bullet
7783
@item poly16x8_t vld1q_lane_p16 (const poly16_t *, poly16x8_t, const int)
7784
@*@emph{Form of expected instruction(s):} @code{vld1.16 @{@var{d0}[@var{0}]@}, [@var{r0}]}
7785
@end itemize
7786
 
7787
 
7788
@itemize @bullet
7789
@item poly8x16_t vld1q_lane_p8 (const poly8_t *, poly8x16_t, const int)
7790
@*@emph{Form of expected instruction(s):} @code{vld1.8 @{@var{d0}[@var{0}]@}, [@var{r0}]}
7791
@end itemize
7792
 
7793
 
7794
@itemize @bullet
7795
@item uint64x2_t vld1q_lane_u64 (const uint64_t *, uint64x2_t, const int)
7796
@*@emph{Form of expected instruction(s):} @code{vld1.64 @{@var{d0}@}, [@var{r0}]}
7797
@end itemize
7798
 
7799
 
7800
@itemize @bullet
7801
@item int64x2_t vld1q_lane_s64 (const int64_t *, int64x2_t, const int)
7802
@*@emph{Form of expected instruction(s):} @code{vld1.64 @{@var{d0}@}, [@var{r0}]}
7803
@end itemize
7804
 
7805
 
7806
@itemize @bullet
7807
@item uint32x2_t vld1_dup_u32 (const uint32_t *)
7808
@*@emph{Form of expected instruction(s):} @code{vld1.32 @{@var{d0}[]@}, [@var{r0}]}
7809
@end itemize
7810
 
7811
 
7812
@itemize @bullet
7813
@item uint16x4_t vld1_dup_u16 (const uint16_t *)
7814
@*@emph{Form of expected instruction(s):} @code{vld1.16 @{@var{d0}[]@}, [@var{r0}]}
7815
@end itemize
7816
 
7817
 
7818
@itemize @bullet
7819
@item uint8x8_t vld1_dup_u8 (const uint8_t *)
7820
@*@emph{Form of expected instruction(s):} @code{vld1.8 @{@var{d0}[]@}, [@var{r0}]}
7821
@end itemize
7822
 
7823
 
7824
@itemize @bullet
7825
@item int32x2_t vld1_dup_s32 (const int32_t *)
7826
@*@emph{Form of expected instruction(s):} @code{vld1.32 @{@var{d0}[]@}, [@var{r0}]}
7827
@end itemize
7828
 
7829
 
7830
@itemize @bullet
7831
@item int16x4_t vld1_dup_s16 (const int16_t *)
7832
@*@emph{Form of expected instruction(s):} @code{vld1.16 @{@var{d0}[]@}, [@var{r0}]}
7833
@end itemize
7834
 
7835
 
7836
@itemize @bullet
7837
@item int8x8_t vld1_dup_s8 (const int8_t *)
7838
@*@emph{Form of expected instruction(s):} @code{vld1.8 @{@var{d0}[]@}, [@var{r0}]}
7839
@end itemize
7840
 
7841
 
7842
@itemize @bullet
7843
@item float32x2_t vld1_dup_f32 (const float32_t *)
7844
@*@emph{Form of expected instruction(s):} @code{vld1.32 @{@var{d0}[]@}, [@var{r0}]}
7845
@end itemize
7846
 
7847
 
7848
@itemize @bullet
7849
@item poly16x4_t vld1_dup_p16 (const poly16_t *)
7850
@*@emph{Form of expected instruction(s):} @code{vld1.16 @{@var{d0}[]@}, [@var{r0}]}
7851
@end itemize
7852
 
7853
 
7854
@itemize @bullet
7855
@item poly8x8_t vld1_dup_p8 (const poly8_t *)
7856
@*@emph{Form of expected instruction(s):} @code{vld1.8 @{@var{d0}[]@}, [@var{r0}]}
7857
@end itemize
7858
 
7859
 
7860
@itemize @bullet
7861
@item uint64x1_t vld1_dup_u64 (const uint64_t *)
7862
@*@emph{Form of expected instruction(s):} @code{vld1.64 @{@var{d0}@}, [@var{r0}]}
7863
@end itemize
7864
 
7865
 
7866
@itemize @bullet
7867
@item int64x1_t vld1_dup_s64 (const int64_t *)
7868
@*@emph{Form of expected instruction(s):} @code{vld1.64 @{@var{d0}@}, [@var{r0}]}
7869
@end itemize
7870
 
7871
 
7872
@itemize @bullet
7873
@item uint32x4_t vld1q_dup_u32 (const uint32_t *)
7874
@*@emph{Form of expected instruction(s):} @code{vld1.32 @{@var{d0}[], @var{d1}[]@}, [@var{r0}]}
7875
@end itemize
7876
 
7877
 
7878
@itemize @bullet
7879
@item uint16x8_t vld1q_dup_u16 (const uint16_t *)
7880
@*@emph{Form of expected instruction(s):} @code{vld1.16 @{@var{d0}[], @var{d1}[]@}, [@var{r0}]}
7881
@end itemize
7882
 
7883
 
7884
@itemize @bullet
7885
@item uint8x16_t vld1q_dup_u8 (const uint8_t *)
7886
@*@emph{Form of expected instruction(s):} @code{vld1.8 @{@var{d0}[], @var{d1}[]@}, [@var{r0}]}
7887
@end itemize
7888
 
7889
 
7890
@itemize @bullet
7891
@item int32x4_t vld1q_dup_s32 (const int32_t *)
7892
@*@emph{Form of expected instruction(s):} @code{vld1.32 @{@var{d0}[], @var{d1}[]@}, [@var{r0}]}
7893
@end itemize
7894
 
7895
 
7896
@itemize @bullet
7897
@item int16x8_t vld1q_dup_s16 (const int16_t *)
7898
@*@emph{Form of expected instruction(s):} @code{vld1.16 @{@var{d0}[], @var{d1}[]@}, [@var{r0}]}
7899
@end itemize
7900
 
7901
 
7902
@itemize @bullet
7903
@item int8x16_t vld1q_dup_s8 (const int8_t *)
7904
@*@emph{Form of expected instruction(s):} @code{vld1.8 @{@var{d0}[], @var{d1}[]@}, [@var{r0}]}
7905
@end itemize
7906
 
7907
 
7908
@itemize @bullet
7909
@item float32x4_t vld1q_dup_f32 (const float32_t *)
7910
@*@emph{Form of expected instruction(s):} @code{vld1.32 @{@var{d0}[], @var{d1}[]@}, [@var{r0}]}
7911
@end itemize
7912
 
7913
 
7914
@itemize @bullet
7915
@item poly16x8_t vld1q_dup_p16 (const poly16_t *)
7916
@*@emph{Form of expected instruction(s):} @code{vld1.16 @{@var{d0}[], @var{d1}[]@}, [@var{r0}]}
7917
@end itemize
7918
 
7919
 
7920
@itemize @bullet
7921
@item poly8x16_t vld1q_dup_p8 (const poly8_t *)
7922
@*@emph{Form of expected instruction(s):} @code{vld1.8 @{@var{d0}[], @var{d1}[]@}, [@var{r0}]}
7923
@end itemize
7924
 
7925
 
7926
@itemize @bullet
7927
@item uint64x2_t vld1q_dup_u64 (const uint64_t *)
7928
@*@emph{Form of expected instruction(s):} @code{vld1.64 @{@var{d0}, @var{d1}@}, [@var{r0}]}
7929
@end itemize
7930
 
7931
 
7932
@itemize @bullet
7933
@item int64x2_t vld1q_dup_s64 (const int64_t *)
7934
@*@emph{Form of expected instruction(s):} @code{vld1.64 @{@var{d0}, @var{d1}@}, [@var{r0}]}
7935
@end itemize
7936
 
7937
 
7938
 
7939
 
7940
@subsubsection Element/structure stores, VST1 variants
7941
 
7942
@itemize @bullet
7943
@item void vst1_u32 (uint32_t *, uint32x2_t)
7944
@*@emph{Form of expected instruction(s):} @code{vst1.32 @{@var{d0}@}, [@var{r0}]}
7945
@end itemize
7946
 
7947
 
7948
@itemize @bullet
7949
@item void vst1_u16 (uint16_t *, uint16x4_t)
7950
@*@emph{Form of expected instruction(s):} @code{vst1.16 @{@var{d0}@}, [@var{r0}]}
7951
@end itemize
7952
 
7953
 
7954
@itemize @bullet
7955
@item void vst1_u8 (uint8_t *, uint8x8_t)
7956
@*@emph{Form of expected instruction(s):} @code{vst1.8 @{@var{d0}@}, [@var{r0}]}
7957
@end itemize
7958
 
7959
 
7960
@itemize @bullet
7961
@item void vst1_s32 (int32_t *, int32x2_t)
7962
@*@emph{Form of expected instruction(s):} @code{vst1.32 @{@var{d0}@}, [@var{r0}]}
7963
@end itemize
7964
 
7965
 
7966
@itemize @bullet
7967
@item void vst1_s16 (int16_t *, int16x4_t)
7968
@*@emph{Form of expected instruction(s):} @code{vst1.16 @{@var{d0}@}, [@var{r0}]}
7969
@end itemize
7970
 
7971
 
7972
@itemize @bullet
7973
@item void vst1_s8 (int8_t *, int8x8_t)
7974
@*@emph{Form of expected instruction(s):} @code{vst1.8 @{@var{d0}@}, [@var{r0}]}
7975
@end itemize
7976
 
7977
 
7978
@itemize @bullet
7979
@item void vst1_u64 (uint64_t *, uint64x1_t)
7980
@*@emph{Form of expected instruction(s):} @code{vst1.64 @{@var{d0}@}, [@var{r0}]}
7981
@end itemize
7982
 
7983
 
7984
@itemize @bullet
7985
@item void vst1_s64 (int64_t *, int64x1_t)
7986
@*@emph{Form of expected instruction(s):} @code{vst1.64 @{@var{d0}@}, [@var{r0}]}
7987
@end itemize
7988
 
7989
 
7990
@itemize @bullet
7991
@item void vst1_f32 (float32_t *, float32x2_t)
7992
@*@emph{Form of expected instruction(s):} @code{vst1.32 @{@var{d0}@}, [@var{r0}]}
7993
@end itemize
7994
 
7995
 
7996
@itemize @bullet
7997
@item void vst1_p16 (poly16_t *, poly16x4_t)
7998
@*@emph{Form of expected instruction(s):} @code{vst1.16 @{@var{d0}@}, [@var{r0}]}
7999
@end itemize
8000
 
8001
 
8002
@itemize @bullet
8003
@item void vst1_p8 (poly8_t *, poly8x8_t)
8004
@*@emph{Form of expected instruction(s):} @code{vst1.8 @{@var{d0}@}, [@var{r0}]}
8005
@end itemize
8006
 
8007
 
8008
@itemize @bullet
8009
@item void vst1q_u32 (uint32_t *, uint32x4_t)
8010
@*@emph{Form of expected instruction(s):} @code{vst1.32 @{@var{d0}, @var{d1}@}, [@var{r0}]}
8011
@end itemize
8012
 
8013
 
8014
@itemize @bullet
8015
@item void vst1q_u16 (uint16_t *, uint16x8_t)
8016
@*@emph{Form of expected instruction(s):} @code{vst1.16 @{@var{d0}, @var{d1}@}, [@var{r0}]}
8017
@end itemize
8018
 
8019
 
8020
@itemize @bullet
8021
@item void vst1q_u8 (uint8_t *, uint8x16_t)
8022
@*@emph{Form of expected instruction(s):} @code{vst1.8 @{@var{d0}, @var{d1}@}, [@var{r0}]}
8023
@end itemize
8024
 
8025
 
8026
@itemize @bullet
8027
@item void vst1q_s32 (int32_t *, int32x4_t)
8028
@*@emph{Form of expected instruction(s):} @code{vst1.32 @{@var{d0}, @var{d1}@}, [@var{r0}]}
8029
@end itemize
8030
 
8031
 
8032
@itemize @bullet
8033
@item void vst1q_s16 (int16_t *, int16x8_t)
8034
@*@emph{Form of expected instruction(s):} @code{vst1.16 @{@var{d0}, @var{d1}@}, [@var{r0}]}
8035
@end itemize
8036
 
8037
 
8038
@itemize @bullet
8039
@item void vst1q_s8 (int8_t *, int8x16_t)
8040
@*@emph{Form of expected instruction(s):} @code{vst1.8 @{@var{d0}, @var{d1}@}, [@var{r0}]}
8041
@end itemize
8042
 
8043
 
8044
@itemize @bullet
8045
@item void vst1q_u64 (uint64_t *, uint64x2_t)
8046
@*@emph{Form of expected instruction(s):} @code{vst1.64 @{@var{d0}, @var{d1}@}, [@var{r0}]}
8047
@end itemize
8048
 
8049
 
8050
@itemize @bullet
8051
@item void vst1q_s64 (int64_t *, int64x2_t)
8052
@*@emph{Form of expected instruction(s):} @code{vst1.64 @{@var{d0}, @var{d1}@}, [@var{r0}]}
8053
@end itemize
8054
 
8055
 
8056
@itemize @bullet
8057
@item void vst1q_f32 (float32_t *, float32x4_t)
8058
@*@emph{Form of expected instruction(s):} @code{vst1.32 @{@var{d0}, @var{d1}@}, [@var{r0}]}
8059
@end itemize
8060
 
8061
 
8062
@itemize @bullet
8063
@item void vst1q_p16 (poly16_t *, poly16x8_t)
8064
@*@emph{Form of expected instruction(s):} @code{vst1.16 @{@var{d0}, @var{d1}@}, [@var{r0}]}
8065
@end itemize
8066
 
8067
 
8068
@itemize @bullet
8069
@item void vst1q_p8 (poly8_t *, poly8x16_t)
8070
@*@emph{Form of expected instruction(s):} @code{vst1.8 @{@var{d0}, @var{d1}@}, [@var{r0}]}
8071
@end itemize
8072
 
8073
 
8074
@itemize @bullet
8075
@item void vst1_lane_u32 (uint32_t *, uint32x2_t, const int)
8076
@*@emph{Form of expected instruction(s):} @code{vst1.32 @{@var{d0}[@var{0}]@}, [@var{r0}]}
8077
@end itemize
8078
 
8079
 
8080
@itemize @bullet
8081
@item void vst1_lane_u16 (uint16_t *, uint16x4_t, const int)
8082
@*@emph{Form of expected instruction(s):} @code{vst1.16 @{@var{d0}[@var{0}]@}, [@var{r0}]}
8083
@end itemize
8084
 
8085
 
8086
@itemize @bullet
8087
@item void vst1_lane_u8 (uint8_t *, uint8x8_t, const int)
8088
@*@emph{Form of expected instruction(s):} @code{vst1.8 @{@var{d0}[@var{0}]@}, [@var{r0}]}
8089
@end itemize
8090
 
8091
 
8092
@itemize @bullet
8093
@item void vst1_lane_s32 (int32_t *, int32x2_t, const int)
8094
@*@emph{Form of expected instruction(s):} @code{vst1.32 @{@var{d0}[@var{0}]@}, [@var{r0}]}
8095
@end itemize
8096
 
8097
 
8098
@itemize @bullet
8099
@item void vst1_lane_s16 (int16_t *, int16x4_t, const int)
8100
@*@emph{Form of expected instruction(s):} @code{vst1.16 @{@var{d0}[@var{0}]@}, [@var{r0}]}
8101
@end itemize
8102
 
8103
 
8104
@itemize @bullet
8105
@item void vst1_lane_s8 (int8_t *, int8x8_t, const int)
8106
@*@emph{Form of expected instruction(s):} @code{vst1.8 @{@var{d0}[@var{0}]@}, [@var{r0}]}
8107
@end itemize
8108
 
8109
 
8110
@itemize @bullet
8111
@item void vst1_lane_f32 (float32_t *, float32x2_t, const int)
8112
@*@emph{Form of expected instruction(s):} @code{vst1.32 @{@var{d0}[@var{0}]@}, [@var{r0}]}
8113
@end itemize
8114
 
8115
 
8116
@itemize @bullet
8117
@item void vst1_lane_p16 (poly16_t *, poly16x4_t, const int)
8118
@*@emph{Form of expected instruction(s):} @code{vst1.16 @{@var{d0}[@var{0}]@}, [@var{r0}]}
8119
@end itemize
8120
 
8121
 
8122
@itemize @bullet
8123
@item void vst1_lane_p8 (poly8_t *, poly8x8_t, const int)
8124
@*@emph{Form of expected instruction(s):} @code{vst1.8 @{@var{d0}[@var{0}]@}, [@var{r0}]}
8125
@end itemize
8126
 
8127
 
8128
@itemize @bullet
8129
@item void vst1_lane_s64 (int64_t *, int64x1_t, const int)
8130
@*@emph{Form of expected instruction(s):} @code{vst1.64 @{@var{d0}@}, [@var{r0}]}
8131
@end itemize
8132
 
8133
 
8134
@itemize @bullet
8135
@item void vst1_lane_u64 (uint64_t *, uint64x1_t, const int)
8136
@*@emph{Form of expected instruction(s):} @code{vst1.64 @{@var{d0}@}, [@var{r0}]}
8137
@end itemize
8138
 
8139
 
8140
@itemize @bullet
8141
@item void vst1q_lane_u32 (uint32_t *, uint32x4_t, const int)
8142
@*@emph{Form of expected instruction(s):} @code{vst1.32 @{@var{d0}[@var{0}]@}, [@var{r0}]}
8143
@end itemize
8144
 
8145
 
8146
@itemize @bullet
8147
@item void vst1q_lane_u16 (uint16_t *, uint16x8_t, const int)
8148
@*@emph{Form of expected instruction(s):} @code{vst1.16 @{@var{d0}[@var{0}]@}, [@var{r0}]}
8149
@end itemize
8150
 
8151
 
8152
@itemize @bullet
8153
@item void vst1q_lane_u8 (uint8_t *, uint8x16_t, const int)
8154
@*@emph{Form of expected instruction(s):} @code{vst1.8 @{@var{d0}[@var{0}]@}, [@var{r0}]}
8155
@end itemize
8156
 
8157
 
8158
@itemize @bullet
8159
@item void vst1q_lane_s32 (int32_t *, int32x4_t, const int)
8160
@*@emph{Form of expected instruction(s):} @code{vst1.32 @{@var{d0}[@var{0}]@}, [@var{r0}]}
8161
@end itemize
8162
 
8163
 
8164
@itemize @bullet
8165
@item void vst1q_lane_s16 (int16_t *, int16x8_t, const int)
8166
@*@emph{Form of expected instruction(s):} @code{vst1.16 @{@var{d0}[@var{0}]@}, [@var{r0}]}
8167
@end itemize
8168
 
8169
 
8170
@itemize @bullet
8171
@item void vst1q_lane_s8 (int8_t *, int8x16_t, const int)
8172
@*@emph{Form of expected instruction(s):} @code{vst1.8 @{@var{d0}[@var{0}]@}, [@var{r0}]}
8173
@end itemize
8174
 
8175
 
8176
@itemize @bullet
8177
@item void vst1q_lane_f32 (float32_t *, float32x4_t, const int)
8178
@*@emph{Form of expected instruction(s):} @code{vst1.32 @{@var{d0}[@var{0}]@}, [@var{r0}]}
8179
@end itemize
8180
 
8181
 
8182
@itemize @bullet
8183
@item void vst1q_lane_p16 (poly16_t *, poly16x8_t, const int)
8184
@*@emph{Form of expected instruction(s):} @code{vst1.16 @{@var{d0}[@var{0}]@}, [@var{r0}]}
8185
@end itemize
8186
 
8187
 
8188
@itemize @bullet
8189
@item void vst1q_lane_p8 (poly8_t *, poly8x16_t, const int)
8190
@*@emph{Form of expected instruction(s):} @code{vst1.8 @{@var{d0}[@var{0}]@}, [@var{r0}]}
8191
@end itemize
8192
 
8193
 
8194
@itemize @bullet
8195
@item void vst1q_lane_s64 (int64_t *, int64x2_t, const int)
8196
@*@emph{Form of expected instruction(s):} @code{vst1.64 @{@var{d0}@}, [@var{r0}]}
8197
@end itemize
8198
 
8199
 
8200
@itemize @bullet
8201
@item void vst1q_lane_u64 (uint64_t *, uint64x2_t, const int)
8202
@*@emph{Form of expected instruction(s):} @code{vst1.64 @{@var{d0}@}, [@var{r0}]}
8203
@end itemize
8204
 
8205
 
8206
 
8207
 
8208
@subsubsection Element/structure loads, VLD2 variants
8209
 
8210
@itemize @bullet
8211
@item uint32x2x2_t vld2_u32 (const uint32_t *)
8212
@*@emph{Form of expected instruction(s):} @code{vld2.32 @{@var{d0}, @var{d1}@}, [@var{r0}]}
8213
@end itemize
8214
 
8215
 
8216
@itemize @bullet
8217
@item uint16x4x2_t vld2_u16 (const uint16_t *)
8218
@*@emph{Form of expected instruction(s):} @code{vld2.16 @{@var{d0}, @var{d1}@}, [@var{r0}]}
8219
@end itemize
8220
 
8221
 
8222
@itemize @bullet
8223
@item uint8x8x2_t vld2_u8 (const uint8_t *)
8224
@*@emph{Form of expected instruction(s):} @code{vld2.8 @{@var{d0}, @var{d1}@}, [@var{r0}]}
8225
@end itemize
8226
 
8227
 
8228
@itemize @bullet
8229
@item int32x2x2_t vld2_s32 (const int32_t *)
8230
@*@emph{Form of expected instruction(s):} @code{vld2.32 @{@var{d0}, @var{d1}@}, [@var{r0}]}
8231
@end itemize
8232
 
8233
 
8234
@itemize @bullet
8235
@item int16x4x2_t vld2_s16 (const int16_t *)
8236
@*@emph{Form of expected instruction(s):} @code{vld2.16 @{@var{d0}, @var{d1}@}, [@var{r0}]}
8237
@end itemize
8238
 
8239
 
8240
@itemize @bullet
8241
@item int8x8x2_t vld2_s8 (const int8_t *)
8242
@*@emph{Form of expected instruction(s):} @code{vld2.8 @{@var{d0}, @var{d1}@}, [@var{r0}]}
8243
@end itemize
8244
 
8245
 
8246
@itemize @bullet
8247
@item float32x2x2_t vld2_f32 (const float32_t *)
8248
@*@emph{Form of expected instruction(s):} @code{vld2.32 @{@var{d0}, @var{d1}@}, [@var{r0}]}
8249
@end itemize
8250
 
8251
 
8252
@itemize @bullet
8253
@item poly16x4x2_t vld2_p16 (const poly16_t *)
8254
@*@emph{Form of expected instruction(s):} @code{vld2.16 @{@var{d0}, @var{d1}@}, [@var{r0}]}
8255
@end itemize
8256
 
8257
 
8258
@itemize @bullet
8259
@item poly8x8x2_t vld2_p8 (const poly8_t *)
8260
@*@emph{Form of expected instruction(s):} @code{vld2.8 @{@var{d0}, @var{d1}@}, [@var{r0}]}
8261
@end itemize
8262
 
8263
 
8264
@itemize @bullet
8265
@item uint64x1x2_t vld2_u64 (const uint64_t *)
8266
@*@emph{Form of expected instruction(s):} @code{vld1.64 @{@var{d0}, @var{d1}@}, [@var{r0}]}
8267
@end itemize
8268
 
8269
 
8270
@itemize @bullet
8271
@item int64x1x2_t vld2_s64 (const int64_t *)
8272
@*@emph{Form of expected instruction(s):} @code{vld1.64 @{@var{d0}, @var{d1}@}, [@var{r0}]}
8273
@end itemize
8274
 
8275
 
8276
@itemize @bullet
8277
@item uint32x4x2_t vld2q_u32 (const uint32_t *)
8278
@*@emph{Form of expected instruction(s):} @code{vld2.32 @{@var{d0}, @var{d1}@}, [@var{r0}]}
8279
@end itemize
8280
 
8281
 
8282
@itemize @bullet
8283
@item uint16x8x2_t vld2q_u16 (const uint16_t *)
8284
@*@emph{Form of expected instruction(s):} @code{vld2.16 @{@var{d0}, @var{d1}@}, [@var{r0}]}
8285
@end itemize
8286
 
8287
 
8288
@itemize @bullet
8289
@item uint8x16x2_t vld2q_u8 (const uint8_t *)
8290
@*@emph{Form of expected instruction(s):} @code{vld2.8 @{@var{d0}, @var{d1}@}, [@var{r0}]}
8291
@end itemize
8292
 
8293
 
8294
@itemize @bullet
8295
@item int32x4x2_t vld2q_s32 (const int32_t *)
8296
@*@emph{Form of expected instruction(s):} @code{vld2.32 @{@var{d0}, @var{d1}@}, [@var{r0}]}
8297
@end itemize
8298
 
8299
 
8300
@itemize @bullet
8301
@item int16x8x2_t vld2q_s16 (const int16_t *)
8302
@*@emph{Form of expected instruction(s):} @code{vld2.16 @{@var{d0}, @var{d1}@}, [@var{r0}]}
8303
@end itemize
8304
 
8305
 
8306
@itemize @bullet
8307
@item int8x16x2_t vld2q_s8 (const int8_t *)
8308
@*@emph{Form of expected instruction(s):} @code{vld2.8 @{@var{d0}, @var{d1}@}, [@var{r0}]}
8309
@end itemize
8310
 
8311
 
8312
@itemize @bullet
8313
@item float32x4x2_t vld2q_f32 (const float32_t *)
8314
@*@emph{Form of expected instruction(s):} @code{vld2.32 @{@var{d0}, @var{d1}@}, [@var{r0}]}
8315
@end itemize
8316
 
8317
 
8318
@itemize @bullet
8319
@item poly16x8x2_t vld2q_p16 (const poly16_t *)
8320
@*@emph{Form of expected instruction(s):} @code{vld2.16 @{@var{d0}, @var{d1}@}, [@var{r0}]}
8321
@end itemize
8322
 
8323
 
8324
@itemize @bullet
8325
@item poly8x16x2_t vld2q_p8 (const poly8_t *)
8326
@*@emph{Form of expected instruction(s):} @code{vld2.8 @{@var{d0}, @var{d1}@}, [@var{r0}]}
8327
@end itemize
8328
 
8329
 
8330
@itemize @bullet
8331
@item uint32x2x2_t vld2_lane_u32 (const uint32_t *, uint32x2x2_t, const int)
8332
@*@emph{Form of expected instruction(s):} @code{vld2.32 @{@var{d0}[@var{0}], @var{d1}[@var{0}]@}, [@var{r0}]}
8333
@end itemize
8334
 
8335
 
8336
@itemize @bullet
8337
@item uint16x4x2_t vld2_lane_u16 (const uint16_t *, uint16x4x2_t, const int)
8338
@*@emph{Form of expected instruction(s):} @code{vld2.16 @{@var{d0}[@var{0}], @var{d1}[@var{0}]@}, [@var{r0}]}
8339
@end itemize
8340
 
8341
 
8342
@itemize @bullet
8343
@item uint8x8x2_t vld2_lane_u8 (const uint8_t *, uint8x8x2_t, const int)
8344
@*@emph{Form of expected instruction(s):} @code{vld2.8 @{@var{d0}[@var{0}], @var{d1}[@var{0}]@}, [@var{r0}]}
8345
@end itemize
8346
 
8347
 
8348
@itemize @bullet
8349
@item int32x2x2_t vld2_lane_s32 (const int32_t *, int32x2x2_t, const int)
8350
@*@emph{Form of expected instruction(s):} @code{vld2.32 @{@var{d0}[@var{0}], @var{d1}[@var{0}]@}, [@var{r0}]}
8351
@end itemize
8352
 
8353
 
8354
@itemize @bullet
8355
@item int16x4x2_t vld2_lane_s16 (const int16_t *, int16x4x2_t, const int)
8356
@*@emph{Form of expected instruction(s):} @code{vld2.16 @{@var{d0}[@var{0}], @var{d1}[@var{0}]@}, [@var{r0}]}
8357
@end itemize
8358
 
8359
 
8360
@itemize @bullet
8361
@item int8x8x2_t vld2_lane_s8 (const int8_t *, int8x8x2_t, const int)
8362
@*@emph{Form of expected instruction(s):} @code{vld2.8 @{@var{d0}[@var{0}], @var{d1}[@var{0}]@}, [@var{r0}]}
8363
@end itemize
8364
 
8365
 
8366
@itemize @bullet
8367
@item float32x2x2_t vld2_lane_f32 (const float32_t *, float32x2x2_t, const int)
8368
@*@emph{Form of expected instruction(s):} @code{vld2.32 @{@var{d0}[@var{0}], @var{d1}[@var{0}]@}, [@var{r0}]}
8369
@end itemize
8370
 
8371
 
8372
@itemize @bullet
8373
@item poly16x4x2_t vld2_lane_p16 (const poly16_t *, poly16x4x2_t, const int)
8374
@*@emph{Form of expected instruction(s):} @code{vld2.16 @{@var{d0}[@var{0}], @var{d1}[@var{0}]@}, [@var{r0}]}
8375
@end itemize
8376
 
8377
 
8378
@itemize @bullet
8379
@item poly8x8x2_t vld2_lane_p8 (const poly8_t *, poly8x8x2_t, const int)
8380
@*@emph{Form of expected instruction(s):} @code{vld2.8 @{@var{d0}[@var{0}], @var{d1}[@var{0}]@}, [@var{r0}]}
8381
@end itemize
8382
 
8383
 
8384
@itemize @bullet
8385
@item int32x4x2_t vld2q_lane_s32 (const int32_t *, int32x4x2_t, const int)
8386
@*@emph{Form of expected instruction(s):} @code{vld2.32 @{@var{d0}[@var{0}], @var{d1}[@var{0}]@}, [@var{r0}]}
8387
@end itemize
8388
 
8389
 
8390
@itemize @bullet
8391
@item int16x8x2_t vld2q_lane_s16 (const int16_t *, int16x8x2_t, const int)
8392
@*@emph{Form of expected instruction(s):} @code{vld2.16 @{@var{d0}[@var{0}], @var{d1}[@var{0}]@}, [@var{r0}]}
8393
@end itemize
8394
 
8395
 
8396
@itemize @bullet
8397
@item uint32x4x2_t vld2q_lane_u32 (const uint32_t *, uint32x4x2_t, const int)
8398
@*@emph{Form of expected instruction(s):} @code{vld2.32 @{@var{d0}[@var{0}], @var{d1}[@var{0}]@}, [@var{r0}]}
8399
@end itemize
8400
 
8401
 
8402
@itemize @bullet
8403
@item uint16x8x2_t vld2q_lane_u16 (const uint16_t *, uint16x8x2_t, const int)
8404
@*@emph{Form of expected instruction(s):} @code{vld2.16 @{@var{d0}[@var{0}], @var{d1}[@var{0}]@}, [@var{r0}]}
8405
@end itemize
8406
 
8407
 
8408
@itemize @bullet
8409
@item float32x4x2_t vld2q_lane_f32 (const float32_t *, float32x4x2_t, const int)
8410
@*@emph{Form of expected instruction(s):} @code{vld2.32 @{@var{d0}[@var{0}], @var{d1}[@var{0}]@}, [@var{r0}]}
8411
@end itemize
8412
 
8413
 
8414
@itemize @bullet
8415
@item poly16x8x2_t vld2q_lane_p16 (const poly16_t *, poly16x8x2_t, const int)
8416
@*@emph{Form of expected instruction(s):} @code{vld2.16 @{@var{d0}[@var{0}], @var{d1}[@var{0}]@}, [@var{r0}]}
8417
@end itemize
8418
 
8419
 
8420
@itemize @bullet
8421
@item uint32x2x2_t vld2_dup_u32 (const uint32_t *)
8422
@*@emph{Form of expected instruction(s):} @code{vld2.32 @{@var{d0}[], @var{d1}[]@}, [@var{r0}]}
8423
@end itemize
8424
 
8425
 
8426
@itemize @bullet
8427
@item uint16x4x2_t vld2_dup_u16 (const uint16_t *)
8428
@*@emph{Form of expected instruction(s):} @code{vld2.16 @{@var{d0}[], @var{d1}[]@}, [@var{r0}]}
8429
@end itemize
8430
 
8431
 
8432
@itemize @bullet
8433
@item uint8x8x2_t vld2_dup_u8 (const uint8_t *)
8434
@*@emph{Form of expected instruction(s):} @code{vld2.8 @{@var{d0}[], @var{d1}[]@}, [@var{r0}]}
8435
@end itemize
8436
 
8437
 
8438
@itemize @bullet
8439
@item int32x2x2_t vld2_dup_s32 (const int32_t *)
8440
@*@emph{Form of expected instruction(s):} @code{vld2.32 @{@var{d0}[], @var{d1}[]@}, [@var{r0}]}
8441
@end itemize
8442
 
8443
 
8444
@itemize @bullet
8445
@item int16x4x2_t vld2_dup_s16 (const int16_t *)
8446
@*@emph{Form of expected instruction(s):} @code{vld2.16 @{@var{d0}[], @var{d1}[]@}, [@var{r0}]}
8447
@end itemize
8448
 
8449
 
8450
@itemize @bullet
8451
@item int8x8x2_t vld2_dup_s8 (const int8_t *)
8452
@*@emph{Form of expected instruction(s):} @code{vld2.8 @{@var{d0}[], @var{d1}[]@}, [@var{r0}]}
8453
@end itemize
8454
 
8455
 
8456
@itemize @bullet
8457
@item float32x2x2_t vld2_dup_f32 (const float32_t *)
8458
@*@emph{Form of expected instruction(s):} @code{vld2.32 @{@var{d0}[], @var{d1}[]@}, [@var{r0}]}
8459
@end itemize
8460
 
8461
 
8462
@itemize @bullet
8463
@item poly16x4x2_t vld2_dup_p16 (const poly16_t *)
8464
@*@emph{Form of expected instruction(s):} @code{vld2.16 @{@var{d0}[], @var{d1}[]@}, [@var{r0}]}
8465
@end itemize
8466
 
8467
 
8468
@itemize @bullet
8469
@item poly8x8x2_t vld2_dup_p8 (const poly8_t *)
8470
@*@emph{Form of expected instruction(s):} @code{vld2.8 @{@var{d0}[], @var{d1}[]@}, [@var{r0}]}
8471
@end itemize
8472
 
8473
 
8474
@itemize @bullet
8475
@item uint64x1x2_t vld2_dup_u64 (const uint64_t *)
8476
@*@emph{Form of expected instruction(s):} @code{vld1.64 @{@var{d0}, @var{d1}@}, [@var{r0}]}
8477
@end itemize
8478
 
8479
 
8480
@itemize @bullet
8481
@item int64x1x2_t vld2_dup_s64 (const int64_t *)
8482
@*@emph{Form of expected instruction(s):} @code{vld1.64 @{@var{d0}, @var{d1}@}, [@var{r0}]}
8483
@end itemize
8484
 
8485
 
8486
 
8487
 
8488
@subsubsection Element/structure stores, VST2 variants
8489
 
8490
@itemize @bullet
8491
@item void vst2_u32 (uint32_t *, uint32x2x2_t)
8492
@*@emph{Form of expected instruction(s):} @code{vst2.32 @{@var{d0}, @var{d1}@}, [@var{r0}]}
8493
@end itemize
8494
 
8495
 
8496
@itemize @bullet
8497
@item void vst2_u16 (uint16_t *, uint16x4x2_t)
8498
@*@emph{Form of expected instruction(s):} @code{vst2.16 @{@var{d0}, @var{d1}@}, [@var{r0}]}
8499
@end itemize
8500
 
8501
 
8502
@itemize @bullet
8503
@item void vst2_u8 (uint8_t *, uint8x8x2_t)
8504
@*@emph{Form of expected instruction(s):} @code{vst2.8 @{@var{d0}, @var{d1}@}, [@var{r0}]}
8505
@end itemize
8506
 
8507
 
8508
@itemize @bullet
8509
@item void vst2_s32 (int32_t *, int32x2x2_t)
8510
@*@emph{Form of expected instruction(s):} @code{vst2.32 @{@var{d0}, @var{d1}@}, [@var{r0}]}
8511
@end itemize
8512
 
8513
 
8514
@itemize @bullet
8515
@item void vst2_s16 (int16_t *, int16x4x2_t)
8516
@*@emph{Form of expected instruction(s):} @code{vst2.16 @{@var{d0}, @var{d1}@}, [@var{r0}]}
8517
@end itemize
8518
 
8519
 
8520
@itemize @bullet
8521
@item void vst2_s8 (int8_t *, int8x8x2_t)
8522
@*@emph{Form of expected instruction(s):} @code{vst2.8 @{@var{d0}, @var{d1}@}, [@var{r0}]}
8523
@end itemize
8524
 
8525
 
8526
@itemize @bullet
8527
@item void vst2_f32 (float32_t *, float32x2x2_t)
8528
@*@emph{Form of expected instruction(s):} @code{vst2.32 @{@var{d0}, @var{d1}@}, [@var{r0}]}
8529
@end itemize
8530
 
8531
 
8532
@itemize @bullet
8533
@item void vst2_p16 (poly16_t *, poly16x4x2_t)
8534
@*@emph{Form of expected instruction(s):} @code{vst2.16 @{@var{d0}, @var{d1}@}, [@var{r0}]}
8535
@end itemize
8536
 
8537
 
8538
@itemize @bullet
8539
@item void vst2_p8 (poly8_t *, poly8x8x2_t)
8540
@*@emph{Form of expected instruction(s):} @code{vst2.8 @{@var{d0}, @var{d1}@}, [@var{r0}]}
8541
@end itemize
8542
 
8543
 
8544
@itemize @bullet
8545
@item void vst2_u64 (uint64_t *, uint64x1x2_t)
8546
@*@emph{Form of expected instruction(s):} @code{vst1.64 @{@var{d0}, @var{d1}@}, [@var{r0}]}
8547
@end itemize
8548
 
8549
 
8550
@itemize @bullet
8551
@item void vst2_s64 (int64_t *, int64x1x2_t)
8552
@*@emph{Form of expected instruction(s):} @code{vst1.64 @{@var{d0}, @var{d1}@}, [@var{r0}]}
8553
@end itemize
8554
 
8555
 
8556
@itemize @bullet
8557
@item void vst2q_u32 (uint32_t *, uint32x4x2_t)
8558
@*@emph{Form of expected instruction(s):} @code{vst2.32 @{@var{d0}, @var{d1}@}, [@var{r0}]}
8559
@end itemize
8560
 
8561
 
8562
@itemize @bullet
8563
@item void vst2q_u16 (uint16_t *, uint16x8x2_t)
8564
@*@emph{Form of expected instruction(s):} @code{vst2.16 @{@var{d0}, @var{d1}@}, [@var{r0}]}
8565
@end itemize
8566
 
8567
 
8568
@itemize @bullet
8569
@item void vst2q_u8 (uint8_t *, uint8x16x2_t)
8570
@*@emph{Form of expected instruction(s):} @code{vst2.8 @{@var{d0}, @var{d1}@}, [@var{r0}]}
8571
@end itemize
8572
 
8573
 
8574
@itemize @bullet
8575
@item void vst2q_s32 (int32_t *, int32x4x2_t)
8576
@*@emph{Form of expected instruction(s):} @code{vst2.32 @{@var{d0}, @var{d1}@}, [@var{r0}]}
8577
@end itemize
8578
 
8579
 
8580
@itemize @bullet
8581
@item void vst2q_s16 (int16_t *, int16x8x2_t)
8582
@*@emph{Form of expected instruction(s):} @code{vst2.16 @{@var{d0}, @var{d1}@}, [@var{r0}]}
8583
@end itemize
8584
 
8585
 
8586
@itemize @bullet
8587
@item void vst2q_s8 (int8_t *, int8x16x2_t)
8588
@*@emph{Form of expected instruction(s):} @code{vst2.8 @{@var{d0}, @var{d1}@}, [@var{r0}]}
8589
@end itemize
8590
 
8591
 
8592
@itemize @bullet
8593
@item void vst2q_f32 (float32_t *, float32x4x2_t)
8594
@*@emph{Form of expected instruction(s):} @code{vst2.32 @{@var{d0}, @var{d1}@}, [@var{r0}]}
8595
@end itemize
8596
 
8597
 
8598
@itemize @bullet
8599
@item void vst2q_p16 (poly16_t *, poly16x8x2_t)
8600
@*@emph{Form of expected instruction(s):} @code{vst2.16 @{@var{d0}, @var{d1}@}, [@var{r0}]}
8601
@end itemize
8602
 
8603
 
8604
@itemize @bullet
8605
@item void vst2q_p8 (poly8_t *, poly8x16x2_t)
8606
@*@emph{Form of expected instruction(s):} @code{vst2.8 @{@var{d0}, @var{d1}@}, [@var{r0}]}
8607
@end itemize
8608
 
8609
 
8610
@itemize @bullet
8611
@item void vst2_lane_u32 (uint32_t *, uint32x2x2_t, const int)
8612
@*@emph{Form of expected instruction(s):} @code{vst2.32 @{@var{d0}[@var{0}], @var{d1}[@var{0}]@}, [@var{r0}]}
8613
@end itemize
8614
 
8615
 
8616
@itemize @bullet
8617
@item void vst2_lane_u16 (uint16_t *, uint16x4x2_t, const int)
8618
@*@emph{Form of expected instruction(s):} @code{vst2.16 @{@var{d0}[@var{0}], @var{d1}[@var{0}]@}, [@var{r0}]}
8619
@end itemize
8620
 
8621
 
8622
@itemize @bullet
8623
@item void vst2_lane_u8 (uint8_t *, uint8x8x2_t, const int)
8624
@*@emph{Form of expected instruction(s):} @code{vst2.8 @{@var{d0}[@var{0}], @var{d1}[@var{0}]@}, [@var{r0}]}
8625
@end itemize
8626
 
8627
 
8628
@itemize @bullet
8629
@item void vst2_lane_s32 (int32_t *, int32x2x2_t, const int)
8630
@*@emph{Form of expected instruction(s):} @code{vst2.32 @{@var{d0}[@var{0}], @var{d1}[@var{0}]@}, [@var{r0}]}
8631
@end itemize
8632
 
8633
 
8634
@itemize @bullet
8635
@item void vst2_lane_s16 (int16_t *, int16x4x2_t, const int)
8636
@*@emph{Form of expected instruction(s):} @code{vst2.16 @{@var{d0}[@var{0}], @var{d1}[@var{0}]@}, [@var{r0}]}
8637
@end itemize
8638
 
8639
 
8640
@itemize @bullet
8641
@item void vst2_lane_s8 (int8_t *, int8x8x2_t, const int)
8642
@*@emph{Form of expected instruction(s):} @code{vst2.8 @{@var{d0}[@var{0}], @var{d1}[@var{0}]@}, [@var{r0}]}
8643
@end itemize
8644
 
8645
 
8646
@itemize @bullet
8647
@item void vst2_lane_f32 (float32_t *, float32x2x2_t, const int)
8648
@*@emph{Form of expected instruction(s):} @code{vst2.32 @{@var{d0}[@var{0}], @var{d1}[@var{0}]@}, [@var{r0}]}
8649
@end itemize
8650
 
8651
 
8652
@itemize @bullet
8653
@item void vst2_lane_p16 (poly16_t *, poly16x4x2_t, const int)
8654
@*@emph{Form of expected instruction(s):} @code{vst2.16 @{@var{d0}[@var{0}], @var{d1}[@var{0}]@}, [@var{r0}]}
8655
@end itemize
8656
 
8657
 
8658
@itemize @bullet
8659
@item void vst2_lane_p8 (poly8_t *, poly8x8x2_t, const int)
8660
@*@emph{Form of expected instruction(s):} @code{vst2.8 @{@var{d0}[@var{0}], @var{d1}[@var{0}]@}, [@var{r0}]}
8661
@end itemize
8662
 
8663
 
8664
@itemize @bullet
8665
@item void vst2q_lane_s32 (int32_t *, int32x4x2_t, const int)
8666
@*@emph{Form of expected instruction(s):} @code{vst2.32 @{@var{d0}[@var{0}], @var{d1}[@var{0}]@}, [@var{r0}]}
8667
@end itemize
8668
 
8669
 
8670
@itemize @bullet
8671
@item void vst2q_lane_s16 (int16_t *, int16x8x2_t, const int)
8672
@*@emph{Form of expected instruction(s):} @code{vst2.16 @{@var{d0}[@var{0}], @var{d1}[@var{0}]@}, [@var{r0}]}
8673
@end itemize
8674
 
8675
 
8676
@itemize @bullet
8677
@item void vst2q_lane_u32 (uint32_t *, uint32x4x2_t, const int)
8678
@*@emph{Form of expected instruction(s):} @code{vst2.32 @{@var{d0}[@var{0}], @var{d1}[@var{0}]@}, [@var{r0}]}
8679
@end itemize
8680
 
8681
 
8682
@itemize @bullet
8683
@item void vst2q_lane_u16 (uint16_t *, uint16x8x2_t, const int)
8684
@*@emph{Form of expected instruction(s):} @code{vst2.16 @{@var{d0}[@var{0}], @var{d1}[@var{0}]@}, [@var{r0}]}
8685
@end itemize
8686
 
8687
 
8688
@itemize @bullet
8689
@item void vst2q_lane_f32 (float32_t *, float32x4x2_t, const int)
8690
@*@emph{Form of expected instruction(s):} @code{vst2.32 @{@var{d0}[@var{0}], @var{d1}[@var{0}]@}, [@var{r0}]}
8691
@end itemize
8692
 
8693
 
8694
@itemize @bullet
8695
@item void vst2q_lane_p16 (poly16_t *, poly16x8x2_t, const int)
8696
@*@emph{Form of expected instruction(s):} @code{vst2.16 @{@var{d0}[@var{0}], @var{d1}[@var{0}]@}, [@var{r0}]}
8697
@end itemize
8698
 
8699
 
8700
 
8701
 
8702
@subsubsection Element/structure loads, VLD3 variants
8703
 
8704
@itemize @bullet
8705
@item uint32x2x3_t vld3_u32 (const uint32_t *)
8706
@*@emph{Form of expected instruction(s):} @code{vld3.32 @{@var{d0}, @var{d1}, @var{d2}@}, [@var{r0}]}
8707
@end itemize
8708
 
8709
 
8710
@itemize @bullet
8711
@item uint16x4x3_t vld3_u16 (const uint16_t *)
8712
@*@emph{Form of expected instruction(s):} @code{vld3.16 @{@var{d0}, @var{d1}, @var{d2}@}, [@var{r0}]}
8713
@end itemize
8714
 
8715
 
8716
@itemize @bullet
8717
@item uint8x8x3_t vld3_u8 (const uint8_t *)
8718
@*@emph{Form of expected instruction(s):} @code{vld3.8 @{@var{d0}, @var{d1}, @var{d2}@}, [@var{r0}]}
8719
@end itemize
8720
 
8721
 
8722
@itemize @bullet
8723
@item int32x2x3_t vld3_s32 (const int32_t *)
8724
@*@emph{Form of expected instruction(s):} @code{vld3.32 @{@var{d0}, @var{d1}, @var{d2}@}, [@var{r0}]}
8725
@end itemize
8726
 
8727
 
8728
@itemize @bullet
8729
@item int16x4x3_t vld3_s16 (const int16_t *)
8730
@*@emph{Form of expected instruction(s):} @code{vld3.16 @{@var{d0}, @var{d1}, @var{d2}@}, [@var{r0}]}
8731
@end itemize
8732
 
8733
 
8734
@itemize @bullet
8735
@item int8x8x3_t vld3_s8 (const int8_t *)
8736
@*@emph{Form of expected instruction(s):} @code{vld3.8 @{@var{d0}, @var{d1}, @var{d2}@}, [@var{r0}]}
8737
@end itemize
8738
 
8739
 
8740
@itemize @bullet
8741
@item float32x2x3_t vld3_f32 (const float32_t *)
8742
@*@emph{Form of expected instruction(s):} @code{vld3.32 @{@var{d0}, @var{d1}, @var{d2}@}, [@var{r0}]}
8743
@end itemize
8744
 
8745
 
8746
@itemize @bullet
8747
@item poly16x4x3_t vld3_p16 (const poly16_t *)
8748
@*@emph{Form of expected instruction(s):} @code{vld3.16 @{@var{d0}, @var{d1}, @var{d2}@}, [@var{r0}]}
8749
@end itemize
8750
 
8751
 
8752
@itemize @bullet
8753
@item poly8x8x3_t vld3_p8 (const poly8_t *)
8754
@*@emph{Form of expected instruction(s):} @code{vld3.8 @{@var{d0}, @var{d1}, @var{d2}@}, [@var{r0}]}
8755
@end itemize
8756
 
8757
 
8758
@itemize @bullet
8759
@item uint64x1x3_t vld3_u64 (const uint64_t *)
8760
@*@emph{Form of expected instruction(s):} @code{vld1.64 @{@var{d0}, @var{d1}, @var{d2}@}, [@var{r0}]}
8761
@end itemize
8762
 
8763
 
8764
@itemize @bullet
8765
@item int64x1x3_t vld3_s64 (const int64_t *)
8766
@*@emph{Form of expected instruction(s):} @code{vld1.64 @{@var{d0}, @var{d1}, @var{d2}@}, [@var{r0}]}
8767
@end itemize
8768
 
8769
 
8770
@itemize @bullet
8771
@item uint32x4x3_t vld3q_u32 (const uint32_t *)
8772
@*@emph{Form of expected instruction(s):} @code{vld3.32 @{@var{d0}, @var{d1}, @var{d2}@}, [@var{r0}]}
8773
@end itemize
8774
 
8775
 
8776
@itemize @bullet
8777
@item uint16x8x3_t vld3q_u16 (const uint16_t *)
8778
@*@emph{Form of expected instruction(s):} @code{vld3.16 @{@var{d0}, @var{d1}, @var{d2}@}, [@var{r0}]}
8779
@end itemize
8780
 
8781
 
8782
@itemize @bullet
8783
@item uint8x16x3_t vld3q_u8 (const uint8_t *)
8784
@*@emph{Form of expected instruction(s):} @code{vld3.8 @{@var{d0}, @var{d1}, @var{d2}@}, [@var{r0}]}
8785
@end itemize
8786
 
8787
 
8788
@itemize @bullet
8789
@item int32x4x3_t vld3q_s32 (const int32_t *)
8790
@*@emph{Form of expected instruction(s):} @code{vld3.32 @{@var{d0}, @var{d1}, @var{d2}@}, [@var{r0}]}
8791
@end itemize
8792
 
8793
 
8794
@itemize @bullet
8795
@item int16x8x3_t vld3q_s16 (const int16_t *)
8796
@*@emph{Form of expected instruction(s):} @code{vld3.16 @{@var{d0}, @var{d1}, @var{d2}@}, [@var{r0}]}
8797
@end itemize
8798
 
8799
 
8800
@itemize @bullet
8801
@item int8x16x3_t vld3q_s8 (const int8_t *)
8802
@*@emph{Form of expected instruction(s):} @code{vld3.8 @{@var{d0}, @var{d1}, @var{d2}@}, [@var{r0}]}
8803
@end itemize
8804
 
8805
 
8806
@itemize @bullet
8807
@item float32x4x3_t vld3q_f32 (const float32_t *)
8808
@*@emph{Form of expected instruction(s):} @code{vld3.32 @{@var{d0}, @var{d1}, @var{d2}@}, [@var{r0}]}
8809
@end itemize
8810
 
8811
 
8812
@itemize @bullet
8813
@item poly16x8x3_t vld3q_p16 (const poly16_t *)
8814
@*@emph{Form of expected instruction(s):} @code{vld3.16 @{@var{d0}, @var{d1}, @var{d2}@}, [@var{r0}]}
8815
@end itemize
8816
 
8817
 
8818
@itemize @bullet
8819
@item poly8x16x3_t vld3q_p8 (const poly8_t *)
8820
@*@emph{Form of expected instruction(s):} @code{vld3.8 @{@var{d0}, @var{d1}, @var{d2}@}, [@var{r0}]}
8821
@end itemize
8822
 
8823
 
8824
@itemize @bullet
8825
@item uint32x2x3_t vld3_lane_u32 (const uint32_t *, uint32x2x3_t, const int)
8826
@*@emph{Form of expected instruction(s):} @code{vld3.32 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}]@}, [@var{r0}]}
8827
@end itemize
8828
 
8829
 
8830
@itemize @bullet
8831
@item uint16x4x3_t vld3_lane_u16 (const uint16_t *, uint16x4x3_t, const int)
8832
@*@emph{Form of expected instruction(s):} @code{vld3.16 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}]@}, [@var{r0}]}
8833
@end itemize
8834
 
8835
 
8836
@itemize @bullet
8837
@item uint8x8x3_t vld3_lane_u8 (const uint8_t *, uint8x8x3_t, const int)
8838
@*@emph{Form of expected instruction(s):} @code{vld3.8 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}]@}, [@var{r0}]}
8839
@end itemize
8840
 
8841
 
8842
@itemize @bullet
8843
@item int32x2x3_t vld3_lane_s32 (const int32_t *, int32x2x3_t, const int)
8844
@*@emph{Form of expected instruction(s):} @code{vld3.32 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}]@}, [@var{r0}]}
8845
@end itemize
8846
 
8847
 
8848
@itemize @bullet
8849
@item int16x4x3_t vld3_lane_s16 (const int16_t *, int16x4x3_t, const int)
8850
@*@emph{Form of expected instruction(s):} @code{vld3.16 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}]@}, [@var{r0}]}
8851
@end itemize
8852
 
8853
 
8854
@itemize @bullet
8855
@item int8x8x3_t vld3_lane_s8 (const int8_t *, int8x8x3_t, const int)
8856
@*@emph{Form of expected instruction(s):} @code{vld3.8 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}]@}, [@var{r0}]}
8857
@end itemize
8858
 
8859
 
8860
@itemize @bullet
8861
@item float32x2x3_t vld3_lane_f32 (const float32_t *, float32x2x3_t, const int)
8862
@*@emph{Form of expected instruction(s):} @code{vld3.32 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}]@}, [@var{r0}]}
8863
@end itemize
8864
 
8865
 
8866
@itemize @bullet
8867
@item poly16x4x3_t vld3_lane_p16 (const poly16_t *, poly16x4x3_t, const int)
8868
@*@emph{Form of expected instruction(s):} @code{vld3.16 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}]@}, [@var{r0}]}
8869
@end itemize
8870
 
8871
 
8872
@itemize @bullet
8873
@item poly8x8x3_t vld3_lane_p8 (const poly8_t *, poly8x8x3_t, const int)
8874
@*@emph{Form of expected instruction(s):} @code{vld3.8 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}]@}, [@var{r0}]}
8875
@end itemize
8876
 
8877
 
8878
@itemize @bullet
8879
@item int32x4x3_t vld3q_lane_s32 (const int32_t *, int32x4x3_t, const int)
8880
@*@emph{Form of expected instruction(s):} @code{vld3.32 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}]@}, [@var{r0}]}
8881
@end itemize
8882
 
8883
 
8884
@itemize @bullet
8885
@item int16x8x3_t vld3q_lane_s16 (const int16_t *, int16x8x3_t, const int)
8886
@*@emph{Form of expected instruction(s):} @code{vld3.16 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}]@}, [@var{r0}]}
8887
@end itemize
8888
 
8889
 
8890
@itemize @bullet
8891
@item uint32x4x3_t vld3q_lane_u32 (const uint32_t *, uint32x4x3_t, const int)
8892
@*@emph{Form of expected instruction(s):} @code{vld3.32 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}]@}, [@var{r0}]}
8893
@end itemize
8894
 
8895
 
8896
@itemize @bullet
8897
@item uint16x8x3_t vld3q_lane_u16 (const uint16_t *, uint16x8x3_t, const int)
8898
@*@emph{Form of expected instruction(s):} @code{vld3.16 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}]@}, [@var{r0}]}
8899
@end itemize
8900
 
8901
 
8902
@itemize @bullet
8903
@item float32x4x3_t vld3q_lane_f32 (const float32_t *, float32x4x3_t, const int)
8904
@*@emph{Form of expected instruction(s):} @code{vld3.32 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}]@}, [@var{r0}]}
8905
@end itemize
8906
 
8907
 
8908
@itemize @bullet
8909
@item poly16x8x3_t vld3q_lane_p16 (const poly16_t *, poly16x8x3_t, const int)
8910
@*@emph{Form of expected instruction(s):} @code{vld3.16 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}]@}, [@var{r0}]}
8911
@end itemize
8912
 
8913
 
8914
@itemize @bullet
8915
@item uint32x2x3_t vld3_dup_u32 (const uint32_t *)
8916
@*@emph{Form of expected instruction(s):} @code{vld3.32 @{@var{d0}[], @var{d1}[], @var{d2}[]@}, [@var{r0}]}
8917
@end itemize
8918
 
8919
 
8920
@itemize @bullet
8921
@item uint16x4x3_t vld3_dup_u16 (const uint16_t *)
8922
@*@emph{Form of expected instruction(s):} @code{vld3.16 @{@var{d0}[], @var{d1}[], @var{d2}[]@}, [@var{r0}]}
8923
@end itemize
8924
 
8925
 
8926
@itemize @bullet
8927
@item uint8x8x3_t vld3_dup_u8 (const uint8_t *)
8928
@*@emph{Form of expected instruction(s):} @code{vld3.8 @{@var{d0}[], @var{d1}[], @var{d2}[]@}, [@var{r0}]}
8929
@end itemize
8930
 
8931
 
8932
@itemize @bullet
8933
@item int32x2x3_t vld3_dup_s32 (const int32_t *)
8934
@*@emph{Form of expected instruction(s):} @code{vld3.32 @{@var{d0}[], @var{d1}[], @var{d2}[]@}, [@var{r0}]}
8935
@end itemize
8936
 
8937
 
8938
@itemize @bullet
8939
@item int16x4x3_t vld3_dup_s16 (const int16_t *)
8940
@*@emph{Form of expected instruction(s):} @code{vld3.16 @{@var{d0}[], @var{d1}[], @var{d2}[]@}, [@var{r0}]}
8941
@end itemize
8942
 
8943
 
8944
@itemize @bullet
8945
@item int8x8x3_t vld3_dup_s8 (const int8_t *)
8946
@*@emph{Form of expected instruction(s):} @code{vld3.8 @{@var{d0}[], @var{d1}[], @var{d2}[]@}, [@var{r0}]}
8947
@end itemize
8948
 
8949
 
8950
@itemize @bullet
8951
@item float32x2x3_t vld3_dup_f32 (const float32_t *)
8952
@*@emph{Form of expected instruction(s):} @code{vld3.32 @{@var{d0}[], @var{d1}[], @var{d2}[]@}, [@var{r0}]}
8953
@end itemize
8954
 
8955
 
8956
@itemize @bullet
8957
@item poly16x4x3_t vld3_dup_p16 (const poly16_t *)
8958
@*@emph{Form of expected instruction(s):} @code{vld3.16 @{@var{d0}[], @var{d1}[], @var{d2}[]@}, [@var{r0}]}
8959
@end itemize
8960
 
8961
 
8962
@itemize @bullet
8963
@item poly8x8x3_t vld3_dup_p8 (const poly8_t *)
8964
@*@emph{Form of expected instruction(s):} @code{vld3.8 @{@var{d0}[], @var{d1}[], @var{d2}[]@}, [@var{r0}]}
8965
@end itemize
8966
 
8967
 
8968
@itemize @bullet
8969
@item uint64x1x3_t vld3_dup_u64 (const uint64_t *)
8970
@*@emph{Form of expected instruction(s):} @code{vld1.64 @{@var{d0}, @var{d1}, @var{d2}@}, [@var{r0}]}
8971
@end itemize
8972
 
8973
 
8974
@itemize @bullet
8975
@item int64x1x3_t vld3_dup_s64 (const int64_t *)
8976
@*@emph{Form of expected instruction(s):} @code{vld1.64 @{@var{d0}, @var{d1}, @var{d2}@}, [@var{r0}]}
8977
@end itemize
8978
 
8979
 
8980
 
8981
 
8982
@subsubsection Element/structure stores, VST3 variants
8983
 
8984
@itemize @bullet
8985
@item void vst3_u32 (uint32_t *, uint32x2x3_t)
8986
@*@emph{Form of expected instruction(s):} @code{vst3.32 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
8987
@end itemize
8988
 
8989
 
8990
@itemize @bullet
8991
@item void vst3_u16 (uint16_t *, uint16x4x3_t)
8992
@*@emph{Form of expected instruction(s):} @code{vst3.16 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
8993
@end itemize
8994
 
8995
 
8996
@itemize @bullet
8997
@item void vst3_u8 (uint8_t *, uint8x8x3_t)
8998
@*@emph{Form of expected instruction(s):} @code{vst3.8 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
8999
@end itemize
9000
 
9001
 
9002
@itemize @bullet
9003
@item void vst3_s32 (int32_t *, int32x2x3_t)
9004
@*@emph{Form of expected instruction(s):} @code{vst3.32 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
9005
@end itemize
9006
 
9007
 
9008
@itemize @bullet
9009
@item void vst3_s16 (int16_t *, int16x4x3_t)
9010
@*@emph{Form of expected instruction(s):} @code{vst3.16 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
9011
@end itemize
9012
 
9013
 
9014
@itemize @bullet
9015
@item void vst3_s8 (int8_t *, int8x8x3_t)
9016
@*@emph{Form of expected instruction(s):} @code{vst3.8 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
9017
@end itemize
9018
 
9019
 
9020
@itemize @bullet
9021
@item void vst3_f32 (float32_t *, float32x2x3_t)
9022
@*@emph{Form of expected instruction(s):} @code{vst3.32 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
9023
@end itemize
9024
 
9025
 
9026
@itemize @bullet
9027
@item void vst3_p16 (poly16_t *, poly16x4x3_t)
9028
@*@emph{Form of expected instruction(s):} @code{vst3.16 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
9029
@end itemize
9030
 
9031
 
9032
@itemize @bullet
9033
@item void vst3_p8 (poly8_t *, poly8x8x3_t)
9034
@*@emph{Form of expected instruction(s):} @code{vst3.8 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
9035
@end itemize
9036
 
9037
 
9038
@itemize @bullet
9039
@item void vst3_u64 (uint64_t *, uint64x1x3_t)
9040
@*@emph{Form of expected instruction(s):} @code{vst1.64 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
9041
@end itemize
9042
 
9043
 
9044
@itemize @bullet
9045
@item void vst3_s64 (int64_t *, int64x1x3_t)
9046
@*@emph{Form of expected instruction(s):} @code{vst1.64 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
9047
@end itemize
9048
 
9049
 
9050
@itemize @bullet
9051
@item void vst3q_u32 (uint32_t *, uint32x4x3_t)
9052
@*@emph{Form of expected instruction(s):} @code{vst3.32 @{@var{d0}, @var{d1}, @var{d2}@}, [@var{r0}]}
9053
@end itemize
9054
 
9055
 
9056
@itemize @bullet
9057
@item void vst3q_u16 (uint16_t *, uint16x8x3_t)
9058
@*@emph{Form of expected instruction(s):} @code{vst3.16 @{@var{d0}, @var{d1}, @var{d2}@}, [@var{r0}]}
9059
@end itemize
9060
 
9061
 
9062
@itemize @bullet
9063
@item void vst3q_u8 (uint8_t *, uint8x16x3_t)
9064
@*@emph{Form of expected instruction(s):} @code{vst3.8 @{@var{d0}, @var{d1}, @var{d2}@}, [@var{r0}]}
9065
@end itemize
9066
 
9067
 
9068
@itemize @bullet
9069
@item void vst3q_s32 (int32_t *, int32x4x3_t)
9070
@*@emph{Form of expected instruction(s):} @code{vst3.32 @{@var{d0}, @var{d1}, @var{d2}@}, [@var{r0}]}
9071
@end itemize
9072
 
9073
 
9074
@itemize @bullet
9075
@item void vst3q_s16 (int16_t *, int16x8x3_t)
9076
@*@emph{Form of expected instruction(s):} @code{vst3.16 @{@var{d0}, @var{d1}, @var{d2}@}, [@var{r0}]}
9077
@end itemize
9078
 
9079
 
9080
@itemize @bullet
9081
@item void vst3q_s8 (int8_t *, int8x16x3_t)
9082
@*@emph{Form of expected instruction(s):} @code{vst3.8 @{@var{d0}, @var{d1}, @var{d2}@}, [@var{r0}]}
9083
@end itemize
9084
 
9085
 
9086
@itemize @bullet
9087
@item void vst3q_f32 (float32_t *, float32x4x3_t)
9088
@*@emph{Form of expected instruction(s):} @code{vst3.32 @{@var{d0}, @var{d1}, @var{d2}@}, [@var{r0}]}
9089
@end itemize
9090
 
9091
 
9092
@itemize @bullet
9093
@item void vst3q_p16 (poly16_t *, poly16x8x3_t)
9094
@*@emph{Form of expected instruction(s):} @code{vst3.16 @{@var{d0}, @var{d1}, @var{d2}@}, [@var{r0}]}
9095
@end itemize
9096
 
9097
 
9098
@itemize @bullet
9099
@item void vst3q_p8 (poly8_t *, poly8x16x3_t)
9100
@*@emph{Form of expected instruction(s):} @code{vst3.8 @{@var{d0}, @var{d1}, @var{d2}@}, [@var{r0}]}
9101
@end itemize
9102
 
9103
 
9104
@itemize @bullet
9105
@item void vst3_lane_u32 (uint32_t *, uint32x2x3_t, const int)
9106
@*@emph{Form of expected instruction(s):} @code{vst3.32 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}]@}, [@var{r0}]}
9107
@end itemize
9108
 
9109
 
9110
@itemize @bullet
9111
@item void vst3_lane_u16 (uint16_t *, uint16x4x3_t, const int)
9112
@*@emph{Form of expected instruction(s):} @code{vst3.16 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}]@}, [@var{r0}]}
9113
@end itemize
9114
 
9115
 
9116
@itemize @bullet
9117
@item void vst3_lane_u8 (uint8_t *, uint8x8x3_t, const int)
9118
@*@emph{Form of expected instruction(s):} @code{vst3.8 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}]@}, [@var{r0}]}
9119
@end itemize
9120
 
9121
 
9122
@itemize @bullet
9123
@item void vst3_lane_s32 (int32_t *, int32x2x3_t, const int)
9124
@*@emph{Form of expected instruction(s):} @code{vst3.32 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}]@}, [@var{r0}]}
9125
@end itemize
9126
 
9127
 
9128
@itemize @bullet
9129
@item void vst3_lane_s16 (int16_t *, int16x4x3_t, const int)
9130
@*@emph{Form of expected instruction(s):} @code{vst3.16 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}]@}, [@var{r0}]}
9131
@end itemize
9132
 
9133
 
9134
@itemize @bullet
9135
@item void vst3_lane_s8 (int8_t *, int8x8x3_t, const int)
9136
@*@emph{Form of expected instruction(s):} @code{vst3.8 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}]@}, [@var{r0}]}
9137
@end itemize
9138
 
9139
 
9140
@itemize @bullet
9141
@item void vst3_lane_f32 (float32_t *, float32x2x3_t, const int)
9142
@*@emph{Form of expected instruction(s):} @code{vst3.32 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}]@}, [@var{r0}]}
9143
@end itemize
9144
 
9145
 
9146
@itemize @bullet
9147
@item void vst3_lane_p16 (poly16_t *, poly16x4x3_t, const int)
9148
@*@emph{Form of expected instruction(s):} @code{vst3.16 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}]@}, [@var{r0}]}
9149
@end itemize
9150
 
9151
 
9152
@itemize @bullet
9153
@item void vst3_lane_p8 (poly8_t *, poly8x8x3_t, const int)
9154
@*@emph{Form of expected instruction(s):} @code{vst3.8 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}]@}, [@var{r0}]}
9155
@end itemize
9156
 
9157
 
9158
@itemize @bullet
9159
@item void vst3q_lane_s32 (int32_t *, int32x4x3_t, const int)
9160
@*@emph{Form of expected instruction(s):} @code{vst3.32 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}]@}, [@var{r0}]}
9161
@end itemize
9162
 
9163
 
9164
@itemize @bullet
9165
@item void vst3q_lane_s16 (int16_t *, int16x8x3_t, const int)
9166
@*@emph{Form of expected instruction(s):} @code{vst3.16 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}]@}, [@var{r0}]}
9167
@end itemize
9168
 
9169
 
9170
@itemize @bullet
9171
@item void vst3q_lane_u32 (uint32_t *, uint32x4x3_t, const int)
9172
@*@emph{Form of expected instruction(s):} @code{vst3.32 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}]@}, [@var{r0}]}
9173
@end itemize
9174
 
9175
 
9176
@itemize @bullet
9177
@item void vst3q_lane_u16 (uint16_t *, uint16x8x3_t, const int)
9178
@*@emph{Form of expected instruction(s):} @code{vst3.16 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}]@}, [@var{r0}]}
9179
@end itemize
9180
 
9181
 
9182
@itemize @bullet
9183
@item void vst3q_lane_f32 (float32_t *, float32x4x3_t, const int)
9184
@*@emph{Form of expected instruction(s):} @code{vst3.32 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}]@}, [@var{r0}]}
9185
@end itemize
9186
 
9187
 
9188
@itemize @bullet
9189
@item void vst3q_lane_p16 (poly16_t *, poly16x8x3_t, const int)
9190
@*@emph{Form of expected instruction(s):} @code{vst3.16 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}]@}, [@var{r0}]}
9191
@end itemize
9192
 
9193
 
9194
 
9195
 
9196
@subsubsection Element/structure loads, VLD4 variants
9197
 
9198
@itemize @bullet
9199
@item uint32x2x4_t vld4_u32 (const uint32_t *)
9200
@*@emph{Form of expected instruction(s):} @code{vld4.32 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
9201
@end itemize
9202
 
9203
 
9204
@itemize @bullet
9205
@item uint16x4x4_t vld4_u16 (const uint16_t *)
9206
@*@emph{Form of expected instruction(s):} @code{vld4.16 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
9207
@end itemize
9208
 
9209
 
9210
@itemize @bullet
9211
@item uint8x8x4_t vld4_u8 (const uint8_t *)
9212
@*@emph{Form of expected instruction(s):} @code{vld4.8 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
9213
@end itemize
9214
 
9215
 
9216
@itemize @bullet
9217
@item int32x2x4_t vld4_s32 (const int32_t *)
9218
@*@emph{Form of expected instruction(s):} @code{vld4.32 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
9219
@end itemize
9220
 
9221
 
9222
@itemize @bullet
9223
@item int16x4x4_t vld4_s16 (const int16_t *)
9224
@*@emph{Form of expected instruction(s):} @code{vld4.16 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
9225
@end itemize
9226
 
9227
 
9228
@itemize @bullet
9229
@item int8x8x4_t vld4_s8 (const int8_t *)
9230
@*@emph{Form of expected instruction(s):} @code{vld4.8 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
9231
@end itemize
9232
 
9233
 
9234
@itemize @bullet
9235
@item float32x2x4_t vld4_f32 (const float32_t *)
9236
@*@emph{Form of expected instruction(s):} @code{vld4.32 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
9237
@end itemize
9238
 
9239
 
9240
@itemize @bullet
9241
@item poly16x4x4_t vld4_p16 (const poly16_t *)
9242
@*@emph{Form of expected instruction(s):} @code{vld4.16 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
9243
@end itemize
9244
 
9245
 
9246
@itemize @bullet
9247
@item poly8x8x4_t vld4_p8 (const poly8_t *)
9248
@*@emph{Form of expected instruction(s):} @code{vld4.8 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
9249
@end itemize
9250
 
9251
 
9252
@itemize @bullet
9253
@item uint64x1x4_t vld4_u64 (const uint64_t *)
9254
@*@emph{Form of expected instruction(s):} @code{vld1.64 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
9255
@end itemize
9256
 
9257
 
9258
@itemize @bullet
9259
@item int64x1x4_t vld4_s64 (const int64_t *)
9260
@*@emph{Form of expected instruction(s):} @code{vld1.64 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
9261
@end itemize
9262
 
9263
 
9264
@itemize @bullet
9265
@item uint32x4x4_t vld4q_u32 (const uint32_t *)
9266
@*@emph{Form of expected instruction(s):} @code{vld4.32 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
9267
@end itemize
9268
 
9269
 
9270
@itemize @bullet
9271
@item uint16x8x4_t vld4q_u16 (const uint16_t *)
9272
@*@emph{Form of expected instruction(s):} @code{vld4.16 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
9273
@end itemize
9274
 
9275
 
9276
@itemize @bullet
9277
@item uint8x16x4_t vld4q_u8 (const uint8_t *)
9278
@*@emph{Form of expected instruction(s):} @code{vld4.8 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
9279
@end itemize
9280
 
9281
 
9282
@itemize @bullet
9283
@item int32x4x4_t vld4q_s32 (const int32_t *)
9284
@*@emph{Form of expected instruction(s):} @code{vld4.32 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
9285
@end itemize
9286
 
9287
 
9288
@itemize @bullet
9289
@item int16x8x4_t vld4q_s16 (const int16_t *)
9290
@*@emph{Form of expected instruction(s):} @code{vld4.16 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
9291
@end itemize
9292
 
9293
 
9294
@itemize @bullet
9295
@item int8x16x4_t vld4q_s8 (const int8_t *)
9296
@*@emph{Form of expected instruction(s):} @code{vld4.8 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
9297
@end itemize
9298
 
9299
 
9300
@itemize @bullet
9301
@item float32x4x4_t vld4q_f32 (const float32_t *)
9302
@*@emph{Form of expected instruction(s):} @code{vld4.32 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
9303
@end itemize
9304
 
9305
 
9306
@itemize @bullet
9307
@item poly16x8x4_t vld4q_p16 (const poly16_t *)
9308
@*@emph{Form of expected instruction(s):} @code{vld4.16 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
9309
@end itemize
9310
 
9311
 
9312
@itemize @bullet
9313
@item poly8x16x4_t vld4q_p8 (const poly8_t *)
9314
@*@emph{Form of expected instruction(s):} @code{vld4.8 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
9315
@end itemize
9316
 
9317
 
9318
@itemize @bullet
9319
@item uint32x2x4_t vld4_lane_u32 (const uint32_t *, uint32x2x4_t, const int)
9320
@*@emph{Form of expected instruction(s):} @code{vld4.32 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}], @var{d3}[@var{0}]@}, [@var{r0}]}
9321
@end itemize
9322
 
9323
 
9324
@itemize @bullet
9325
@item uint16x4x4_t vld4_lane_u16 (const uint16_t *, uint16x4x4_t, const int)
9326
@*@emph{Form of expected instruction(s):} @code{vld4.16 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}], @var{d3}[@var{0}]@}, [@var{r0}]}
9327
@end itemize
9328
 
9329
 
9330
@itemize @bullet
9331
@item uint8x8x4_t vld4_lane_u8 (const uint8_t *, uint8x8x4_t, const int)
9332
@*@emph{Form of expected instruction(s):} @code{vld4.8 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}], @var{d3}[@var{0}]@}, [@var{r0}]}
9333
@end itemize
9334
 
9335
 
9336
@itemize @bullet
9337
@item int32x2x4_t vld4_lane_s32 (const int32_t *, int32x2x4_t, const int)
9338
@*@emph{Form of expected instruction(s):} @code{vld4.32 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}], @var{d3}[@var{0}]@}, [@var{r0}]}
9339
@end itemize
9340
 
9341
 
9342
@itemize @bullet
9343
@item int16x4x4_t vld4_lane_s16 (const int16_t *, int16x4x4_t, const int)
9344
@*@emph{Form of expected instruction(s):} @code{vld4.16 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}], @var{d3}[@var{0}]@}, [@var{r0}]}
9345
@end itemize
9346
 
9347
 
9348
@itemize @bullet
9349
@item int8x8x4_t vld4_lane_s8 (const int8_t *, int8x8x4_t, const int)
9350
@*@emph{Form of expected instruction(s):} @code{vld4.8 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}], @var{d3}[@var{0}]@}, [@var{r0}]}
9351
@end itemize
9352
 
9353
 
9354
@itemize @bullet
9355
@item float32x2x4_t vld4_lane_f32 (const float32_t *, float32x2x4_t, const int)
9356
@*@emph{Form of expected instruction(s):} @code{vld4.32 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}], @var{d3}[@var{0}]@}, [@var{r0}]}
9357
@end itemize
9358
 
9359
 
9360
@itemize @bullet
9361
@item poly16x4x4_t vld4_lane_p16 (const poly16_t *, poly16x4x4_t, const int)
9362
@*@emph{Form of expected instruction(s):} @code{vld4.16 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}], @var{d3}[@var{0}]@}, [@var{r0}]}
9363
@end itemize
9364
 
9365
 
9366
@itemize @bullet
9367
@item poly8x8x4_t vld4_lane_p8 (const poly8_t *, poly8x8x4_t, const int)
9368
@*@emph{Form of expected instruction(s):} @code{vld4.8 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}], @var{d3}[@var{0}]@}, [@var{r0}]}
9369
@end itemize
9370
 
9371
 
9372
@itemize @bullet
9373
@item int32x4x4_t vld4q_lane_s32 (const int32_t *, int32x4x4_t, const int)
9374
@*@emph{Form of expected instruction(s):} @code{vld4.32 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}], @var{d3}[@var{0}]@}, [@var{r0}]}
9375
@end itemize
9376
 
9377
 
9378
@itemize @bullet
9379
@item int16x8x4_t vld4q_lane_s16 (const int16_t *, int16x8x4_t, const int)
9380
@*@emph{Form of expected instruction(s):} @code{vld4.16 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}], @var{d3}[@var{0}]@}, [@var{r0}]}
9381
@end itemize
9382
 
9383
 
9384
@itemize @bullet
9385
@item uint32x4x4_t vld4q_lane_u32 (const uint32_t *, uint32x4x4_t, const int)
9386
@*@emph{Form of expected instruction(s):} @code{vld4.32 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}], @var{d3}[@var{0}]@}, [@var{r0}]}
9387
@end itemize
9388
 
9389
 
9390
@itemize @bullet
9391
@item uint16x8x4_t vld4q_lane_u16 (const uint16_t *, uint16x8x4_t, const int)
9392
@*@emph{Form of expected instruction(s):} @code{vld4.16 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}], @var{d3}[@var{0}]@}, [@var{r0}]}
9393
@end itemize
9394
 
9395
 
9396
@itemize @bullet
9397
@item float32x4x4_t vld4q_lane_f32 (const float32_t *, float32x4x4_t, const int)
9398
@*@emph{Form of expected instruction(s):} @code{vld4.32 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}], @var{d3}[@var{0}]@}, [@var{r0}]}
9399
@end itemize
9400
 
9401
 
9402
@itemize @bullet
9403
@item poly16x8x4_t vld4q_lane_p16 (const poly16_t *, poly16x8x4_t, const int)
9404
@*@emph{Form of expected instruction(s):} @code{vld4.16 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}], @var{d3}[@var{0}]@}, [@var{r0}]}
9405
@end itemize
9406
 
9407
 
9408
@itemize @bullet
9409
@item uint32x2x4_t vld4_dup_u32 (const uint32_t *)
9410
@*@emph{Form of expected instruction(s):} @code{vld4.32 @{@var{d0}[], @var{d1}[], @var{d2}[], @var{d3}[]@}, [@var{r0}]}
9411
@end itemize
9412
 
9413
 
9414
@itemize @bullet
9415
@item uint16x4x4_t vld4_dup_u16 (const uint16_t *)
9416
@*@emph{Form of expected instruction(s):} @code{vld4.16 @{@var{d0}[], @var{d1}[], @var{d2}[], @var{d3}[]@}, [@var{r0}]}
9417
@end itemize
9418
 
9419
 
9420
@itemize @bullet
9421
@item uint8x8x4_t vld4_dup_u8 (const uint8_t *)
9422
@*@emph{Form of expected instruction(s):} @code{vld4.8 @{@var{d0}[], @var{d1}[], @var{d2}[], @var{d3}[]@}, [@var{r0}]}
9423
@end itemize
9424
 
9425
 
9426
@itemize @bullet
9427
@item int32x2x4_t vld4_dup_s32 (const int32_t *)
9428
@*@emph{Form of expected instruction(s):} @code{vld4.32 @{@var{d0}[], @var{d1}[], @var{d2}[], @var{d3}[]@}, [@var{r0}]}
9429
@end itemize
9430
 
9431
 
9432
@itemize @bullet
9433
@item int16x4x4_t vld4_dup_s16 (const int16_t *)
9434
@*@emph{Form of expected instruction(s):} @code{vld4.16 @{@var{d0}[], @var{d1}[], @var{d2}[], @var{d3}[]@}, [@var{r0}]}
9435
@end itemize
9436
 
9437
 
9438
@itemize @bullet
9439
@item int8x8x4_t vld4_dup_s8 (const int8_t *)
9440
@*@emph{Form of expected instruction(s):} @code{vld4.8 @{@var{d0}[], @var{d1}[], @var{d2}[], @var{d3}[]@}, [@var{r0}]}
9441
@end itemize
9442
 
9443
 
9444
@itemize @bullet
9445
@item float32x2x4_t vld4_dup_f32 (const float32_t *)
9446
@*@emph{Form of expected instruction(s):} @code{vld4.32 @{@var{d0}[], @var{d1}[], @var{d2}[], @var{d3}[]@}, [@var{r0}]}
9447
@end itemize
9448
 
9449
 
9450
@itemize @bullet
9451
@item poly16x4x4_t vld4_dup_p16 (const poly16_t *)
9452
@*@emph{Form of expected instruction(s):} @code{vld4.16 @{@var{d0}[], @var{d1}[], @var{d2}[], @var{d3}[]@}, [@var{r0}]}
9453
@end itemize
9454
 
9455
 
9456
@itemize @bullet
9457
@item poly8x8x4_t vld4_dup_p8 (const poly8_t *)
9458
@*@emph{Form of expected instruction(s):} @code{vld4.8 @{@var{d0}[], @var{d1}[], @var{d2}[], @var{d3}[]@}, [@var{r0}]}
9459
@end itemize
9460
 
9461
 
9462
@itemize @bullet
9463
@item uint64x1x4_t vld4_dup_u64 (const uint64_t *)
9464
@*@emph{Form of expected instruction(s):} @code{vld1.64 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
9465
@end itemize
9466
 
9467
 
9468
@itemize @bullet
9469
@item int64x1x4_t vld4_dup_s64 (const int64_t *)
9470
@*@emph{Form of expected instruction(s):} @code{vld1.64 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
9471
@end itemize
9472
 
9473
 
9474
 
9475
 
9476
@subsubsection Element/structure stores, VST4 variants
9477
 
9478
@itemize @bullet
9479
@item void vst4_u32 (uint32_t *, uint32x2x4_t)
9480
@*@emph{Form of expected instruction(s):} @code{vst4.32 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
9481
@end itemize
9482
 
9483
 
9484
@itemize @bullet
9485
@item void vst4_u16 (uint16_t *, uint16x4x4_t)
9486
@*@emph{Form of expected instruction(s):} @code{vst4.16 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
9487
@end itemize
9488
 
9489
 
9490
@itemize @bullet
9491
@item void vst4_u8 (uint8_t *, uint8x8x4_t)
9492
@*@emph{Form of expected instruction(s):} @code{vst4.8 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
9493
@end itemize
9494
 
9495
 
9496
@itemize @bullet
9497
@item void vst4_s32 (int32_t *, int32x2x4_t)
9498
@*@emph{Form of expected instruction(s):} @code{vst4.32 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
9499
@end itemize
9500
 
9501
 
9502
@itemize @bullet
9503
@item void vst4_s16 (int16_t *, int16x4x4_t)
9504
@*@emph{Form of expected instruction(s):} @code{vst4.16 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
9505
@end itemize
9506
 
9507
 
9508
@itemize @bullet
9509
@item void vst4_s8 (int8_t *, int8x8x4_t)
9510
@*@emph{Form of expected instruction(s):} @code{vst4.8 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
9511
@end itemize
9512
 
9513
 
9514
@itemize @bullet
9515
@item void vst4_f32 (float32_t *, float32x2x4_t)
9516
@*@emph{Form of expected instruction(s):} @code{vst4.32 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
9517
@end itemize
9518
 
9519
 
9520
@itemize @bullet
9521
@item void vst4_p16 (poly16_t *, poly16x4x4_t)
9522
@*@emph{Form of expected instruction(s):} @code{vst4.16 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
9523
@end itemize
9524
 
9525
 
9526
@itemize @bullet
9527
@item void vst4_p8 (poly8_t *, poly8x8x4_t)
9528
@*@emph{Form of expected instruction(s):} @code{vst4.8 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
9529
@end itemize
9530
 
9531
 
9532
@itemize @bullet
9533
@item void vst4_u64 (uint64_t *, uint64x1x4_t)
9534
@*@emph{Form of expected instruction(s):} @code{vst1.64 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
9535
@end itemize
9536
 
9537
 
9538
@itemize @bullet
9539
@item void vst4_s64 (int64_t *, int64x1x4_t)
9540
@*@emph{Form of expected instruction(s):} @code{vst1.64 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
9541
@end itemize
9542
 
9543
 
9544
@itemize @bullet
9545
@item void vst4q_u32 (uint32_t *, uint32x4x4_t)
9546
@*@emph{Form of expected instruction(s):} @code{vst4.32 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
9547
@end itemize
9548
 
9549
 
9550
@itemize @bullet
9551
@item void vst4q_u16 (uint16_t *, uint16x8x4_t)
9552
@*@emph{Form of expected instruction(s):} @code{vst4.16 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
9553
@end itemize
9554
 
9555
 
9556
@itemize @bullet
9557
@item void vst4q_u8 (uint8_t *, uint8x16x4_t)
9558
@*@emph{Form of expected instruction(s):} @code{vst4.8 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
9559
@end itemize
9560
 
9561
 
9562
@itemize @bullet
9563
@item void vst4q_s32 (int32_t *, int32x4x4_t)
9564
@*@emph{Form of expected instruction(s):} @code{vst4.32 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
9565
@end itemize
9566
 
9567
 
9568
@itemize @bullet
9569
@item void vst4q_s16 (int16_t *, int16x8x4_t)
9570
@*@emph{Form of expected instruction(s):} @code{vst4.16 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
9571
@end itemize
9572
 
9573
 
9574
@itemize @bullet
9575
@item void vst4q_s8 (int8_t *, int8x16x4_t)
9576
@*@emph{Form of expected instruction(s):} @code{vst4.8 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
9577
@end itemize
9578
 
9579
 
9580
@itemize @bullet
9581
@item void vst4q_f32 (float32_t *, float32x4x4_t)
9582
@*@emph{Form of expected instruction(s):} @code{vst4.32 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
9583
@end itemize
9584
 
9585
 
9586
@itemize @bullet
9587
@item void vst4q_p16 (poly16_t *, poly16x8x4_t)
9588
@*@emph{Form of expected instruction(s):} @code{vst4.16 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
9589
@end itemize
9590
 
9591
 
9592
@itemize @bullet
9593
@item void vst4q_p8 (poly8_t *, poly8x16x4_t)
9594
@*@emph{Form of expected instruction(s):} @code{vst4.8 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
9595
@end itemize
9596
 
9597
 
9598
@itemize @bullet
9599
@item void vst4_lane_u32 (uint32_t *, uint32x2x4_t, const int)
9600
@*@emph{Form of expected instruction(s):} @code{vst4.32 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}], @var{d3}[@var{0}]@}, [@var{r0}]}
9601
@end itemize
9602
 
9603
 
9604
@itemize @bullet
9605
@item void vst4_lane_u16 (uint16_t *, uint16x4x4_t, const int)
9606
@*@emph{Form of expected instruction(s):} @code{vst4.16 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}], @var{d3}[@var{0}]@}, [@var{r0}]}
9607
@end itemize
9608
 
9609
 
9610
@itemize @bullet
9611
@item void vst4_lane_u8 (uint8_t *, uint8x8x4_t, const int)
9612
@*@emph{Form of expected instruction(s):} @code{vst4.8 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}], @var{d3}[@var{0}]@}, [@var{r0}]}
9613
@end itemize
9614
 
9615
 
9616
@itemize @bullet
9617
@item void vst4_lane_s32 (int32_t *, int32x2x4_t, const int)
9618
@*@emph{Form of expected instruction(s):} @code{vst4.32 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}], @var{d3}[@var{0}]@}, [@var{r0}]}
9619
@end itemize
9620
 
9621
 
9622
@itemize @bullet
9623
@item void vst4_lane_s16 (int16_t *, int16x4x4_t, const int)
9624
@*@emph{Form of expected instruction(s):} @code{vst4.16 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}], @var{d3}[@var{0}]@}, [@var{r0}]}
9625
@end itemize
9626
 
9627
 
9628
@itemize @bullet
9629
@item void vst4_lane_s8 (int8_t *, int8x8x4_t, const int)
9630
@*@emph{Form of expected instruction(s):} @code{vst4.8 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}], @var{d3}[@var{0}]@}, [@var{r0}]}
9631
@end itemize
9632
 
9633
 
9634
@itemize @bullet
9635
@item void vst4_lane_f32 (float32_t *, float32x2x4_t, const int)
9636
@*@emph{Form of expected instruction(s):} @code{vst4.32 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}], @var{d3}[@var{0}]@}, [@var{r0}]}
9637
@end itemize
9638
 
9639
 
9640
@itemize @bullet
9641
@item void vst4_lane_p16 (poly16_t *, poly16x4x4_t, const int)
9642
@*@emph{Form of expected instruction(s):} @code{vst4.16 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}], @var{d3}[@var{0}]@}, [@var{r0}]}
9643
@end itemize
9644
 
9645
 
9646
@itemize @bullet
9647
@item void vst4_lane_p8 (poly8_t *, poly8x8x4_t, const int)
9648
@*@emph{Form of expected instruction(s):} @code{vst4.8 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}], @var{d3}[@var{0}]@}, [@var{r0}]}
9649
@end itemize
9650
 
9651
 
9652
@itemize @bullet
9653
@item void vst4q_lane_s32 (int32_t *, int32x4x4_t, const int)
9654
@*@emph{Form of expected instruction(s):} @code{vst4.32 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}], @var{d3}[@var{0}]@}, [@var{r0}]}
9655
@end itemize
9656
 
9657
 
9658
@itemize @bullet
9659
@item void vst4q_lane_s16 (int16_t *, int16x8x4_t, const int)
9660
@*@emph{Form of expected instruction(s):} @code{vst4.16 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}], @var{d3}[@var{0}]@}, [@var{r0}]}
9661
@end itemize
9662
 
9663
 
9664
@itemize @bullet
9665
@item void vst4q_lane_u32 (uint32_t *, uint32x4x4_t, const int)
9666
@*@emph{Form of expected instruction(s):} @code{vst4.32 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}], @var{d3}[@var{0}]@}, [@var{r0}]}
9667
@end itemize
9668
 
9669
 
9670
@itemize @bullet
9671
@item void vst4q_lane_u16 (uint16_t *, uint16x8x4_t, const int)
9672
@*@emph{Form of expected instruction(s):} @code{vst4.16 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}], @var{d3}[@var{0}]@}, [@var{r0}]}
9673
@end itemize
9674
 
9675
 
9676
@itemize @bullet
9677
@item void vst4q_lane_f32 (float32_t *, float32x4x4_t, const int)
9678
@*@emph{Form of expected instruction(s):} @code{vst4.32 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}], @var{d3}[@var{0}]@}, [@var{r0}]}
9679
@end itemize
9680
 
9681
 
9682
@itemize @bullet
9683
@item void vst4q_lane_p16 (poly16_t *, poly16x8x4_t, const int)
9684
@*@emph{Form of expected instruction(s):} @code{vst4.16 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}], @var{d3}[@var{0}]@}, [@var{r0}]}
9685
@end itemize
9686
 
9687
 
9688
 
9689
 
9690
@subsubsection Logical operations (AND)
9691
 
9692
@itemize @bullet
9693
@item uint32x2_t vand_u32 (uint32x2_t, uint32x2_t)
9694
@*@emph{Form of expected instruction(s):} @code{vand @var{d0}, @var{d0}, @var{d0}}
9695
@end itemize
9696
 
9697
 
9698
@itemize @bullet
9699
@item uint16x4_t vand_u16 (uint16x4_t, uint16x4_t)
9700
@*@emph{Form of expected instruction(s):} @code{vand @var{d0}, @var{d0}, @var{d0}}
9701
@end itemize
9702
 
9703
 
9704
@itemize @bullet
9705
@item uint8x8_t vand_u8 (uint8x8_t, uint8x8_t)
9706
@*@emph{Form of expected instruction(s):} @code{vand @var{d0}, @var{d0}, @var{d0}}
9707
@end itemize
9708
 
9709
 
9710
@itemize @bullet
9711
@item int32x2_t vand_s32 (int32x2_t, int32x2_t)
9712
@*@emph{Form of expected instruction(s):} @code{vand @var{d0}, @var{d0}, @var{d0}}
9713
@end itemize
9714
 
9715
 
9716
@itemize @bullet
9717
@item int16x4_t vand_s16 (int16x4_t, int16x4_t)
9718
@*@emph{Form of expected instruction(s):} @code{vand @var{d0}, @var{d0}, @var{d0}}
9719
@end itemize
9720
 
9721
 
9722
@itemize @bullet
9723
@item int8x8_t vand_s8 (int8x8_t, int8x8_t)
9724
@*@emph{Form of expected instruction(s):} @code{vand @var{d0}, @var{d0}, @var{d0}}
9725
@end itemize
9726
 
9727
 
9728
@itemize @bullet
9729
@item uint64x1_t vand_u64 (uint64x1_t, uint64x1_t)
9730
@*@emph{Form of expected instruction(s):} @code{vand @var{d0}, @var{d0}, @var{d0}}
9731
@end itemize
9732
 
9733
 
9734
@itemize @bullet
9735
@item int64x1_t vand_s64 (int64x1_t, int64x1_t)
9736
@*@emph{Form of expected instruction(s):} @code{vand @var{d0}, @var{d0}, @var{d0}}
9737
@end itemize
9738
 
9739
 
9740
@itemize @bullet
9741
@item uint32x4_t vandq_u32 (uint32x4_t, uint32x4_t)
9742
@*@emph{Form of expected instruction(s):} @code{vand @var{q0}, @var{q0}, @var{q0}}
9743
@end itemize
9744
 
9745
 
9746
@itemize @bullet
9747
@item uint16x8_t vandq_u16 (uint16x8_t, uint16x8_t)
9748
@*@emph{Form of expected instruction(s):} @code{vand @var{q0}, @var{q0}, @var{q0}}
9749
@end itemize
9750
 
9751
 
9752
@itemize @bullet
9753
@item uint8x16_t vandq_u8 (uint8x16_t, uint8x16_t)
9754
@*@emph{Form of expected instruction(s):} @code{vand @var{q0}, @var{q0}, @var{q0}}
9755
@end itemize
9756
 
9757
 
9758
@itemize @bullet
9759
@item int32x4_t vandq_s32 (int32x4_t, int32x4_t)
9760
@*@emph{Form of expected instruction(s):} @code{vand @var{q0}, @var{q0}, @var{q0}}
9761
@end itemize
9762
 
9763
 
9764
@itemize @bullet
9765
@item int16x8_t vandq_s16 (int16x8_t, int16x8_t)
9766
@*@emph{Form of expected instruction(s):} @code{vand @var{q0}, @var{q0}, @var{q0}}
9767
@end itemize
9768
 
9769
 
9770
@itemize @bullet
9771
@item int8x16_t vandq_s8 (int8x16_t, int8x16_t)
9772
@*@emph{Form of expected instruction(s):} @code{vand @var{q0}, @var{q0}, @var{q0}}
9773
@end itemize
9774
 
9775
 
9776
@itemize @bullet
9777
@item uint64x2_t vandq_u64 (uint64x2_t, uint64x2_t)
9778
@*@emph{Form of expected instruction(s):} @code{vand @var{q0}, @var{q0}, @var{q0}}
9779
@end itemize
9780
 
9781
 
9782
@itemize @bullet
9783
@item int64x2_t vandq_s64 (int64x2_t, int64x2_t)
9784
@*@emph{Form of expected instruction(s):} @code{vand @var{q0}, @var{q0}, @var{q0}}
9785
@end itemize
9786
 
9787
 
9788
 
9789
 
9790
@subsubsection Logical operations (OR)
9791
 
9792
@itemize @bullet
9793
@item uint32x2_t vorr_u32 (uint32x2_t, uint32x2_t)
9794
@*@emph{Form of expected instruction(s):} @code{vorr @var{d0}, @var{d0}, @var{d0}}
9795
@end itemize
9796
 
9797
 
9798
@itemize @bullet
9799
@item uint16x4_t vorr_u16 (uint16x4_t, uint16x4_t)
9800
@*@emph{Form of expected instruction(s):} @code{vorr @var{d0}, @var{d0}, @var{d0}}
9801
@end itemize
9802
 
9803
 
9804
@itemize @bullet
9805
@item uint8x8_t vorr_u8 (uint8x8_t, uint8x8_t)
9806
@*@emph{Form of expected instruction(s):} @code{vorr @var{d0}, @var{d0}, @var{d0}}
9807
@end itemize
9808
 
9809
 
9810
@itemize @bullet
9811
@item int32x2_t vorr_s32 (int32x2_t, int32x2_t)
9812
@*@emph{Form of expected instruction(s):} @code{vorr @var{d0}, @var{d0}, @var{d0}}
9813
@end itemize
9814
 
9815
 
9816
@itemize @bullet
9817
@item int16x4_t vorr_s16 (int16x4_t, int16x4_t)
9818
@*@emph{Form of expected instruction(s):} @code{vorr @var{d0}, @var{d0}, @var{d0}}
9819
@end itemize
9820
 
9821
 
9822
@itemize @bullet
9823
@item int8x8_t vorr_s8 (int8x8_t, int8x8_t)
9824
@*@emph{Form of expected instruction(s):} @code{vorr @var{d0}, @var{d0}, @var{d0}}
9825
@end itemize
9826
 
9827
 
9828
@itemize @bullet
9829
@item uint64x1_t vorr_u64 (uint64x1_t, uint64x1_t)
9830
@*@emph{Form of expected instruction(s):} @code{vorr @var{d0}, @var{d0}, @var{d0}}
9831
@end itemize
9832
 
9833
 
9834
@itemize @bullet
9835
@item int64x1_t vorr_s64 (int64x1_t, int64x1_t)
9836
@*@emph{Form of expected instruction(s):} @code{vorr @var{d0}, @var{d0}, @var{d0}}
9837
@end itemize
9838
 
9839
 
9840
@itemize @bullet
9841
@item uint32x4_t vorrq_u32 (uint32x4_t, uint32x4_t)
9842
@*@emph{Form of expected instruction(s):} @code{vorr @var{q0}, @var{q0}, @var{q0}}
9843
@end itemize
9844
 
9845
 
9846
@itemize @bullet
9847
@item uint16x8_t vorrq_u16 (uint16x8_t, uint16x8_t)
9848
@*@emph{Form of expected instruction(s):} @code{vorr @var{q0}, @var{q0}, @var{q0}}
9849
@end itemize
9850
 
9851
 
9852
@itemize @bullet
9853
@item uint8x16_t vorrq_u8 (uint8x16_t, uint8x16_t)
9854
@*@emph{Form of expected instruction(s):} @code{vorr @var{q0}, @var{q0}, @var{q0}}
9855
@end itemize
9856
 
9857
 
9858
@itemize @bullet
9859
@item int32x4_t vorrq_s32 (int32x4_t, int32x4_t)
9860
@*@emph{Form of expected instruction(s):} @code{vorr @var{q0}, @var{q0}, @var{q0}}
9861
@end itemize
9862
 
9863
 
9864
@itemize @bullet
9865
@item int16x8_t vorrq_s16 (int16x8_t, int16x8_t)
9866
@*@emph{Form of expected instruction(s):} @code{vorr @var{q0}, @var{q0}, @var{q0}}
9867
@end itemize
9868
 
9869
 
9870
@itemize @bullet
9871
@item int8x16_t vorrq_s8 (int8x16_t, int8x16_t)
9872
@*@emph{Form of expected instruction(s):} @code{vorr @var{q0}, @var{q0}, @var{q0}}
9873
@end itemize
9874
 
9875
 
9876
@itemize @bullet
9877
@item uint64x2_t vorrq_u64 (uint64x2_t, uint64x2_t)
9878
@*@emph{Form of expected instruction(s):} @code{vorr @var{q0}, @var{q0}, @var{q0}}
9879
@end itemize
9880
 
9881
 
9882
@itemize @bullet
9883
@item int64x2_t vorrq_s64 (int64x2_t, int64x2_t)
9884
@*@emph{Form of expected instruction(s):} @code{vorr @var{q0}, @var{q0}, @var{q0}}
9885
@end itemize
9886
 
9887
 
9888
 
9889
 
9890
@subsubsection Logical operations (exclusive OR)
9891
 
9892
@itemize @bullet
9893
@item uint32x2_t veor_u32 (uint32x2_t, uint32x2_t)
9894
@*@emph{Form of expected instruction(s):} @code{veor @var{d0}, @var{d0}, @var{d0}}
9895
@end itemize
9896
 
9897
 
9898
@itemize @bullet
9899
@item uint16x4_t veor_u16 (uint16x4_t, uint16x4_t)
9900
@*@emph{Form of expected instruction(s):} @code{veor @var{d0}, @var{d0}, @var{d0}}
9901
@end itemize
9902
 
9903
 
9904
@itemize @bullet
9905
@item uint8x8_t veor_u8 (uint8x8_t, uint8x8_t)
9906
@*@emph{Form of expected instruction(s):} @code{veor @var{d0}, @var{d0}, @var{d0}}
9907
@end itemize
9908
 
9909
 
9910
@itemize @bullet
9911
@item int32x2_t veor_s32 (int32x2_t, int32x2_t)
9912
@*@emph{Form of expected instruction(s):} @code{veor @var{d0}, @var{d0}, @var{d0}}
9913
@end itemize
9914
 
9915
 
9916
@itemize @bullet
9917
@item int16x4_t veor_s16 (int16x4_t, int16x4_t)
9918
@*@emph{Form of expected instruction(s):} @code{veor @var{d0}, @var{d0}, @var{d0}}
9919
@end itemize
9920
 
9921
 
9922
@itemize @bullet
9923
@item int8x8_t veor_s8 (int8x8_t, int8x8_t)
9924
@*@emph{Form of expected instruction(s):} @code{veor @var{d0}, @var{d0}, @var{d0}}
9925
@end itemize
9926
 
9927
 
9928
@itemize @bullet
9929
@item uint64x1_t veor_u64 (uint64x1_t, uint64x1_t)
9930
@*@emph{Form of expected instruction(s):} @code{veor @var{d0}, @var{d0}, @var{d0}}
9931
@end itemize
9932
 
9933
 
9934
@itemize @bullet
9935
@item int64x1_t veor_s64 (int64x1_t, int64x1_t)
9936
@*@emph{Form of expected instruction(s):} @code{veor @var{d0}, @var{d0}, @var{d0}}
9937
@end itemize
9938
 
9939
 
9940
@itemize @bullet
9941
@item uint32x4_t veorq_u32 (uint32x4_t, uint32x4_t)
9942
@*@emph{Form of expected instruction(s):} @code{veor @var{q0}, @var{q0}, @var{q0}}
9943
@end itemize
9944
 
9945
 
9946
@itemize @bullet
9947
@item uint16x8_t veorq_u16 (uint16x8_t, uint16x8_t)
9948
@*@emph{Form of expected instruction(s):} @code{veor @var{q0}, @var{q0}, @var{q0}}
9949
@end itemize
9950
 
9951
 
9952
@itemize @bullet
9953
@item uint8x16_t veorq_u8 (uint8x16_t, uint8x16_t)
9954
@*@emph{Form of expected instruction(s):} @code{veor @var{q0}, @var{q0}, @var{q0}}
9955
@end itemize
9956
 
9957
 
9958
@itemize @bullet
9959
@item int32x4_t veorq_s32 (int32x4_t, int32x4_t)
9960
@*@emph{Form of expected instruction(s):} @code{veor @var{q0}, @var{q0}, @var{q0}}
9961
@end itemize
9962
 
9963
 
9964
@itemize @bullet
9965
@item int16x8_t veorq_s16 (int16x8_t, int16x8_t)
9966
@*@emph{Form of expected instruction(s):} @code{veor @var{q0}, @var{q0}, @var{q0}}
9967
@end itemize
9968
 
9969
 
9970
@itemize @bullet
9971
@item int8x16_t veorq_s8 (int8x16_t, int8x16_t)
9972
@*@emph{Form of expected instruction(s):} @code{veor @var{q0}, @var{q0}, @var{q0}}
9973
@end itemize
9974
 
9975
 
9976
@itemize @bullet
9977
@item uint64x2_t veorq_u64 (uint64x2_t, uint64x2_t)
9978
@*@emph{Form of expected instruction(s):} @code{veor @var{q0}, @var{q0}, @var{q0}}
9979
@end itemize
9980
 
9981
 
9982
@itemize @bullet
9983
@item int64x2_t veorq_s64 (int64x2_t, int64x2_t)
9984
@*@emph{Form of expected instruction(s):} @code{veor @var{q0}, @var{q0}, @var{q0}}
9985
@end itemize
9986
 
9987
 
9988
 
9989
 
9990
@subsubsection Logical operations (AND-NOT)
9991
 
9992
@itemize @bullet
9993
@item uint32x2_t vbic_u32 (uint32x2_t, uint32x2_t)
9994
@*@emph{Form of expected instruction(s):} @code{vbic @var{d0}, @var{d0}, @var{d0}}
9995
@end itemize
9996
 
9997
 
9998
@itemize @bullet
9999
@item uint16x4_t vbic_u16 (uint16x4_t, uint16x4_t)
10000
@*@emph{Form of expected instruction(s):} @code{vbic @var{d0}, @var{d0}, @var{d0}}
10001
@end itemize
10002
 
10003
 
10004
@itemize @bullet
10005
@item uint8x8_t vbic_u8 (uint8x8_t, uint8x8_t)
10006
@*@emph{Form of expected instruction(s):} @code{vbic @var{d0}, @var{d0}, @var{d0}}
10007
@end itemize
10008
 
10009
 
10010
@itemize @bullet
10011
@item int32x2_t vbic_s32 (int32x2_t, int32x2_t)
10012
@*@emph{Form of expected instruction(s):} @code{vbic @var{d0}, @var{d0}, @var{d0}}
10013
@end itemize
10014
 
10015
 
10016
@itemize @bullet
10017
@item int16x4_t vbic_s16 (int16x4_t, int16x4_t)
10018
@*@emph{Form of expected instruction(s):} @code{vbic @var{d0}, @var{d0}, @var{d0}}
10019
@end itemize
10020
 
10021
 
10022
@itemize @bullet
10023
@item int8x8_t vbic_s8 (int8x8_t, int8x8_t)
10024
@*@emph{Form of expected instruction(s):} @code{vbic @var{d0}, @var{d0}, @var{d0}}
10025
@end itemize
10026
 
10027
 
10028
@itemize @bullet
10029
@item uint64x1_t vbic_u64 (uint64x1_t, uint64x1_t)
10030
@*@emph{Form of expected instruction(s):} @code{vbic @var{d0}, @var{d0}, @var{d0}}
10031
@end itemize
10032
 
10033
 
10034
@itemize @bullet
10035
@item int64x1_t vbic_s64 (int64x1_t, int64x1_t)
10036
@*@emph{Form of expected instruction(s):} @code{vbic @var{d0}, @var{d0}, @var{d0}}
10037
@end itemize
10038
 
10039
 
10040
@itemize @bullet
10041
@item uint32x4_t vbicq_u32 (uint32x4_t, uint32x4_t)
10042
@*@emph{Form of expected instruction(s):} @code{vbic @var{q0}, @var{q0}, @var{q0}}
10043
@end itemize
10044
 
10045
 
10046
@itemize @bullet
10047
@item uint16x8_t vbicq_u16 (uint16x8_t, uint16x8_t)
10048
@*@emph{Form of expected instruction(s):} @code{vbic @var{q0}, @var{q0}, @var{q0}}
10049
@end itemize
10050
 
10051
 
10052
@itemize @bullet
10053
@item uint8x16_t vbicq_u8 (uint8x16_t, uint8x16_t)
10054
@*@emph{Form of expected instruction(s):} @code{vbic @var{q0}, @var{q0}, @var{q0}}
10055
@end itemize
10056
 
10057
 
10058
@itemize @bullet
10059
@item int32x4_t vbicq_s32 (int32x4_t, int32x4_t)
10060
@*@emph{Form of expected instruction(s):} @code{vbic @var{q0}, @var{q0}, @var{q0}}
10061
@end itemize
10062
 
10063
 
10064
@itemize @bullet
10065
@item int16x8_t vbicq_s16 (int16x8_t, int16x8_t)
10066
@*@emph{Form of expected instruction(s):} @code{vbic @var{q0}, @var{q0}, @var{q0}}
10067
@end itemize
10068
 
10069
 
10070
@itemize @bullet
10071
@item int8x16_t vbicq_s8 (int8x16_t, int8x16_t)
10072
@*@emph{Form of expected instruction(s):} @code{vbic @var{q0}, @var{q0}, @var{q0}}
10073
@end itemize
10074
 
10075
 
10076
@itemize @bullet
10077
@item uint64x2_t vbicq_u64 (uint64x2_t, uint64x2_t)
10078
@*@emph{Form of expected instruction(s):} @code{vbic @var{q0}, @var{q0}, @var{q0}}
10079
@end itemize
10080
 
10081
 
10082
@itemize @bullet
10083
@item int64x2_t vbicq_s64 (int64x2_t, int64x2_t)
10084
@*@emph{Form of expected instruction(s):} @code{vbic @var{q0}, @var{q0}, @var{q0}}
10085
@end itemize
10086
 
10087
 
10088
 
10089
 
10090
@subsubsection Logical operations (OR-NOT)
10091
 
10092
@itemize @bullet
10093
@item uint32x2_t vorn_u32 (uint32x2_t, uint32x2_t)
10094
@*@emph{Form of expected instruction(s):} @code{vorn @var{d0}, @var{d0}, @var{d0}}
10095
@end itemize
10096
 
10097
 
10098
@itemize @bullet
10099
@item uint16x4_t vorn_u16 (uint16x4_t, uint16x4_t)
10100
@*@emph{Form of expected instruction(s):} @code{vorn @var{d0}, @var{d0}, @var{d0}}
10101
@end itemize
10102
 
10103
 
10104
@itemize @bullet
10105
@item uint8x8_t vorn_u8 (uint8x8_t, uint8x8_t)
10106
@*@emph{Form of expected instruction(s):} @code{vorn @var{d0}, @var{d0}, @var{d0}}
10107
@end itemize
10108
 
10109
 
10110
@itemize @bullet
10111
@item int32x2_t vorn_s32 (int32x2_t, int32x2_t)
10112
@*@emph{Form of expected instruction(s):} @code{vorn @var{d0}, @var{d0}, @var{d0}}
10113
@end itemize
10114
 
10115
 
10116
@itemize @bullet
10117
@item int16x4_t vorn_s16 (int16x4_t, int16x4_t)
10118
@*@emph{Form of expected instruction(s):} @code{vorn @var{d0}, @var{d0}, @var{d0}}
10119
@end itemize
10120
 
10121
 
10122
@itemize @bullet
10123
@item int8x8_t vorn_s8 (int8x8_t, int8x8_t)
10124
@*@emph{Form of expected instruction(s):} @code{vorn @var{d0}, @var{d0}, @var{d0}}
10125
@end itemize
10126
 
10127
 
10128
@itemize @bullet
10129
@item uint64x1_t vorn_u64 (uint64x1_t, uint64x1_t)
10130
@*@emph{Form of expected instruction(s):} @code{vorn @var{d0}, @var{d0}, @var{d0}}
10131
@end itemize
10132
 
10133
 
10134
@itemize @bullet
10135
@item int64x1_t vorn_s64 (int64x1_t, int64x1_t)
10136
@*@emph{Form of expected instruction(s):} @code{vorn @var{d0}, @var{d0}, @var{d0}}
10137
@end itemize
10138
 
10139
 
10140
@itemize @bullet
10141
@item uint32x4_t vornq_u32 (uint32x4_t, uint32x4_t)
10142
@*@emph{Form of expected instruction(s):} @code{vorn @var{q0}, @var{q0}, @var{q0}}
10143
@end itemize
10144
 
10145
 
10146
@itemize @bullet
10147
@item uint16x8_t vornq_u16 (uint16x8_t, uint16x8_t)
10148
@*@emph{Form of expected instruction(s):} @code{vorn @var{q0}, @var{q0}, @var{q0}}
10149
@end itemize
10150
 
10151
 
10152
@itemize @bullet
10153
@item uint8x16_t vornq_u8 (uint8x16_t, uint8x16_t)
10154
@*@emph{Form of expected instruction(s):} @code{vorn @var{q0}, @var{q0}, @var{q0}}
10155
@end itemize
10156
 
10157
 
10158
@itemize @bullet
10159
@item int32x4_t vornq_s32 (int32x4_t, int32x4_t)
10160
@*@emph{Form of expected instruction(s):} @code{vorn @var{q0}, @var{q0}, @var{q0}}
10161
@end itemize
10162
 
10163
 
10164
@itemize @bullet
10165
@item int16x8_t vornq_s16 (int16x8_t, int16x8_t)
10166
@*@emph{Form of expected instruction(s):} @code{vorn @var{q0}, @var{q0}, @var{q0}}
10167
@end itemize
10168
 
10169
 
10170
@itemize @bullet
10171
@item int8x16_t vornq_s8 (int8x16_t, int8x16_t)
10172
@*@emph{Form of expected instruction(s):} @code{vorn @var{q0}, @var{q0}, @var{q0}}
10173
@end itemize
10174
 
10175
 
10176
@itemize @bullet
10177
@item uint64x2_t vornq_u64 (uint64x2_t, uint64x2_t)
10178
@*@emph{Form of expected instruction(s):} @code{vorn @var{q0}, @var{q0}, @var{q0}}
10179
@end itemize
10180
 
10181
 
10182
@itemize @bullet
10183
@item int64x2_t vornq_s64 (int64x2_t, int64x2_t)
10184
@*@emph{Form of expected instruction(s):} @code{vorn @var{q0}, @var{q0}, @var{q0}}
10185
@end itemize
10186
 
10187
 
10188
 
10189
 
10190
@subsubsection Reinterpret casts
10191
 
10192
@itemize @bullet
10193
@item poly8x8_t vreinterpret_p8_u32 (uint32x2_t)
10194
@end itemize
10195
 
10196
 
10197
@itemize @bullet
10198
@item poly8x8_t vreinterpret_p8_u16 (uint16x4_t)
10199
@end itemize
10200
 
10201
 
10202
@itemize @bullet
10203
@item poly8x8_t vreinterpret_p8_u8 (uint8x8_t)
10204
@end itemize
10205
 
10206
 
10207
@itemize @bullet
10208
@item poly8x8_t vreinterpret_p8_s32 (int32x2_t)
10209
@end itemize
10210
 
10211
 
10212
@itemize @bullet
10213
@item poly8x8_t vreinterpret_p8_s16 (int16x4_t)
10214
@end itemize
10215
 
10216
 
10217
@itemize @bullet
10218
@item poly8x8_t vreinterpret_p8_s8 (int8x8_t)
10219
@end itemize
10220
 
10221
 
10222
@itemize @bullet
10223
@item poly8x8_t vreinterpret_p8_u64 (uint64x1_t)
10224
@end itemize
10225
 
10226
 
10227
@itemize @bullet
10228
@item poly8x8_t vreinterpret_p8_s64 (int64x1_t)
10229
@end itemize
10230
 
10231
 
10232
@itemize @bullet
10233
@item poly8x8_t vreinterpret_p8_f32 (float32x2_t)
10234
@end itemize
10235
 
10236
 
10237
@itemize @bullet
10238
@item poly8x8_t vreinterpret_p8_p16 (poly16x4_t)
10239
@end itemize
10240
 
10241
 
10242
@itemize @bullet
10243
@item poly8x16_t vreinterpretq_p8_u32 (uint32x4_t)
10244
@end itemize
10245
 
10246
 
10247
@itemize @bullet
10248
@item poly8x16_t vreinterpretq_p8_u16 (uint16x8_t)
10249
@end itemize
10250
 
10251
 
10252
@itemize @bullet
10253
@item poly8x16_t vreinterpretq_p8_u8 (uint8x16_t)
10254
@end itemize
10255
 
10256
 
10257
@itemize @bullet
10258
@item poly8x16_t vreinterpretq_p8_s32 (int32x4_t)
10259
@end itemize
10260
 
10261
 
10262
@itemize @bullet
10263
@item poly8x16_t vreinterpretq_p8_s16 (int16x8_t)
10264
@end itemize
10265
 
10266
 
10267
@itemize @bullet
10268
@item poly8x16_t vreinterpretq_p8_s8 (int8x16_t)
10269
@end itemize
10270
 
10271
 
10272
@itemize @bullet
10273
@item poly8x16_t vreinterpretq_p8_u64 (uint64x2_t)
10274
@end itemize
10275
 
10276
 
10277
@itemize @bullet
10278
@item poly8x16_t vreinterpretq_p8_s64 (int64x2_t)
10279
@end itemize
10280
 
10281
 
10282
@itemize @bullet
10283
@item poly8x16_t vreinterpretq_p8_f32 (float32x4_t)
10284
@end itemize
10285
 
10286
 
10287
@itemize @bullet
10288
@item poly8x16_t vreinterpretq_p8_p16 (poly16x8_t)
10289
@end itemize
10290
 
10291
 
10292
@itemize @bullet
10293
@item poly16x4_t vreinterpret_p16_u32 (uint32x2_t)
10294
@end itemize
10295
 
10296
 
10297
@itemize @bullet
10298
@item poly16x4_t vreinterpret_p16_u16 (uint16x4_t)
10299
@end itemize
10300
 
10301
 
10302
@itemize @bullet
10303
@item poly16x4_t vreinterpret_p16_u8 (uint8x8_t)
10304
@end itemize
10305
 
10306
 
10307
@itemize @bullet
10308
@item poly16x4_t vreinterpret_p16_s32 (int32x2_t)
10309
@end itemize
10310
 
10311
 
10312
@itemize @bullet
10313
@item poly16x4_t vreinterpret_p16_s16 (int16x4_t)
10314
@end itemize
10315
 
10316
 
10317
@itemize @bullet
10318
@item poly16x4_t vreinterpret_p16_s8 (int8x8_t)
10319
@end itemize
10320
 
10321
 
10322
@itemize @bullet
10323
@item poly16x4_t vreinterpret_p16_u64 (uint64x1_t)
10324
@end itemize
10325
 
10326
 
10327
@itemize @bullet
10328
@item poly16x4_t vreinterpret_p16_s64 (int64x1_t)
10329
@end itemize
10330
 
10331
 
10332
@itemize @bullet
10333
@item poly16x4_t vreinterpret_p16_f32 (float32x2_t)
10334
@end itemize
10335
 
10336
 
10337
@itemize @bullet
10338
@item poly16x4_t vreinterpret_p16_p8 (poly8x8_t)
10339
@end itemize
10340
 
10341
 
10342
@itemize @bullet
10343
@item poly16x8_t vreinterpretq_p16_u32 (uint32x4_t)
10344
@end itemize
10345
 
10346
 
10347
@itemize @bullet
10348
@item poly16x8_t vreinterpretq_p16_u16 (uint16x8_t)
10349
@end itemize
10350
 
10351
 
10352
@itemize @bullet
10353
@item poly16x8_t vreinterpretq_p16_u8 (uint8x16_t)
10354
@end itemize
10355
 
10356
 
10357
@itemize @bullet
10358
@item poly16x8_t vreinterpretq_p16_s32 (int32x4_t)
10359
@end itemize
10360
 
10361
 
10362
@itemize @bullet
10363
@item poly16x8_t vreinterpretq_p16_s16 (int16x8_t)
10364
@end itemize
10365
 
10366
 
10367
@itemize @bullet
10368
@item poly16x8_t vreinterpretq_p16_s8 (int8x16_t)
10369
@end itemize
10370
 
10371
 
10372
@itemize @bullet
10373
@item poly16x8_t vreinterpretq_p16_u64 (uint64x2_t)
10374
@end itemize
10375
 
10376
 
10377
@itemize @bullet
10378
@item poly16x8_t vreinterpretq_p16_s64 (int64x2_t)
10379
@end itemize
10380
 
10381
 
10382
@itemize @bullet
10383
@item poly16x8_t vreinterpretq_p16_f32 (float32x4_t)
10384
@end itemize
10385
 
10386
 
10387
@itemize @bullet
10388
@item poly16x8_t vreinterpretq_p16_p8 (poly8x16_t)
10389
@end itemize
10390
 
10391
 
10392
@itemize @bullet
10393
@item float32x2_t vreinterpret_f32_u32 (uint32x2_t)
10394
@end itemize
10395
 
10396
 
10397
@itemize @bullet
10398
@item float32x2_t vreinterpret_f32_u16 (uint16x4_t)
10399
@end itemize
10400
 
10401
 
10402
@itemize @bullet
10403
@item float32x2_t vreinterpret_f32_u8 (uint8x8_t)
10404
@end itemize
10405
 
10406
 
10407
@itemize @bullet
10408
@item float32x2_t vreinterpret_f32_s32 (int32x2_t)
10409
@end itemize
10410
 
10411
 
10412
@itemize @bullet
10413
@item float32x2_t vreinterpret_f32_s16 (int16x4_t)
10414
@end itemize
10415
 
10416
 
10417
@itemize @bullet
10418
@item float32x2_t vreinterpret_f32_s8 (int8x8_t)
10419
@end itemize
10420
 
10421
 
10422
@itemize @bullet
10423
@item float32x2_t vreinterpret_f32_u64 (uint64x1_t)
10424
@end itemize
10425
 
10426
 
10427
@itemize @bullet
10428
@item float32x2_t vreinterpret_f32_s64 (int64x1_t)
10429
@end itemize
10430
 
10431
 
10432
@itemize @bullet
10433
@item float32x2_t vreinterpret_f32_p16 (poly16x4_t)
10434
@end itemize
10435
 
10436
 
10437
@itemize @bullet
10438
@item float32x2_t vreinterpret_f32_p8 (poly8x8_t)
10439
@end itemize
10440
 
10441
 
10442
@itemize @bullet
10443
@item float32x4_t vreinterpretq_f32_u32 (uint32x4_t)
10444
@end itemize
10445
 
10446
 
10447
@itemize @bullet
10448
@item float32x4_t vreinterpretq_f32_u16 (uint16x8_t)
10449
@end itemize
10450
 
10451
 
10452
@itemize @bullet
10453
@item float32x4_t vreinterpretq_f32_u8 (uint8x16_t)
10454
@end itemize
10455
 
10456
 
10457
@itemize @bullet
10458
@item float32x4_t vreinterpretq_f32_s32 (int32x4_t)
10459
@end itemize
10460
 
10461
 
10462
@itemize @bullet
10463
@item float32x4_t vreinterpretq_f32_s16 (int16x8_t)
10464
@end itemize
10465
 
10466
 
10467
@itemize @bullet
10468
@item float32x4_t vreinterpretq_f32_s8 (int8x16_t)
10469
@end itemize
10470
 
10471
 
10472
@itemize @bullet
10473
@item float32x4_t vreinterpretq_f32_u64 (uint64x2_t)
10474
@end itemize
10475
 
10476
 
10477
@itemize @bullet
10478
@item float32x4_t vreinterpretq_f32_s64 (int64x2_t)
10479
@end itemize
10480
 
10481
 
10482
@itemize @bullet
10483
@item float32x4_t vreinterpretq_f32_p16 (poly16x8_t)
10484
@end itemize
10485
 
10486
 
10487
@itemize @bullet
10488
@item float32x4_t vreinterpretq_f32_p8 (poly8x16_t)
10489
@end itemize
10490
 
10491
 
10492
@itemize @bullet
10493
@item int64x1_t vreinterpret_s64_u32 (uint32x2_t)
10494
@end itemize
10495
 
10496
 
10497
@itemize @bullet
10498
@item int64x1_t vreinterpret_s64_u16 (uint16x4_t)
10499
@end itemize
10500
 
10501
 
10502
@itemize @bullet
10503
@item int64x1_t vreinterpret_s64_u8 (uint8x8_t)
10504
@end itemize
10505
 
10506
 
10507
@itemize @bullet
10508
@item int64x1_t vreinterpret_s64_s32 (int32x2_t)
10509
@end itemize
10510
 
10511
 
10512
@itemize @bullet
10513
@item int64x1_t vreinterpret_s64_s16 (int16x4_t)
10514
@end itemize
10515
 
10516
 
10517
@itemize @bullet
10518
@item int64x1_t vreinterpret_s64_s8 (int8x8_t)
10519
@end itemize
10520
 
10521
 
10522
@itemize @bullet
10523
@item int64x1_t vreinterpret_s64_u64 (uint64x1_t)
10524
@end itemize
10525
 
10526
 
10527
@itemize @bullet
10528
@item int64x1_t vreinterpret_s64_f32 (float32x2_t)
10529
@end itemize
10530
 
10531
 
10532
@itemize @bullet
10533
@item int64x1_t vreinterpret_s64_p16 (poly16x4_t)
10534
@end itemize
10535
 
10536
 
10537
@itemize @bullet
10538
@item int64x1_t vreinterpret_s64_p8 (poly8x8_t)
10539
@end itemize
10540
 
10541
 
10542
@itemize @bullet
10543
@item int64x2_t vreinterpretq_s64_u32 (uint32x4_t)
10544
@end itemize
10545
 
10546
 
10547
@itemize @bullet
10548
@item int64x2_t vreinterpretq_s64_u16 (uint16x8_t)
10549
@end itemize
10550
 
10551
 
10552
@itemize @bullet
10553
@item int64x2_t vreinterpretq_s64_u8 (uint8x16_t)
10554
@end itemize
10555
 
10556
 
10557
@itemize @bullet
10558
@item int64x2_t vreinterpretq_s64_s32 (int32x4_t)
10559
@end itemize
10560
 
10561
 
10562
@itemize @bullet
10563
@item int64x2_t vreinterpretq_s64_s16 (int16x8_t)
10564
@end itemize
10565
 
10566
 
10567
@itemize @bullet
10568
@item int64x2_t vreinterpretq_s64_s8 (int8x16_t)
10569
@end itemize
10570
 
10571
 
10572
@itemize @bullet
10573
@item int64x2_t vreinterpretq_s64_u64 (uint64x2_t)
10574
@end itemize
10575
 
10576
 
10577
@itemize @bullet
10578
@item int64x2_t vreinterpretq_s64_f32 (float32x4_t)
10579
@end itemize
10580
 
10581
 
10582
@itemize @bullet
10583
@item int64x2_t vreinterpretq_s64_p16 (poly16x8_t)
10584
@end itemize
10585
 
10586
 
10587
@itemize @bullet
10588
@item int64x2_t vreinterpretq_s64_p8 (poly8x16_t)
10589
@end itemize
10590
 
10591
 
10592
@itemize @bullet
10593
@item uint64x1_t vreinterpret_u64_u32 (uint32x2_t)
10594
@end itemize
10595
 
10596
 
10597
@itemize @bullet
10598
@item uint64x1_t vreinterpret_u64_u16 (uint16x4_t)
10599
@end itemize
10600
 
10601
 
10602
@itemize @bullet
10603
@item uint64x1_t vreinterpret_u64_u8 (uint8x8_t)
10604
@end itemize
10605
 
10606
 
10607
@itemize @bullet
10608
@item uint64x1_t vreinterpret_u64_s32 (int32x2_t)
10609
@end itemize
10610
 
10611
 
10612
@itemize @bullet
10613
@item uint64x1_t vreinterpret_u64_s16 (int16x4_t)
10614
@end itemize
10615
 
10616
 
10617
@itemize @bullet
10618
@item uint64x1_t vreinterpret_u64_s8 (int8x8_t)
10619
@end itemize
10620
 
10621
 
10622
@itemize @bullet
10623
@item uint64x1_t vreinterpret_u64_s64 (int64x1_t)
10624
@end itemize
10625
 
10626
 
10627
@itemize @bullet
10628
@item uint64x1_t vreinterpret_u64_f32 (float32x2_t)
10629
@end itemize
10630
 
10631
 
10632
@itemize @bullet
10633
@item uint64x1_t vreinterpret_u64_p16 (poly16x4_t)
10634
@end itemize
10635
 
10636
 
10637
@itemize @bullet
10638
@item uint64x1_t vreinterpret_u64_p8 (poly8x8_t)
10639
@end itemize
10640
 
10641
 
10642
@itemize @bullet
10643
@item uint64x2_t vreinterpretq_u64_u32 (uint32x4_t)
10644
@end itemize
10645
 
10646
 
10647
@itemize @bullet
10648
@item uint64x2_t vreinterpretq_u64_u16 (uint16x8_t)
10649
@end itemize
10650
 
10651
 
10652
@itemize @bullet
10653
@item uint64x2_t vreinterpretq_u64_u8 (uint8x16_t)
10654
@end itemize
10655
 
10656
 
10657
@itemize @bullet
10658
@item uint64x2_t vreinterpretq_u64_s32 (int32x4_t)
10659
@end itemize
10660
 
10661
 
10662
@itemize @bullet
10663
@item uint64x2_t vreinterpretq_u64_s16 (int16x8_t)
10664
@end itemize
10665
 
10666
 
10667
@itemize @bullet
10668
@item uint64x2_t vreinterpretq_u64_s8 (int8x16_t)
10669
@end itemize
10670
 
10671
 
10672
@itemize @bullet
10673
@item uint64x2_t vreinterpretq_u64_s64 (int64x2_t)
10674
@end itemize
10675
 
10676
 
10677
@itemize @bullet
10678
@item uint64x2_t vreinterpretq_u64_f32 (float32x4_t)
10679
@end itemize
10680
 
10681
 
10682
@itemize @bullet
10683
@item uint64x2_t vreinterpretq_u64_p16 (poly16x8_t)
10684
@end itemize
10685
 
10686
 
10687
@itemize @bullet
10688
@item uint64x2_t vreinterpretq_u64_p8 (poly8x16_t)
10689
@end itemize
10690
 
10691
 
10692
@itemize @bullet
10693
@item int8x8_t vreinterpret_s8_u32 (uint32x2_t)
10694
@end itemize
10695
 
10696
 
10697
@itemize @bullet
10698
@item int8x8_t vreinterpret_s8_u16 (uint16x4_t)
10699
@end itemize
10700
 
10701
 
10702
@itemize @bullet
10703
@item int8x8_t vreinterpret_s8_u8 (uint8x8_t)
10704
@end itemize
10705
 
10706
 
10707
@itemize @bullet
10708
@item int8x8_t vreinterpret_s8_s32 (int32x2_t)
10709
@end itemize
10710
 
10711
 
10712
@itemize @bullet
10713
@item int8x8_t vreinterpret_s8_s16 (int16x4_t)
10714
@end itemize
10715
 
10716
 
10717
@itemize @bullet
10718
@item int8x8_t vreinterpret_s8_u64 (uint64x1_t)
10719
@end itemize
10720
 
10721
 
10722
@itemize @bullet
10723
@item int8x8_t vreinterpret_s8_s64 (int64x1_t)
10724
@end itemize
10725
 
10726
 
10727
@itemize @bullet
10728
@item int8x8_t vreinterpret_s8_f32 (float32x2_t)
10729
@end itemize
10730
 
10731
 
10732
@itemize @bullet
10733
@item int8x8_t vreinterpret_s8_p16 (poly16x4_t)
10734
@end itemize
10735
 
10736
 
10737
@itemize @bullet
10738
@item int8x8_t vreinterpret_s8_p8 (poly8x8_t)
10739
@end itemize
10740
 
10741
 
10742
@itemize @bullet
10743
@item int8x16_t vreinterpretq_s8_u32 (uint32x4_t)
10744
@end itemize
10745
 
10746
 
10747
@itemize @bullet
10748
@item int8x16_t vreinterpretq_s8_u16 (uint16x8_t)
10749
@end itemize
10750
 
10751
 
10752
@itemize @bullet
10753
@item int8x16_t vreinterpretq_s8_u8 (uint8x16_t)
10754
@end itemize
10755
 
10756
 
10757
@itemize @bullet
10758
@item int8x16_t vreinterpretq_s8_s32 (int32x4_t)
10759
@end itemize
10760
 
10761
 
10762
@itemize @bullet
10763
@item int8x16_t vreinterpretq_s8_s16 (int16x8_t)
10764
@end itemize
10765
 
10766
 
10767
@itemize @bullet
10768
@item int8x16_t vreinterpretq_s8_u64 (uint64x2_t)
10769
@end itemize
10770
 
10771
 
10772
@itemize @bullet
10773
@item int8x16_t vreinterpretq_s8_s64 (int64x2_t)
10774
@end itemize
10775
 
10776
 
10777
@itemize @bullet
10778
@item int8x16_t vreinterpretq_s8_f32 (float32x4_t)
10779
@end itemize
10780
 
10781
 
10782
@itemize @bullet
10783
@item int8x16_t vreinterpretq_s8_p16 (poly16x8_t)
10784
@end itemize
10785
 
10786
 
10787
@itemize @bullet
10788
@item int8x16_t vreinterpretq_s8_p8 (poly8x16_t)
10789
@end itemize
10790
 
10791
 
10792
@itemize @bullet
10793
@item int16x4_t vreinterpret_s16_u32 (uint32x2_t)
10794
@end itemize
10795
 
10796
 
10797
@itemize @bullet
10798
@item int16x4_t vreinterpret_s16_u16 (uint16x4_t)
10799
@end itemize
10800
 
10801
 
10802
@itemize @bullet
10803
@item int16x4_t vreinterpret_s16_u8 (uint8x8_t)
10804
@end itemize
10805
 
10806
 
10807
@itemize @bullet
10808
@item int16x4_t vreinterpret_s16_s32 (int32x2_t)
10809
@end itemize
10810
 
10811
 
10812
@itemize @bullet
10813
@item int16x4_t vreinterpret_s16_s8 (int8x8_t)
10814
@end itemize
10815
 
10816
 
10817
@itemize @bullet
10818
@item int16x4_t vreinterpret_s16_u64 (uint64x1_t)
10819
@end itemize
10820
 
10821
 
10822
@itemize @bullet
10823
@item int16x4_t vreinterpret_s16_s64 (int64x1_t)
10824
@end itemize
10825
 
10826
 
10827
@itemize @bullet
10828
@item int16x4_t vreinterpret_s16_f32 (float32x2_t)
10829
@end itemize
10830
 
10831
 
10832
@itemize @bullet
10833
@item int16x4_t vreinterpret_s16_p16 (poly16x4_t)
10834
@end itemize
10835
 
10836
 
10837
@itemize @bullet
10838
@item int16x4_t vreinterpret_s16_p8 (poly8x8_t)
10839
@end itemize
10840
 
10841
 
10842
@itemize @bullet
10843
@item int16x8_t vreinterpretq_s16_u32 (uint32x4_t)
10844
@end itemize
10845
 
10846
 
10847
@itemize @bullet
10848
@item int16x8_t vreinterpretq_s16_u16 (uint16x8_t)
10849
@end itemize
10850
 
10851
 
10852
@itemize @bullet
10853
@item int16x8_t vreinterpretq_s16_u8 (uint8x16_t)
10854
@end itemize
10855
 
10856
 
10857
@itemize @bullet
10858
@item int16x8_t vreinterpretq_s16_s32 (int32x4_t)
10859
@end itemize
10860
 
10861
 
10862
@itemize @bullet
10863
@item int16x8_t vreinterpretq_s16_s8 (int8x16_t)
10864
@end itemize
10865
 
10866
 
10867
@itemize @bullet
10868
@item int16x8_t vreinterpretq_s16_u64 (uint64x2_t)
10869
@end itemize
10870
 
10871
 
10872
@itemize @bullet
10873
@item int16x8_t vreinterpretq_s16_s64 (int64x2_t)
10874
@end itemize
10875
 
10876
 
10877
@itemize @bullet
10878
@item int16x8_t vreinterpretq_s16_f32 (float32x4_t)
10879
@end itemize
10880
 
10881
 
10882
@itemize @bullet
10883
@item int16x8_t vreinterpretq_s16_p16 (poly16x8_t)
10884
@end itemize
10885
 
10886
 
10887
@itemize @bullet
10888
@item int16x8_t vreinterpretq_s16_p8 (poly8x16_t)
10889
@end itemize
10890
 
10891
 
10892
@itemize @bullet
10893
@item int32x2_t vreinterpret_s32_u32 (uint32x2_t)
10894
@end itemize
10895
 
10896
 
10897
@itemize @bullet
10898
@item int32x2_t vreinterpret_s32_u16 (uint16x4_t)
10899
@end itemize
10900
 
10901
 
10902
@itemize @bullet
10903
@item int32x2_t vreinterpret_s32_u8 (uint8x8_t)
10904
@end itemize
10905
 
10906
 
10907
@itemize @bullet
10908
@item int32x2_t vreinterpret_s32_s16 (int16x4_t)
10909
@end itemize
10910
 
10911
 
10912
@itemize @bullet
10913
@item int32x2_t vreinterpret_s32_s8 (int8x8_t)
10914
@end itemize
10915
 
10916
 
10917
@itemize @bullet
10918
@item int32x2_t vreinterpret_s32_u64 (uint64x1_t)
10919
@end itemize
10920
 
10921
 
10922
@itemize @bullet
10923
@item int32x2_t vreinterpret_s32_s64 (int64x1_t)
10924
@end itemize
10925
 
10926
 
10927
@itemize @bullet
10928
@item int32x2_t vreinterpret_s32_f32 (float32x2_t)
10929
@end itemize
10930
 
10931
 
10932
@itemize @bullet
10933
@item int32x2_t vreinterpret_s32_p16 (poly16x4_t)
10934
@end itemize
10935
 
10936
 
10937
@itemize @bullet
10938
@item int32x2_t vreinterpret_s32_p8 (poly8x8_t)
10939
@end itemize
10940
 
10941
 
10942
@itemize @bullet
10943
@item int32x4_t vreinterpretq_s32_u32 (uint32x4_t)
10944
@end itemize
10945
 
10946
 
10947
@itemize @bullet
10948
@item int32x4_t vreinterpretq_s32_u16 (uint16x8_t)
10949
@end itemize
10950
 
10951
 
10952
@itemize @bullet
10953
@item int32x4_t vreinterpretq_s32_u8 (uint8x16_t)
10954
@end itemize
10955
 
10956
 
10957
@itemize @bullet
10958
@item int32x4_t vreinterpretq_s32_s16 (int16x8_t)
10959
@end itemize
10960
 
10961
 
10962
@itemize @bullet
10963
@item int32x4_t vreinterpretq_s32_s8 (int8x16_t)
10964
@end itemize
10965
 
10966
 
10967
@itemize @bullet
10968
@item int32x4_t vreinterpretq_s32_u64 (uint64x2_t)
10969
@end itemize
10970
 
10971
 
10972
@itemize @bullet
10973
@item int32x4_t vreinterpretq_s32_s64 (int64x2_t)
10974
@end itemize
10975
 
10976
 
10977
@itemize @bullet
10978
@item int32x4_t vreinterpretq_s32_f32 (float32x4_t)
10979
@end itemize
10980
 
10981
 
10982
@itemize @bullet
10983
@item int32x4_t vreinterpretq_s32_p16 (poly16x8_t)
10984
@end itemize
10985
 
10986
 
10987
@itemize @bullet
10988
@item int32x4_t vreinterpretq_s32_p8 (poly8x16_t)
10989
@end itemize
10990
 
10991
 
10992
@itemize @bullet
10993
@item uint8x8_t vreinterpret_u8_u32 (uint32x2_t)
10994
@end itemize
10995
 
10996
 
10997
@itemize @bullet
10998
@item uint8x8_t vreinterpret_u8_u16 (uint16x4_t)
10999
@end itemize
11000
 
11001
 
11002
@itemize @bullet
11003
@item uint8x8_t vreinterpret_u8_s32 (int32x2_t)
11004
@end itemize
11005
 
11006
 
11007
@itemize @bullet
11008
@item uint8x8_t vreinterpret_u8_s16 (int16x4_t)
11009
@end itemize
11010
 
11011
 
11012
@itemize @bullet
11013
@item uint8x8_t vreinterpret_u8_s8 (int8x8_t)
11014
@end itemize
11015
 
11016
 
11017
@itemize @bullet
11018
@item uint8x8_t vreinterpret_u8_u64 (uint64x1_t)
11019
@end itemize
11020
 
11021
 
11022
@itemize @bullet
11023
@item uint8x8_t vreinterpret_u8_s64 (int64x1_t)
11024
@end itemize
11025
 
11026
 
11027
@itemize @bullet
11028
@item uint8x8_t vreinterpret_u8_f32 (float32x2_t)
11029
@end itemize
11030
 
11031
 
11032
@itemize @bullet
11033
@item uint8x8_t vreinterpret_u8_p16 (poly16x4_t)
11034
@end itemize
11035
 
11036
 
11037
@itemize @bullet
11038
@item uint8x8_t vreinterpret_u8_p8 (poly8x8_t)
11039
@end itemize
11040
 
11041
 
11042
@itemize @bullet
11043
@item uint8x16_t vreinterpretq_u8_u32 (uint32x4_t)
11044
@end itemize
11045
 
11046
 
11047
@itemize @bullet
11048
@item uint8x16_t vreinterpretq_u8_u16 (uint16x8_t)
11049
@end itemize
11050
 
11051
 
11052
@itemize @bullet
11053
@item uint8x16_t vreinterpretq_u8_s32 (int32x4_t)
11054
@end itemize
11055
 
11056
 
11057
@itemize @bullet
11058
@item uint8x16_t vreinterpretq_u8_s16 (int16x8_t)
11059
@end itemize
11060
 
11061
 
11062
@itemize @bullet
11063
@item uint8x16_t vreinterpretq_u8_s8 (int8x16_t)
11064
@end itemize
11065
 
11066
 
11067
@itemize @bullet
11068
@item uint8x16_t vreinterpretq_u8_u64 (uint64x2_t)
11069
@end itemize
11070
 
11071
 
11072
@itemize @bullet
11073
@item uint8x16_t vreinterpretq_u8_s64 (int64x2_t)
11074
@end itemize
11075
 
11076
 
11077
@itemize @bullet
11078
@item uint8x16_t vreinterpretq_u8_f32 (float32x4_t)
11079
@end itemize
11080
 
11081
 
11082
@itemize @bullet
11083
@item uint8x16_t vreinterpretq_u8_p16 (poly16x8_t)
11084
@end itemize
11085
 
11086
 
11087
@itemize @bullet
11088
@item uint8x16_t vreinterpretq_u8_p8 (poly8x16_t)
11089
@end itemize
11090
 
11091
 
11092
@itemize @bullet
11093
@item uint16x4_t vreinterpret_u16_u32 (uint32x2_t)
11094
@end itemize
11095
 
11096
 
11097
@itemize @bullet
11098
@item uint16x4_t vreinterpret_u16_u8 (uint8x8_t)
11099
@end itemize
11100
 
11101
 
11102
@itemize @bullet
11103
@item uint16x4_t vreinterpret_u16_s32 (int32x2_t)
11104
@end itemize
11105
 
11106
 
11107
@itemize @bullet
11108
@item uint16x4_t vreinterpret_u16_s16 (int16x4_t)
11109
@end itemize
11110
 
11111
 
11112
@itemize @bullet
11113
@item uint16x4_t vreinterpret_u16_s8 (int8x8_t)
11114
@end itemize
11115
 
11116
 
11117
@itemize @bullet
11118
@item uint16x4_t vreinterpret_u16_u64 (uint64x1_t)
11119
@end itemize
11120
 
11121
 
11122
@itemize @bullet
11123
@item uint16x4_t vreinterpret_u16_s64 (int64x1_t)
11124
@end itemize
11125
 
11126
 
11127
@itemize @bullet
11128
@item uint16x4_t vreinterpret_u16_f32 (float32x2_t)
11129
@end itemize
11130
 
11131
 
11132
@itemize @bullet
11133
@item uint16x4_t vreinterpret_u16_p16 (poly16x4_t)
11134
@end itemize
11135
 
11136
 
11137
@itemize @bullet
11138
@item uint16x4_t vreinterpret_u16_p8 (poly8x8_t)
11139
@end itemize
11140
 
11141
 
11142
@itemize @bullet
11143
@item uint16x8_t vreinterpretq_u16_u32 (uint32x4_t)
11144
@end itemize
11145
 
11146
 
11147
@itemize @bullet
11148
@item uint16x8_t vreinterpretq_u16_u8 (uint8x16_t)
11149
@end itemize
11150
 
11151
 
11152
@itemize @bullet
11153
@item uint16x8_t vreinterpretq_u16_s32 (int32x4_t)
11154
@end itemize
11155
 
11156
 
11157
@itemize @bullet
11158
@item uint16x8_t vreinterpretq_u16_s16 (int16x8_t)
11159
@end itemize
11160
 
11161
 
11162
@itemize @bullet
11163
@item uint16x8_t vreinterpretq_u16_s8 (int8x16_t)
11164
@end itemize
11165
 
11166
 
11167
@itemize @bullet
11168
@item uint16x8_t vreinterpretq_u16_u64 (uint64x2_t)
11169
@end itemize
11170
 
11171
 
11172
@itemize @bullet
11173
@item uint16x8_t vreinterpretq_u16_s64 (int64x2_t)
11174
@end itemize
11175
 
11176
 
11177
@itemize @bullet
11178
@item uint16x8_t vreinterpretq_u16_f32 (float32x4_t)
11179
@end itemize
11180
 
11181
 
11182
@itemize @bullet
11183
@item uint16x8_t vreinterpretq_u16_p16 (poly16x8_t)
11184
@end itemize
11185
 
11186
 
11187
@itemize @bullet
11188
@item uint16x8_t vreinterpretq_u16_p8 (poly8x16_t)
11189
@end itemize
11190
 
11191
 
11192
@itemize @bullet
11193
@item uint32x2_t vreinterpret_u32_u16 (uint16x4_t)
11194
@end itemize
11195
 
11196
 
11197
@itemize @bullet
11198
@item uint32x2_t vreinterpret_u32_u8 (uint8x8_t)
11199
@end itemize
11200
 
11201
 
11202
@itemize @bullet
11203
@item uint32x2_t vreinterpret_u32_s32 (int32x2_t)
11204
@end itemize
11205
 
11206
 
11207
@itemize @bullet
11208
@item uint32x2_t vreinterpret_u32_s16 (int16x4_t)
11209
@end itemize
11210
 
11211
 
11212
@itemize @bullet
11213
@item uint32x2_t vreinterpret_u32_s8 (int8x8_t)
11214
@end itemize
11215
 
11216
 
11217
@itemize @bullet
11218
@item uint32x2_t vreinterpret_u32_u64 (uint64x1_t)
11219
@end itemize
11220
 
11221
 
11222
@itemize @bullet
11223
@item uint32x2_t vreinterpret_u32_s64 (int64x1_t)
11224
@end itemize
11225
 
11226
 
11227
@itemize @bullet
11228
@item uint32x2_t vreinterpret_u32_f32 (float32x2_t)
11229
@end itemize
11230
 
11231
 
11232
@itemize @bullet
11233
@item uint32x2_t vreinterpret_u32_p16 (poly16x4_t)
11234
@end itemize
11235
 
11236
 
11237
@itemize @bullet
11238
@item uint32x2_t vreinterpret_u32_p8 (poly8x8_t)
11239
@end itemize
11240
 
11241
 
11242
@itemize @bullet
11243
@item uint32x4_t vreinterpretq_u32_u16 (uint16x8_t)
11244
@end itemize
11245
 
11246
 
11247
@itemize @bullet
11248
@item uint32x4_t vreinterpretq_u32_u8 (uint8x16_t)
11249
@end itemize
11250
 
11251
 
11252
@itemize @bullet
11253
@item uint32x4_t vreinterpretq_u32_s32 (int32x4_t)
11254
@end itemize
11255
 
11256
 
11257
@itemize @bullet
11258
@item uint32x4_t vreinterpretq_u32_s16 (int16x8_t)
11259
@end itemize
11260
 
11261
 
11262
@itemize @bullet
11263
@item uint32x4_t vreinterpretq_u32_s8 (int8x16_t)
11264
@end itemize
11265
 
11266
 
11267
@itemize @bullet
11268
@item uint32x4_t vreinterpretq_u32_u64 (uint64x2_t)
11269
@end itemize
11270
 
11271
 
11272
@itemize @bullet
11273
@item uint32x4_t vreinterpretq_u32_s64 (int64x2_t)
11274
@end itemize
11275
 
11276
 
11277
@itemize @bullet
11278
@item uint32x4_t vreinterpretq_u32_f32 (float32x4_t)
11279
@end itemize
11280
 
11281
 
11282
@itemize @bullet
11283
@item uint32x4_t vreinterpretq_u32_p16 (poly16x8_t)
11284
@end itemize
11285
 
11286
 
11287
@itemize @bullet
11288
@item uint32x4_t vreinterpretq_u32_p8 (poly8x16_t)
11289
@end itemize
11290
 
11291
 
11292
 
11293
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.