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/* Instruction scheduling pass.

   Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000,

   2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010

   Free Software Foundation, Inc.

   Contributed by Michael Tiemann (tiemann@cygnus.com) Enhanced by,

   and currently maintained by, Jim Wilson (wilson@cygnus.com)

This file is part of GCC.

GCC is free software; you can redistribute it and/or modify it under

the terms of the GNU General Public License as published by the Free

Software Foundation; either version 3, or (at your option) any later

version.

GCC is distributed in the hope that it will be useful, but WITHOUT ANY

WARRANTY; without even the implied warranty of MERCHANTABILITY or

FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License

for more details.

You should have received a copy of the GNU General Public License

along with GCC; see the file COPYING3.  If not see

<http://www.gnu.org/licenses/>.  */

/* Instruction scheduling pass.  This file, along with sched-deps.c,

   contains the generic parts.  The actual entry point is found for

   the normal instruction scheduling pass is found in sched-rgn.c.

   We compute insn priorities based on data dependencies.  Flow

   analysis only creates a fraction of the data-dependencies we must

   observe: namely, only those dependencies which the combiner can be

   expected to use.  For this pass, we must therefore create the

   remaining dependencies we need to observe: register dependencies,

   memory dependencies, dependencies to keep function calls in order,

   and the dependence between a conditional branch and the setting of

   condition codes are all dealt with here.

   The scheduler first traverses the data flow graph, starting with

   the last instruction, and proceeding to the first, assigning values

   to insn_priority as it goes.  This sorts the instructions

   topologically by data dependence.

   Once priorities have been established, we order the insns using

   list scheduling.  This works as follows: starting with a list of

   all the ready insns, and sorted according to priority number, we

   schedule the insn from the end of the list by placing its

   predecessors in the list according to their priority order.  We

   consider this insn scheduled by setting the pointer to the "end" of

   the list to point to the previous insn.  When an insn has no

   predecessors, we either queue it until sufficient time has elapsed

   or add it to the ready list.  As the instructions are scheduled or

   when stalls are introduced, the queue advances and dumps insns into

   the ready list.  When all insns down to the lowest priority have

   been scheduled, the critical path of the basic block has been made

   as short as possible.  The remaining insns are then scheduled in

   remaining slots.

   The following list shows the order in which we want to break ties

   among insns in the ready list:

   1.  choose insn with the longest path to end of bb, ties

   broken by

   2.  choose insn with least contribution to register pressure,

   ties broken by

   3.  prefer in-block upon interblock motion, ties broken by

   4.  prefer useful upon speculative motion, ties broken by

   5.  choose insn with largest control flow probability, ties

   broken by

   6.  choose insn with the least dependences upon the previously

   scheduled insn, or finally

   7   choose the insn which has the most insns dependent on it.

   8.  choose insn with lowest UID.

   Memory references complicate matters.  Only if we can be certain

   that memory references are not part of the data dependency graph

   (via true, anti, or output dependence), can we move operations past

   memory references.  To first approximation, reads can be done

   independently, while writes introduce dependencies.  Better

   approximations will yield fewer dependencies.

   Before reload, an extended analysis of interblock data dependences

   is required for interblock scheduling.  This is performed in

   compute_block_backward_dependences ().

   Dependencies set up by memory references are treated in exactly the

   same way as other dependencies, by using insn backward dependences

   INSN_BACK_DEPS.  INSN_BACK_DEPS are translated into forward dependences

   INSN_FORW_DEPS the purpose of forward list scheduling.

   Having optimized the critical path, we may have also unduly

   extended the lifetimes of some registers.  If an operation requires

   that constants be loaded into registers, it is certainly desirable

   to load those constants as early as necessary, but no earlier.

   I.e., it will not do to load up a bunch of registers at the

   beginning of a basic block only to use them at the end, if they

   could be loaded later, since this may result in excessive register

   utilization.

   Note that since branches are never in basic blocks, but only end

   basic blocks, this pass will not move branches.  But that is ok,

   since we can use GNU's delayed branch scheduling pass to take care

   of this case.

   Also note that no further optimizations based on algebraic

   identities are performed, so this pass would be a good one to

   perform instruction splitting, such as breaking up a multiply

   instruction into shifts and adds where that is profitable.

   Given the memory aliasing analysis that this pass should perform,

   it should be possible to remove redundant stores to memory, and to

   load values from registers instead of hitting memory.

   Before reload, speculative insns are moved only if a 'proof' exists

   that no exception will be caused by this, and if no live registers

   exist that inhibit the motion (live registers constraints are not

   represented by data dependence edges).

   This pass must update information that subsequent passes expect to

   be correct.  Namely: reg_n_refs, reg_n_sets, reg_n_deaths,

   reg_n_calls_crossed, and reg_live_length.  Also, BB_HEAD, BB_END.

   The information in the line number notes is carefully retained by

   this pass.  Notes that refer to the starting and ending of

   exception regions are also carefully retained by this pass.  All

   other NOTE insns are grouped in their same relative order at the

   beginning of basic blocks and regions that have been scheduled.  */

#include "config.h"

#include "system.h"

#include "coretypes.h"

#include "tm.h"

#include "toplev.h"

#include "rtl.h"

#include "tm_p.h"

#include "hard-reg-set.h"

#include "regs.h"

#include "function.h"

#include "flags.h"

#include "insn-config.h"

#include "insn-attr.h"

#include "except.h"

#include "toplev.h"

#include "recog.h"

#include "sched-int.h"

#include "target.h"

#include "output.h"

#include "params.h"

#include "vecprim.h"

#include "dbgcnt.h"

#include "cfgloop.h"

#include "ira.h"

#ifdef INSN_SCHEDULING

/* issue_rate is the number of insns that can be scheduled in the same

   machine cycle.  It can be defined in the config/mach/mach.h file,

   otherwise we set it to 1.  */

int issue_rate;

/* sched-verbose controls the amount of debugging output the

   scheduler prints.  It is controlled by -fsched-verbose=N:

   N>0 and no -DSR : the output is directed to stderr.

   N>=10 will direct the printouts to stderr (regardless of -dSR).

   N=1: same as -dSR.

   N=2: bb's probabilities, detailed ready list info, unit/insn info.

   N=3: rtl at abort point, control-flow, regions info.

   N=5: dependences info.  */

static int sched_verbose_param = 0;

int sched_verbose = 0;

/* Debugging file.  All printouts are sent to dump, which is always set,

   either to stderr, or to the dump listing file (-dRS).  */

FILE *sched_dump = 0;

/* fix_sched_param() is called from toplev.c upon detection

   of the -fsched-verbose=N option.  */

void

fix_sched_param (const char *param, const char *val)

{

  if (!strcmp (param, "verbose"))

    sched_verbose_param = atoi (val);

  else

    warning (0, "fix_sched_param: unknown param: %s", param);

}

/* This is a placeholder for the scheduler parameters common

   to all schedulers.  */

struct common_sched_info_def *common_sched_info;

#define INSN_TICK(INSN) (HID (INSN)->tick)

#define INTER_TICK(INSN) (HID (INSN)->inter_tick)

/* If INSN_TICK of an instruction is equal to INVALID_TICK,

   then it should be recalculated from scratch.  */

#define INVALID_TICK (-(max_insn_queue_index + 1))

/* The minimal value of the INSN_TICK of an instruction.  */

#define MIN_TICK (-max_insn_queue_index)

/* Issue points are used to distinguish between instructions in max_issue ().

   For now, all instructions are equally good.  */

#define ISSUE_POINTS(INSN) 1

/* List of important notes we must keep around.  This is a pointer to the

   last element in the list.  */

rtx note_list;

static struct spec_info_def spec_info_var;

/* Description of the speculative part of the scheduling.

   If NULL - no speculation.  */

spec_info_t spec_info = NULL;

/* True, if recovery block was added during scheduling of current block.

   Used to determine, if we need to fix INSN_TICKs.  */

static bool haifa_recovery_bb_recently_added_p;

/* True, if recovery block was added during this scheduling pass.

   Used to determine if we should have empty memory pools of dependencies

   after finishing current region.  */

bool haifa_recovery_bb_ever_added_p;

/* Counters of different types of speculative instructions.  */

static int nr_begin_data, nr_be_in_data, nr_begin_control, nr_be_in_control;

/* Array used in {unlink, restore}_bb_notes.  */

static rtx *bb_header = 0;

/* Basic block after which recovery blocks will be created.  */

static basic_block before_recovery;

/* Basic block just before the EXIT_BLOCK and after recovery, if we have

   created it.  */

basic_block after_recovery;

/* FALSE if we add bb to another region, so we don't need to initialize it.  */

bool adding_bb_to_current_region_p = true;

/* Queues, etc.  */

/* An instruction is ready to be scheduled when all insns preceding it

   have already been scheduled.  It is important to ensure that all

   insns which use its result will not be executed until its result

   has been computed.  An insn is maintained in one of four structures:

   (P) the "Pending" set of insns which cannot be scheduled until

   their dependencies have been satisfied.

   (Q) the "Queued" set of insns that can be scheduled when sufficient

   time has passed.

   (R) the "Ready" list of unscheduled, uncommitted insns.

   (S) the "Scheduled" list of insns.

   Initially, all insns are either "Pending" or "Ready" depending on

   whether their dependencies are satisfied.

   Insns move from the "Ready" list to the "Scheduled" list as they

   are committed to the schedule.  As this occurs, the insns in the

   "Pending" list have their dependencies satisfied and move to either

   the "Ready" list or the "Queued" set depending on whether

   sufficient time has passed to make them ready.  As time passes,

   insns move from the "Queued" set to the "Ready" list.

   The "Pending" list (P) are the insns in the INSN_FORW_DEPS of the

   unscheduled insns, i.e., those that are ready, queued, and pending.

   The "Queued" set (Q) is implemented by the variable `insn_queue'.

   The "Ready" list (R) is implemented by the variables `ready' and

   `n_ready'.

   The "Scheduled" list (S) is the new insn chain built by this pass.

   The transition (R->S) is implemented in the scheduling loop in

   `schedule_block' when the best insn to schedule is chosen.

   The transitions (P->R and P->Q) are implemented in `schedule_insn' as

   insns move from the ready list to the scheduled list.

   The transition (Q->R) is implemented in 'queue_to_insn' as time

   passes or stalls are introduced.  */

/* Implement a circular buffer to delay instructions until sufficient

   time has passed.  For the new pipeline description interface,

   MAX_INSN_QUEUE_INDEX is a power of two minus one which is not less

   than maximal time of instruction execution computed by genattr.c on

   the base maximal time of functional unit reservations and getting a

   result.  This is the longest time an insn may be queued.  */

static rtx *insn_queue;

static int q_ptr = 0;

static int q_size = 0;

#define NEXT_Q(X) (((X)+1) & max_insn_queue_index)

#define NEXT_Q_AFTER(X, C) (((X)+C) & max_insn_queue_index)

#define QUEUE_SCHEDULED (-3)

#define QUEUE_NOWHERE   (-2)

#define QUEUE_READY     (-1)

/* QUEUE_SCHEDULED - INSN is scheduled.

   QUEUE_NOWHERE   - INSN isn't scheduled yet and is neither in

   queue or ready list.

   QUEUE_READY     - INSN is in ready list.

   N >= 0 - INSN queued for X [where NEXT_Q_AFTER (q_ptr, X) == N] cycles.  */

#define QUEUE_INDEX(INSN) (HID (INSN)->queue_index)

/* The following variable value refers for all current and future

   reservations of the processor units.  */

state_t curr_state;

/* The following variable value is size of memory representing all

   current and future reservations of the processor units.  */

size_t dfa_state_size;

/* The following array is used to find the best insn from ready when

   the automaton pipeline interface is used.  */

char *ready_try = NULL;

/* The ready list.  */

struct ready_list ready = {NULL, 0, 0, 0, 0};

/* The pointer to the ready list (to be removed).  */

static struct ready_list *readyp = &ready;

/* Scheduling clock.  */

static int clock_var;

static int may_trap_exp (const_rtx, int);

/* Nonzero iff the address is comprised from at most 1 register.  */

#define CONST_BASED_ADDRESS_P(x)                        \

  (REG_P (x)                                    \

   || ((GET_CODE (x) == PLUS || GET_CODE (x) == MINUS   \

        || (GET_CODE (x) == LO_SUM))                    \

       && (CONSTANT_P (XEXP (x, 0))                      \

           || CONSTANT_P (XEXP (x, 1)))))

/* Returns a class that insn with GET_DEST(insn)=x may belong to,

   as found by analyzing insn's expression.  */

static int haifa_luid_for_non_insn (rtx x);

/* Haifa version of sched_info hooks common to all headers.  */

const struct common_sched_info_def haifa_common_sched_info =

  {

    NULL, /* fix_recovery_cfg */

    NULL, /* add_block */

    NULL, /* estimate_number_of_insns */

    haifa_luid_for_non_insn, /* luid_for_non_insn */

    SCHED_PASS_UNKNOWN /* sched_pass_id */

  };

const struct sched_scan_info_def *sched_scan_info;

/* Mapping from instruction UID to its Logical UID.  */

VEC (int, heap) *sched_luids = NULL;

/* Next LUID to assign to an instruction.  */

int sched_max_luid = 1;

/* Haifa Instruction Data.  */

VEC (haifa_insn_data_def, heap) *h_i_d = NULL;

void (* sched_init_only_bb) (basic_block, basic_block);

/* Split block function.  Different schedulers might use different functions

   to handle their internal data consistent.  */

basic_block (* sched_split_block) (basic_block, rtx);

/* Create empty basic block after the specified block.  */

basic_block (* sched_create_empty_bb) (basic_block);

static int

may_trap_exp (const_rtx x, int is_store)

{

  enum rtx_code code;

  if (x == 0)

    return TRAP_FREE;

  code = GET_CODE (x);

  if (is_store)

    {

      if (code == MEM && may_trap_p (x))

        return TRAP_RISKY;

      else

        return TRAP_FREE;

    }

  if (code == MEM)

    {

      /* The insn uses memory:  a volatile load.  */

      if (MEM_VOLATILE_P (x))

        return IRISKY;

      /* An exception-free load.  */

      if (!may_trap_p (x))

        return IFREE;

      /* A load with 1 base register, to be further checked.  */

      if (CONST_BASED_ADDRESS_P (XEXP (x, 0)))

        return PFREE_CANDIDATE;

      /* No info on the load, to be further checked.  */

      return PRISKY_CANDIDATE;

    }

  else

    {

      const char *fmt;

      int i, insn_class = TRAP_FREE;

      /* Neither store nor load, check if it may cause a trap.  */

      if (may_trap_p (x))

        return TRAP_RISKY;

      /* Recursive step: walk the insn...  */

      fmt = GET_RTX_FORMAT (code);

      for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)

        {

          if (fmt[i] == 'e')

            {

              int tmp_class = may_trap_exp (XEXP (x, i), is_store);

              insn_class = WORST_CLASS (insn_class, tmp_class);

            }

          else if (fmt[i] == 'E')

            {

              int j;

              for (j = 0; j < XVECLEN (x, i); j++)

                {

                  int tmp_class = may_trap_exp (XVECEXP (x, i, j), is_store);

                  insn_class = WORST_CLASS (insn_class, tmp_class);

                  if (insn_class == TRAP_RISKY || insn_class == IRISKY)

                    break;

                }

            }

          if (insn_class == TRAP_RISKY || insn_class == IRISKY)

            break;

        }

      return insn_class;

    }

}

/* Classifies rtx X of an insn for the purpose of verifying that X can be

   executed speculatively (and consequently the insn can be moved

   speculatively), by examining X, returning:

   TRAP_RISKY: store, or risky non-load insn (e.g. division by variable).

   TRAP_FREE: non-load insn.

   IFREE: load from a globally safe location.

   IRISKY: volatile load.

   PFREE_CANDIDATE, PRISKY_CANDIDATE: load that need to be checked for

   being either PFREE or PRISKY.  */

static int

haifa_classify_rtx (const_rtx x)

{

  int tmp_class = TRAP_FREE;

  int insn_class = TRAP_FREE;

  enum rtx_code code;

  if (GET_CODE (x) == PARALLEL)

    {

      int i, len = XVECLEN (x, 0);

      for (i = len - 1; i >= 0; i--)

        {

          tmp_class = haifa_classify_rtx (XVECEXP (x, 0, i));

          insn_class = WORST_CLASS (insn_class, tmp_class);

          if (insn_class == TRAP_RISKY || insn_class == IRISKY)

            break;

        }

    }

  else

    {

      code = GET_CODE (x);

      switch (code)

        {

        case CLOBBER:

          /* Test if it is a 'store'.  */

          tmp_class = may_trap_exp (XEXP (x, 0), 1);

          break;

        case SET:

          /* Test if it is a store.  */

          tmp_class = may_trap_exp (SET_DEST (x), 1);

          if (tmp_class == TRAP_RISKY)

            break;

          /* Test if it is a load.  */

          tmp_class =

            WORST_CLASS (tmp_class,

                         may_trap_exp (SET_SRC (x), 0));

          break;

        case COND_EXEC:

          tmp_class = haifa_classify_rtx (COND_EXEC_CODE (x));

          if (tmp_class == TRAP_RISKY)

            break;

          tmp_class = WORST_CLASS (tmp_class,

                                   may_trap_exp (COND_EXEC_TEST (x), 0));

          break;

        case TRAP_IF:

          tmp_class = TRAP_RISKY;

          break;

        default:;

        }

      insn_class = tmp_class;

    }

  return insn_class;

}

int

haifa_classify_insn (const_rtx insn)

{

  return haifa_classify_rtx (PATTERN (insn));

}

/* Forward declarations.  */

static int priority (rtx);

static int rank_for_schedule (const void *, const void *);

static void swap_sort (rtx *, int);

static void queue_insn (rtx, int);

static int schedule_insn (rtx);

static void adjust_priority (rtx);

static void advance_one_cycle (void);

static void extend_h_i_d (void);

/* Notes handling mechanism:

   =========================

   Generally, NOTES are saved before scheduling and restored after scheduling.

   The scheduler distinguishes between two types of notes:

   (1) LOOP_BEGIN, LOOP_END, SETJMP, EHREGION_BEG, EHREGION_END notes:

   Before scheduling a region, a pointer to the note is added to the insn

   that follows or precedes it.  (This happens as part of the data dependence

   computation).  After scheduling an insn, the pointer contained in it is

   used for regenerating the corresponding note (in reemit_notes).

   (2) All other notes (e.g. INSN_DELETED):  Before scheduling a block,

   these notes are put in a list (in rm_other_notes() and

   unlink_other_notes ()).  After scheduling the block, these notes are

   inserted at the beginning of the block (in schedule_block()).  */

static void ready_add (struct ready_list *, rtx, bool);

static rtx ready_remove_first (struct ready_list *);

static void queue_to_ready (struct ready_list *);

static int early_queue_to_ready (state_t, struct ready_list *);

static void debug_ready_list (struct ready_list *);

/* The following functions are used to implement multi-pass scheduling

   on the first cycle.  */

static rtx ready_remove (struct ready_list *, int);

static void ready_remove_insn (rtx);

static int choose_ready (struct ready_list *, rtx *);

static void fix_inter_tick (rtx, rtx);

static int fix_tick_ready (rtx);

static void change_queue_index (rtx, int);

/* The following functions are used to implement scheduling of data/control

   speculative instructions.  */

static void extend_h_i_d (void);

static void init_h_i_d (rtx);

static void generate_recovery_code (rtx);

static void process_insn_forw_deps_be_in_spec (rtx, rtx, ds_t);

static void begin_speculative_block (rtx);

static void add_to_speculative_block (rtx);

static void init_before_recovery (basic_block *);

static void create_check_block_twin (rtx, bool);

static void fix_recovery_deps (basic_block);

static void haifa_change_pattern (rtx, rtx);

static void dump_new_block_header (int, basic_block, rtx, rtx);

static void restore_bb_notes (basic_block);

static void fix_jump_move (rtx);

static void move_block_after_check (rtx);

static void move_succs (VEC(edge,gc) **, basic_block);

static void sched_remove_insn (rtx);

static void clear_priorities (rtx, rtx_vec_t *);

static void calc_priorities (rtx_vec_t);

static void add_jump_dependencies (rtx, rtx);

#ifdef ENABLE_CHECKING

static int has_edge_p (VEC(edge,gc) *, int);

static void check_cfg (rtx, rtx);

#endif

#endif /* INSN_SCHEDULING */

/* Point to state used for the current scheduling pass.  */

struct haifa_sched_info *current_sched_info;

#ifndef INSN_SCHEDULING

void

schedule_insns (void)

{

}

#else

/* Do register pressure sensitive insn scheduling if the flag is set

   up.  */

bool sched_pressure_p;

/* Map regno -> its cover class.  The map defined only when

   SCHED_PRESSURE_P is true.  */

enum reg_class *sched_regno_cover_class;

/* The current register pressure.  Only elements corresponding cover

   classes are defined.  */

static int curr_reg_pressure[N_REG_CLASSES];

/* Saved value of the previous array.  */

static int saved_reg_pressure[N_REG_CLASSES];

/* Register living at given scheduling point.  */

static bitmap curr_reg_live;

/* Saved value of the previous array.  */

static bitmap saved_reg_live;

/* Registers mentioned in the current region.  */

static bitmap region_ref_regs;

/* Initiate register pressure relative info for scheduling the current

   region.  Currently it is only clearing register mentioned in the

   current region.  */

void

sched_init_region_reg_pressure_info (void)

{

  bitmap_clear (region_ref_regs);

}

/* Update current register pressure related info after birth (if

   BIRTH_P) or death of register REGNO.  */

static void

mark_regno_birth_or_death (int regno, bool birth_p)

{

  enum reg_class cover_class;

  cover_class = sched_regno_cover_class[regno];

  if (regno >= FIRST_PSEUDO_REGISTER)

    {

      if (cover_class != NO_REGS)

        {

          if (birth_p)

            {

              bitmap_set_bit (curr_reg_live, regno);

              curr_reg_pressure[cover_class]

                += ira_reg_class_nregs[cover_class][PSEUDO_REGNO_MODE (regno)];

            }

          else

            {

              bitmap_clear_bit (curr_reg_live, regno);

              curr_reg_pressure[cover_class]

                -= ira_reg_class_nregs[cover_class][PSEUDO_REGNO_MODE (regno)];

            }

        }

    }

  else if (cover_class != NO_REGS

           && ! TEST_HARD_REG_BIT (ira_no_alloc_regs, regno))

    {

      if (birth_p)

        {

          bitmap_set_bit (curr_reg_live, regno);

          curr_reg_pressure[cover_class]++;

        }

      else

        {

          bitmap_clear_bit (curr_reg_live, regno);

          curr_reg_pressure[cover_class]--;

        }

    }

}

/* Initiate current register pressure related info from living

   registers given by LIVE.  */

static void

initiate_reg_pressure_info (bitmap live)

{

  int i;

  unsigned int j;

  bitmap_iterator bi;

  for (i = 0; i < ira_reg_class_cover_size; i++)

    curr_reg_pressure[ira_reg_class_cover[i]] = 0;

  bitmap_clear (curr_reg_live);

  EXECUTE_IF_SET_IN_BITMAP (live, 0, j, bi)

    if (current_nr_blocks == 1 || bitmap_bit_p (region_ref_regs, j))

      mark_regno_birth_or_death (j, true);

}

/* Mark registers in X as mentioned in the current region.  */

static void

setup_ref_regs (rtx x)

{

  int i, j, regno;

  const RTX_CODE code = GET_CODE (x);

  const char *fmt;

  if (REG_P (x))

    {

      regno = REGNO (x);

      if (regno >= FIRST_PSEUDO_REGISTER)

        bitmap_set_bit (region_ref_regs, REGNO (x));

      else

        for (i = hard_regno_nregs[regno][GET_MODE (x)] - 1; i >= 0; i--)

          bitmap_set_bit (region_ref_regs, regno + i);

      return;

    }

  fmt = GET_RTX_FORMAT (code);

  for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)

    if (fmt[i] == 'e')

      setup_ref_regs (XEXP (x, i));

    else if (fmt[i] == 'E')

      {

        for (j = 0; j < XVECLEN (x, i); j++)

          setup_ref_regs (XVECEXP (x, i, j));

      }

}

/* Initiate current register pressure related info at the start of

   basic block BB.  */

static void

initiate_bb_reg_pressure_info (basic_block bb)

{

  /* JPB 1-Sep-10: Fixed warning. */

#ifdef EH_RETURN_DATA_REGNO

  unsigned int i;

#endif

  rtx insn;

  if (current_nr_blocks > 1)

    FOR_BB_INSNS (bb, insn)

      if (NONDEBUG_INSN_P (insn))

        setup_ref_regs (PATTERN (insn));

  initiate_reg_pressure_info (df_get_live_in (bb));

#ifdef EH_RETURN_DATA_REGNO

  if (bb_has_eh_pred (bb))

    for (i = 0; ; ++i)

      {

        unsigned int regno = EH_RETURN_DATA_REGNO (i);

        if (regno == INVALID_REGNUM)

          break;

        if (! bitmap_bit_p (df_get_live_in (bb), regno))

          mark_regno_birth_or_death (regno, true);

      }

#endif

}

/* Save current register pressure related info.  */

static void

save_reg_pressure (void)

{

  int i;

  for (i = 0; i < ira_reg_class_cover_size; i++)