OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [gnu-stable/] [gcc-4.5.1/] [gcc/] [testsuite/] [gcc.dg/] [guality/] [vla-1.c] - Blame information for rev 826

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 298 jeremybenn
/* PR debug/43150 */
2
/* { dg-do run } */
3
/* { dg-options "-g" } */
4
 
5
void __attribute__((noinline))
6
bar (short *p)
7
{
8
  __builtin_memset (p, '\0', 17 * sizeof (*p));
9
  asm volatile ("" : : "r" (p) : "memory");
10
}
11
 
12
int __attribute__((noinline))
13
f1 (int i)
14
{
15
  char a[i + 1];
16
  a[0] = 5;              /* { dg-final { gdb-test 17 "i" "5" } } */
17
  return a[0];           /* { dg-final { gdb-test 17 "sizeof (a)" "6" } } */
18
}
19
 
20
int __attribute__((noinline))
21
f2 (int i)
22
{
23
  short a[i * 2 + 7];   /* { dg-final { gdb-test 24 "i" "5" } } */
24
  bar (a);              /* { dg-final { gdb-test 24 "sizeof (a)" "17 * sizeof (short)" } } */
25
  return a[i + 4];
26
}
27
 
28
int
29
main ()
30
{
31
  int i = 5;
32
  asm volatile ("" : "=r" (i) : "0" (i));
33
  f1 (i);
34
  f2 (i);
35
  return 0;
36
}

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.