OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [gnu-stable/] [gcc-4.5.1/] [gcc/] [testsuite/] [gcc.dg/] [pr27861-1.c] - Blame information for rev 826

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 298 jeremybenn
/* PR target/27861 */
2
/* The following code used to cause an ICE during RTL expansion, as
3
   expand shift was stripping the SUBREG of a rotate shift count, and
4
   later producing a VAR_DECL tree whose DECL_RTL's mode didn't match
5
   the VAR_DECL's type's mode.  */
6
/* { dg-do compile } */
7
/* { dg-options "-O2" } */
8
 
9
typedef struct sim_state *SIM_DESC;
10
typedef enum
11
{
12
  SIM_OPEN_STANDALONE, SIM_OPEN_DEBUG
13
}
14
SIM_RC;
15
typedef unsigned int unsigned32 __attribute__ ((__mode__ (__SI__)));
16
typedef unsigned int unsigned64 __attribute__ ((__mode__ (__DI__)));
17
typedef unsigned32 unsigned_address;
18
typedef unsigned_address address_word;
19
static __inline__ unsigned64
20
  __attribute__ ((__unused__)) ROTR64 (unsigned64 val, int shift)
21
{
22
  unsigned64 result;
23
  result = (((val) >> (shift)) | ((val) << ((64) - (shift))));
24
  return result;
25
}
26
typedef struct _sim_cpu sim_cpu;
27
enum
28
{
29
    TRACE_MEMORY_IDX, TRACE_MODEL_IDX, TRACE_ALU_IDX, TRACE_CORE_IDX,
30
};
31
typedef struct _trace_data
32
{
33
  char trace_flags[32];
34
}
35
TRACE_DATA;
36
typedef enum
37
{
38
    nr_watchpoint_types,
39
}
40
watchpoint_type;
41
typedef struct _sim_watchpoints
42
{
43
  TRACE_DATA trace_data;
44
}
45
sim_cpu_base;
46
struct _sim_cpu
47
{
48
  sim_cpu_base base;
49
};
50
struct sim_state
51
{
52
  sim_cpu cpu[1];
53
};
54
typedef address_word instruction_address;
55
do_dror (SIM_DESC sd, instruction_address cia, int MY_INDEX, unsigned64 x,
56
         unsigned64 y)
57
{
58
  unsigned64 result;
59
  result = ROTR64 (x, y);
60
    {
61
      if ((((-1) & (1 << (TRACE_ALU_IDX))) != 0
62
           && (((&(((&(sd)->cpu[0])))->base.trace_data))->
63
               trace_flags)[TRACE_ALU_IDX] != 0))
64
        trace_result_word1 (sd, ((&(sd)->cpu[0])), TRACE_ALU_IDX, (result));
65
    }
66
}
67
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.