OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [gnu-stable/] [gcc-4.5.1/] [gcc/] [testsuite/] [gcc.dg/] [pr42246.c] - Blame information for rev 826

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 298 jeremybenn
/* { dg-do compile { target powerpc*-*-* ia64-*-* x86_64-*-* } } */
2
/* { dg-options "-O2 -fselective-scheduling -fsel-sched-pipelining -fsel-sched-pipelining-outer-loops" } */
3
 
4
typedef enum
5
{
6
  empty = 0, pawn = 1, knight = 2, king = 3, bishop = 5, rook = 6, queen = 7
7
}
8
PIECE;
9
extern int p_values[15];
10
extern int *last[65];
11
int
12
Quiesce (int alpha, int beta, int wtm, int ply)
13
{
14
  register int initial_alpha, value, delta;
15
  register int *goodmv, *movep, moves = 0, *sortv, temp;
16
  for (movep = last[ply - 1]; movep < last[ply]; movep++)
17
    if (p_values[(((*movep) >> 15) & 7) + 7] +
18
        p_values[(((*movep) >> 18) & 7) + 7] >= delta)
19
      {
20
        register int done;
21
        register int *end = last[ply - 1] + moves - 1;
22
        do
23
          {
24
            done = 1;
25
            movep = last[ply - 1];
26
            for (; movep < end; movep++, sortv++)
27
              if (*sortv < *(sortv + 1))
28
                {
29
                  *(movep + 1) = temp;
30
                  done = 0;
31
                }
32
          }
33
        while (!done);
34
      }
35
}
36
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.