OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [gnu-stable/] [gcc-4.5.1/] [gcc/] [testsuite/] [gcc.dg/] [prefetch-loop-arrays-1.c] - Blame information for rev 826

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 298 jeremybenn
/* PR tree-optimization/28887 */
2
/* { dg-do compile } */
3
/* { dg-options "-O2 -fprefetch-loop-arrays -w" } */
4
/* { dg-options "-O2 -fprefetch-loop-arrays -march=i686 -msse -w" { target { { i?86-*-* x86_64-*-* } && ilp32 } } } */
5
/* { dg-require-effective-target sse { target { { i?86-*-* x86_64-*-* } && ilp32 } } } */
6
 
7
__extension__ typedef __SIZE_TYPE__ size_t;
8
 
9
struct re_pattern_buffer
10
{
11
  size_t re_nsub;
12
};
13
 
14
typedef enum
15
{
16
  start_memory,
17
} re_opcode_t;
18
 
19
typedef union
20
{
21
  struct
22
  {
23
    unsigned matched_something:1;
24
  } bits;
25
} byte_register_info_type;
26
 
27
void byte_re_match_2_internal (struct re_pattern_buffer *bufp)
28
{
29
  int mcnt;
30
  size_t num_regs = bufp->re_nsub + 1;
31
  byte_register_info_type *reg_info;
32
  for (mcnt = 1; (unsigned) mcnt < num_regs; mcnt++)
33
    {
34
      ((reg_info[mcnt]).bits.matched_something) = 0;
35
    }
36
}
37
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.