URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [gnu-stable/] [gcc-4.5.1/] [gcc/] [testsuite/] [gcc.dg/] [simd-3.c] - Blame information for rev 826

Details | Compare with Previous | View Log


/* { dg-do compile } */
/* { dg-options "-maltivec" { target { powerpc*-*-* && powerpc_altivec_ok } } } */
 
__attribute__ ((vector_size (2))) signed char v1, v2, v3;
void
one (void)
{
  v1 = v2 + v3;
}
 
__attribute__ ((vector_size (8))) signed char v4, v5, v6;
void
two (void)
{
  v4 = v5 + v6;
}

Line No.	Rev	Author	Line
1	298	jeremybenn	`/* { dg-do compile } */`
2			`/* { dg-options "-maltivec" { target { powerpc--* && powerpc_altivec_ok } } } */`
3
4			`__attribute__ ((vector_size (2))) signed char v1, v2, v3;`
5			`void`
6			`one (void)`
7			`{`
8			`v1 = v2 + v3;`
9			`}`
10
11			`__attribute__ ((vector_size (8))) signed char v4, v5, v6;`
12			`void`
13			`two (void)`
14			`{`
15			`v4 = v5 + v6;`
16			`}`

Browse

Tools

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [gnu-stable/] [gcc-4.5.1/] [gcc/] [testsuite/] [gcc.dg/] [simd-3.c] - Blame information for rev 826