OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [gnu-stable/] [gcc-4.5.1/] [gcc/] [testsuite/] [gcc.dg/] [torture/] [cris-asm-mof-1.c] - Blame information for rev 826

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 298 jeremybenn
/* { dg-do compile { target cris-*-* crisv32-*-* } } */
2
/* { dg-skip-if "" { cris*-*-* } { "-march*" } { "" } } */
3
/* { dg-options "-O2 -march=v10" } */
4
/* { dg-final { scan-assembler "in-asm: .mof" } } */
5
/* { dg-final { scan-assembler "out-asm: .mof" } } */
6
/* { dg-final { scan-assembler "in2-asm: .mof" } } */
7
/* { dg-final { scan-assembler "out2-asm: .mof" } } */
8
 
9
unsigned int
10
in (unsigned int i)
11
{
12
  register int i0 asm ("mof") = i;
13
  asm ("in-asm: %0" : : "x" (i0));
14
}
15
 
16
unsigned int
17
out (void)
18
{
19
  register int o asm ("mof");
20
  asm ("out-asm: %0" : "=x" (o));
21
  return o;
22
}
23
 
24
unsigned int
25
in2 (unsigned int i)
26
{
27
  asm ("in2-asm: %0" : : "h" (i));
28
}
29
 
30
unsigned int
31
out2 (void)
32
{
33
  unsigned int o;
34
  asm ("out2-asm: %0" : "=h" (o));
35
  return o;
36
}

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.