OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [gnu-stable/] [gcc-4.5.1/] [gcc/] [testsuite/] [gcc.target/] [alpha/] [asm-1.c] - Blame information for rev 826

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 312 jeremybenn
/* Asm operands that are given as hard registers must keep the same
2
   hard register all the way through compilation.  Example derived
3
   from glibc source.  */
4
/* { dg-do compile } */
5
/* { dg-options "-O2 -frename-registers -fcprop-registers" } */
6
/* { dg-final { scan-assembler "callsys1 .0 .19 .0 .16 .17" } } */
7
/* { dg-final { scan-assembler "callsys2 .0 .19 .0 .16 .17" } } */
8
 
9
struct stat {
10
  int dummy;
11
};
12
 
13
struct kernel_stat {
14
  int dummy;
15
};
16
 
17
extern int xstat_conv (int vers, struct kernel_stat *kbuf, void *ubuf);
18
extern int *__errno_location (void) __attribute__ ((__const__));
19
 
20
int
21
__fxstat (int vers, int fd, struct stat *buf)
22
{
23
  struct kernel_stat kbuf;
24
  int result;
25
 
26
  if (vers == 0)
27
    return
28
      ({
29
        long _sc_ret, _sc_err;
30
        {
31
          register long _sc_0 __asm__("$0");
32
          register long _sc_16 __asm__("$16");
33
          register long _sc_17 __asm__("$17");
34
          register long _sc_19 __asm__("$19");
35
          _sc_0 = 91;
36
          _sc_16 = (long) (fd);
37
          _sc_17 = (long) (((struct kernel_stat *) buf));
38
          __asm__("callsys1 %0 %1 %2 %3 %4"
39
                  : "=r"(_sc_0), "=r"(_sc_19)
40
                  : "0"(_sc_0), "r"(_sc_16), "r"(_sc_17)
41
                  : "$1", "$2", "$3", "$4", "$5", "$6", "$7", "$8",
42
                    "$22", "$23", "$24", "$25", "$27", "$28", "memory");
43
          _sc_ret = _sc_0, _sc_err = _sc_19;
44
        }
45
        if (_sc_err)
46
          {
47
            (*__errno_location ()) = (_sc_ret);
48
            _sc_ret = -1L;
49
          }
50
        _sc_ret;
51
      });
52
 
53
  result =
54
      ({
55
        long _sc_ret, _sc_err;
56
        {
57
          register long _sc_0 __asm__("$0");
58
          register long _sc_16 __asm__("$16");
59
          register long _sc_17 __asm__("$17");
60
          register long _sc_19 __asm__("$19");
61
          _sc_0 = 91;
62
          _sc_16 = (long) (fd);
63
          _sc_17 = (long) ((&kbuf));
64
          __asm__("callsys2 %0 %1 %2 %3 %4"
65
                  : "=r"(_sc_0), "=r"(_sc_19)
66
                  : "0"(_sc_0), "r"(_sc_16), "r"(_sc_17)
67
                  : "$1", "$2", "$3", "$4", "$5", "$6", "$7", "$8",
68
                    "$22", "$23", "$24", "$25", "$27", "$28", "memory");
69
          _sc_ret = _sc_0, _sc_err = _sc_19;
70
        }
71
        if (_sc_err)
72
          {
73
            (*__errno_location ()) = (_sc_ret);
74
            _sc_ret = -1L;
75
          }
76
        _sc_ret;
77
      });
78
  if (result == 0)
79
    result = xstat_conv (vers, &kbuf, buf);
80
 
81
  return result;
82
}

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.