URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [gnu-stable/] [gcc-4.5.1/] [gcc/] [testsuite/] [gcc.target/] [arm/] [fp16-compile-vcvt.c] - Blame information for rev 816

Go to most recent revision | Details | Compare with Previous | View Log


/* { dg-do compile } */
/* { dg-require-effective-target arm_neon_ok } */
/* { dg-options "-mfp16-format=ieee -mfpu=neon-fp16 -mfloat-abi=softfp" } */
 
/* Test generation of VFP __fp16 instructions.  */
 
__fp16 h1 = 0.0;
__fp16 h2 = 1234.0;
float f1 = 2.0;
float f2 = -999.9;
 
void f (void)
{
  h1 = f1;
  f2 = h2;
}
 
/* { dg-final { scan-assembler "\tvcvtb.f32.f16" } } */
/* { dg-final { scan-assembler "\tvcvtb.f16.f32" } } */

Line No.	Rev	Author	Line
1	313	jeremybenn	`/* { dg-do compile } */`
2			`/* { dg-require-effective-target arm_neon_ok } */`
3			`/* { dg-options "-mfp16-format=ieee -mfpu=neon-fp16 -mfloat-abi=softfp" } */`
4
5			`/* Test generation of VFP __fp16 instructions. */`
6
7			`__fp16 h1 = 0.0;`
8			`__fp16 h2 = 1234.0;`
9			`float f1 = 2.0;`
10			`float f2 = -999.9;`
11
12			`void f (void)`
13			`{`
14			`h1 = f1;`
15			`f2 = h2;`
16			`}`
17
18			`/* { dg-final { scan-assembler "\tvcvtb.f32.f16" } } */`
19			`/* { dg-final { scan-assembler "\tvcvtb.f16.f32" } } */`

Browse

Tools

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [gnu-stable/] [gcc-4.5.1/] [gcc/] [testsuite/] [gcc.target/] [arm/] [fp16-compile-vcvt.c] - Blame information for rev 816