OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [gnu-stable/] [gcc-4.5.1/] [gcc/] [testsuite/] [gcc.target/] [ia64/] [sync-1.c] - Blame information for rev 826

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 319 jeremybenn
/* { dg-do compile } */
2
/* { dg-options "-O2" } */
3
/* { dg-final { scan-assembler "xchg4 .*, r0" } } */
4
/* { dg-final { scan-assembler "cmpxchg4.*, r0, .*" } } */
5
/* { dg-final { scan-assembler "cmpxchg8.*, r0, .*" { target lp64 } } } */
6
 
7
int
8
foo1 (int *p)
9
{
10
  return __sync_lock_test_and_set (p, 0);
11
}
12
 
13
int
14
foo2 (int *p, int v)
15
{
16
  return __sync_bool_compare_and_swap (p, v, 0);
17
}
18
 
19
long
20
foo3 (long *p, long v)
21
{
22
  return __sync_bool_compare_and_swap (p, v, 0);
23
}

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.