OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [gnu-stable/] [gcc-4.5.1/] [gcc/] [testsuite/] [gcc.target/] [m68k/] [pr35018.c] - Blame information for rev 816

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 320 jeremybenn
/* { dg-do compile } */
2
/* { dg-options "-Os -mcpu=5249" } */
3
 
4
static inline void vect_add(int *x, int *y, int n)
5
{
6
    asm volatile ("nop;"
7
                : [n] "+d" (n), [x] "+a" (x), [y] "+a" (y)
8
                : : "%d0", "%d1", "%d2", "%d3", "%a0", "%a1", "%a2", "%a3",
9
                    "cc", "memory");
10
}
11
 
12
extern void vect_copy (int *, int *, int);
13
 
14
void vorbis_synthesis_blockin(int *blocksizes)
15
{
16
    int j, *pcm, *p;
17
 
18
    int n=blocksizes[*p]/2;
19
    int n0=blocksizes[0]/2;
20
    int n1=blocksizes[1]/2;
21
 
22
    for(j=0;j<*p;j++)
23
    {
24
        vect_add(p, pcm, n1);
25
        vect_add(pcm, p, n0);
26
        vect_add(p, pcm, n0);
27
        vect_add(p, pcm, n0);
28
        vect_copy(pcm, p, n);
29
    }
30
}
31
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.