OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [gnu-stable/] [gcc-4.5.1/] [gcc/] [testsuite/] [gcc.target/] [mips/] [fpr-moves-3.c] - Blame information for rev 826

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 321 jeremybenn
/* { dg-options "-mabi=32 -mfp64 -O2 -EL" } */
2
 
3
NOMIPS16 double
4
foo (double d)
5
{
6
  register double l1 asm ("$8") = d;
7
  register double l2 asm ("$f20") = 0.0;
8
  asm ("#foo" : "=d" (l1) : "d" (l1));
9
  asm volatile ("#foo" :: "f" (l2));
10
  return l1;
11
}
12
 
13
/* { dg-final { scan-assembler "\tmfc1\t\\\$8,\\\$f12\n" } } */
14
/* { dg-final { scan-assembler "\tmfhc1\t\\\$9,\\\$f12\n" } } */
15
/* { dg-final { scan-assembler "\tmtc1\t\\\$0,\\\$f20\n" } } */
16
/* { dg-final { scan-assembler "\tmthc1\t\\\$0,\\\$f20\n" } } */
17
/* { dg-final { scan-assembler "\tmtc1\t\\\$8,\\\$f0\n" } } */
18
/* { dg-final { scan-assembler "\tmthc1\t\\\$9,\\\$f0\n" } } */

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.