OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [gnu-stable/] [gcc-4.5.1/] [gcc/] [testsuite/] [gcc.target/] [mips/] [fpr-moves-5.c] - Blame information for rev 816

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 321 jeremybenn
/* { dg-options "-mabi=64 -mhard-float -O2 -EL" } */
2
/* { dg-require-effective-target mips_newabi_large_long_double } */
3
 
4
NOMIPS16 void
5
foo (long double d, long double *x)
6
{
7
  *x = d;
8
}
9
 
10
NOMIPS16 long double
11
bar (long double d, long double *x)
12
{
13
  register long double l1 asm ("$8") = d;
14
  register long double l2 asm ("$10") = x[1];
15
  register long double l3 asm ("$f20") = 0.0;
16
  asm ("#foo" : "=d" (l1) : "d" (l1));
17
  asm ("#foo" : "=d" (l2) : "d" (l2));
18
  asm volatile ("#foo" :: "f" (l3));
19
  x[1] = l1;
20
  return l2;
21
}
22
 
23
/* { dg-final { scan-assembler "\tsdc1\t\\\$f12,0\\\(\\\$6\\\)\n" } } */
24
/* { dg-final { scan-assembler "\tsdc1\t\\\$f13,8\\\(\\\$6\\\)\n" } } */
25
/* { dg-final { scan-assembler "\tdmfc1\t\\\$8,\\\$f12\n" } } */
26
/* { dg-final { scan-assembler "\tdmfc1\t\\\$9,\\\$f13\n" } } */
27
/* { dg-final { scan-assembler "\tld\t\\\$10,16\\\(\\\$6\\\)\n" } } */
28
/* { dg-final { scan-assembler "\tld\t\\\$11,24\\\(\\\$6\\\)\n" } } */
29
/* { dg-final { scan-assembler "\tdmtc1\t\\\$0,\\\$f20\n" } } */
30
/* { dg-final { scan-assembler "\tdmtc1\t\\\$0,\\\$f21\n" } } */
31
/* { dg-final { scan-assembler "\tsd\t\\\$8,16\\\(\\\$6\\\)\n" } } */
32
/* { dg-final { scan-assembler "\tsd\t\\\$9,24\\\(\\\$6\\\)\n" } } */
33
/* { dg-final { scan-assembler "\tdmtc1\t\\\$10,\\\$f0\n" } } */
34
/* { dg-final { scan-assembler "\tdmtc1\t\\\$11,\\\$f2\n" } } */

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.