OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [gnu-stable/] [gcc-4.5.1/] [gcc/] [testsuite/] [gcc.target/] [mips/] [r10k-cache-barrier-5.c] - Blame information for rev 826

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 321 jeremybenn
/* { dg-options "-O2 -mr10k-cache-barrier=store -mno-abicalls -mabi=64" } */
2
 
3
/* Test that in-range stores to static objects do not get an unnecessary
4
   cache barrier.  */
5
 
6
int x[4];
7
void bar (void);
8
 
9
NOMIPS16 void
10
foo (int n)
11
{
12
  while (n--)
13
    {
14
      x[3] = 1;
15
      bar ();
16
    }
17
}
18
 
19
/* { dg-final { scan-assembler-not "\tcache\t" } } */

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.