OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [gnu-stable/] [gcc-4.5.1/] [gcc/] [testsuite/] [gcc.target/] [powerpc/] [altivec-27.c] - Blame information for rev 859

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 322 jeremybenn
/* { dg-do compile { target powerpc*-*-* } } */
2
/* { dg-require-effective-target powerpc_altivec_ok } */
3
/* { dg-options "-maltivec" } */
4
 
5
#define f0() void x0 (vector float x) { }
6
f0 ()
7
 
8
#define f1(type) void x1##type (vector type x) { }
9
f1 (float)
10
 
11
#define f2(v, type) void x2##type (v type x) { }
12
f2 (vector, float)
13
 
14
#define f3(type) void x3##type (vector bool type x) { }
15
f3 (int)
16
 
17
#define f4(v, type) void x4##type (v bool type x) { }
18
f4 (vector, int)
19
 
20
#define f5(b, type) void x5##type (vector b type x) { }
21
f5 (bool, int)
22
 
23
#define f6(v, b, type) void x6##type (v b type x) { }
24
f6 (vector, bool, int)
25
 
26
#define f7(v, b, type) void x7##type (v type b x) { }
27
f7 (vector, bool, int)
28
 
29
int vector = 6;
30
 
31
#define v1(v) int x8 (int v) { return v; }
32
v1(vector)

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.