OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [gnu-stable/] [gcc-4.5.1/] [gcc/] [testsuite/] [gcc.target/] [powerpc/] [asm-es-2.c] - Blame information for rev 826

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 322 jeremybenn 
/* { dg-options "-O2" } */
2 
void
3 
f1 (int *p, int x)
4 
{
5 
  asm ("asm1 %0" : "=es" (p[x]));
6 
}
7 
 
8 
void
9 
f2 (int *p)
10 
{
11 
  while (1)
12 
    {
13 
      p += 4;
14 
      asm ("asm2%U0 %0" : "=m" (*p));
15 
    }
16 
}
17 
 
18 
void
19 
f3 (int *p)
20 
{
21 
  while (1)
22 
    {
23 
      p += 4;
24 
      asm ("asm3%U0 %0" : "=es" (*p));
25 
    }
26 
}
27 
 
28 
void
29 
f4 (int *p)
30 
{
31 
  asm ("asm4 %0" : "=es" (p[100]));
32 
}
33 
 
34 
/* { dg-final { scan-assembler "asm1 3,4" } } */
35 
/* { dg-final { scan-assembler "asm2u 16\\(3\\)" } } */
36 
/* { dg-final { scan-assembler "asm3 0\\(3\\)" } } */
37 
/* { dg-final { scan-assembler "asm4 400\\(3\\)" } } */

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.