OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [gnu-stable/] [gcc-4.5.1/] [gcc/] [testsuite/] [gcc.target/] [powerpc/] [ppc-mov-1.c] - Blame information for rev 859

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 322 jeremybenn
/* { dg-do compile { target { powerpc*-*-* && lp64 } } } */
2
/* { dg-options "-O2" } */
3
 
4
/* { dg-final { scan-assembler-not "fmr \[0-9\]+,\[0-9\]+" } }
5
 
6
/* Origin:Pete Steinmetz <steinmtz@us.ibm.com> */
7
 
8
/* PR 16796: Extraneous move.  */
9
 
10
static const double huge = 1.0e300;
11
typedef int int64_t __attribute__ ((__mode__ (__DI__)));
12
typedef unsigned int u_int64_t __attribute__ ((__mode__ (__DI__)));
13
 
14
double __floor(double x)
15
{
16
  union {
17
    double dbl_val;
18
    long int long_val;
19
  } temp;
20
 
21
  int64_t i0,j0;
22
  u_int64_t i;
23
  temp.dbl_val = x;
24
  i0 = temp.long_val;
25
 
26
  j0 = ((i0>>52)&0x7ff)-0x3ff;
27
  if(j0<52) {
28
    if(j0<0) {
29
      if(huge+x>0.0) {
30
        if(i0>=0) {i0=0;}
31
        else if((i0&0x7fffffffffffffff)!=0)
32
        { i0=0xbff0000000000000;}
33
      }
34
    } else {
35
      i = (0x000fffffffffffff)>>j0;
36
      if((i0&i)==0) return x;
37
      if(huge+x>0.0) {
38
        if(i0<0) i0 += (0x0010000000000000)>>j0;
39
        i0 &= (~i);
40
      }
41
    }
42
  } else {
43
    if (j0==0x400)
44
      return x+x;
45
    else
46
      return x;
47
  }
48
  temp.long_val = i0;
49
  x = temp.dbl_val;
50
  return x;
51
}
52
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.