OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [gnu-stable/] [gcc-4.5.1/] [gcc/] [testsuite/] [gcc.target/] [rx/] [zero-width-bitfield.c] - Blame information for rev 816

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 323 jeremybenn
/* { dg-do run { xfail rx-*-* } } */
2
/* { dg-skip-if "skipped until patch for generic zero=width bit-field handling is accepted" { rx-*-* } { "*" } { "" } } */
3
/* { dg-options "-msim" } */
4
/* Note: The -msim abiove is actually there to override the default
5
   options which do not allow the GCC extension of zero-width bitfields.  */
6
 
7
extern void abort (void);
8
extern void exit  (int);
9
 
10
struct S_zero
11
{
12
  int   f1: 4;
13
  int   f2: 0;
14
  short f3: 4;
15
} S_zero;
16
 
17
struct S_norm
18
{
19
  int   f1: 4;
20
  short f3: 4;
21
} S_norm;
22
 
23
 
24
int
25
main (void)
26
{
27
  if (sizeof (S_zero) != 4 || sizeof (S_norm) != 8)
28
    abort ();
29
 
30
  exit (0);
31
  return 0;
32
}

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.