Subversion Repositories openrisc

/* Xtensa configuration-specific ISA information.

   Copyright 2003, 2004, 2005 Free Software Foundation, Inc.

   This file is part of BFD, the Binary File Descriptor library.

   This program is free software; you can redistribute it and/or

   modify it under the terms of the GNU General Public License as

   published by the Free Software Foundation; either version 2 of the

   License, or (at your option) any later version.

   This program is distributed in the hope that it will be useful,

   but WITHOUT ANY WARRANTY; without even the implied warranty of

   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU

   General Public License for more details.

   You should have received a copy of the GNU General Public License

   along with this program; if not, write to the Free Software

   Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA

   02110-1301, USA.  */

#include "ansidecl.h"

#include <xtensa-isa.h>

#include "xtensa-isa-internal.h"

/* Sysregs.  */

static xtensa_sysreg_internal sysregs[] = {

  { "LBEG", 0, 0 },

  { "LEND", 1, 0 },

  { "LCOUNT", 2, 0 },

  { "BR", 4, 0 },

  { "ACCLO", 16, 0 },

  { "ACCHI", 17, 0 },

  { "M0", 32, 0 },

  { "M1", 33, 0 },

  { "M2", 34, 0 },

  { "M3", 35, 0 },

  { "PTEVADDR", 83, 0 },

  { "MMID", 89, 0 },

  { "DDR", 104, 0 },

  { "176", 176, 0 },

  { "208", 208, 0 },

  { "INTERRUPT", 226, 0 },

  { "INTCLEAR", 227, 0 },

  { "CCOUNT", 234, 0 },

  { "PRID", 235, 0 },

  { "ICOUNT", 236, 0 },

  { "CCOMPARE0", 240, 0 },

  { "CCOMPARE1", 241, 0 },

  { "CCOMPARE2", 242, 0 },

  { "VECBASE", 231, 0 },

  { "EPC1", 177, 0 },

  { "EPC2", 178, 0 },

  { "EPC3", 179, 0 },

  { "EPC4", 180, 0 },

  { "EPC5", 181, 0 },

  { "EPC6", 182, 0 },

  { "EPC7", 183, 0 },

  { "EXCSAVE1", 209, 0 },

  { "EXCSAVE2", 210, 0 },

  { "EXCSAVE3", 211, 0 },

  { "EXCSAVE4", 212, 0 },

  { "EXCSAVE5", 213, 0 },

  { "EXCSAVE6", 214, 0 },

  { "EXCSAVE7", 215, 0 },

  { "EPS2", 194, 0 },

  { "EPS3", 195, 0 },

  { "EPS4", 196, 0 },

  { "EPS5", 197, 0 },

  { "EPS6", 198, 0 },

  { "EPS7", 199, 0 },

  { "EXCCAUSE", 232, 0 },

  { "DEPC", 192, 0 },

  { "EXCVADDR", 238, 0 },

  { "WINDOWBASE", 72, 0 },

  { "WINDOWSTART", 73, 0 },

  { "SAR", 3, 0 },

  { "LITBASE", 5, 0 },

  { "PS", 230, 0 },

  { "MISC0", 244, 0 },

  { "MISC1", 245, 0 },

  { "MISC2", 246, 0 },

  { "MISC3", 247, 0 },

  { "INTENABLE", 228, 0 },

  { "DBREAKA0", 144, 0 },

  { "DBREAKC0", 160, 0 },

  { "DBREAKA1", 145, 0 },

  { "DBREAKC1", 161, 0 },

  { "IBREAKA0", 128, 0 },

  { "IBREAKA1", 129, 0 },

  { "IBREAKENABLE", 96, 0 },

  { "ICOUNTLEVEL", 237, 0 },

  { "DEBUGCAUSE", 233, 0 },

  { "RASID", 90, 0 },

  { "ITLBCFG", 91, 0 },

  { "DTLBCFG", 92, 0 },

  { "CPENABLE", 224, 0 },

  { "SCOMPARE1", 12, 0 },

  { "THREADPTR", 231, 1 },

  { "FCR", 232, 1 },

  { "FSR", 233, 1 }

};

#define NUM_SYSREGS 74

#define MAX_SPECIAL_REG 247

#define MAX_USER_REG 233

/* Processor states.  */

static xtensa_state_internal states[] = {

  { "LCOUNT", 32, 0 },

  { "PC", 32, 0 },

  { "ICOUNT", 32, 0 },

  { "DDR", 32, 0 },

  { "INTERRUPT", 32, 0 },

  { "CCOUNT", 32, 0 },

  { "XTSYNC", 1, 0 },

  { "VECBASE", 22, 0 },

  { "EPC1", 32, 0 },

  { "EPC2", 32, 0 },

  { "EPC3", 32, 0 },

  { "EPC4", 32, 0 },

  { "EPC5", 32, 0 },

  { "EPC6", 32, 0 },

  { "EPC7", 32, 0 },

  { "EXCSAVE1", 32, 0 },

  { "EXCSAVE2", 32, 0 },

  { "EXCSAVE3", 32, 0 },

  { "EXCSAVE4", 32, 0 },

  { "EXCSAVE5", 32, 0 },

  { "EXCSAVE6", 32, 0 },

  { "EXCSAVE7", 32, 0 },

  { "EPS2", 15, 0 },

  { "EPS3", 15, 0 },

  { "EPS4", 15, 0 },

  { "EPS5", 15, 0 },

  { "EPS6", 15, 0 },

  { "EPS7", 15, 0 },

  { "EXCCAUSE", 6, 0 },

  { "PSINTLEVEL", 4, 0 },

  { "PSUM", 1, 0 },

  { "PSWOE", 1, 0 },

  { "PSRING", 2, 0 },

  { "PSEXCM", 1, 0 },

  { "DEPC", 32, 0 },

  { "EXCVADDR", 32, 0 },

  { "WindowBase", 4, 0 },

  { "WindowStart", 16, 0 },

  { "PSCALLINC", 2, 0 },

  { "PSOWB", 4, 0 },

  { "LBEG", 32, 0 },

  { "LEND", 32, 0 },

  { "SAR", 6, 0 },

  { "THREADPTR", 32, 0 },

  { "LITBADDR", 20, 0 },

  { "LITBEN", 1, 0 },

  { "MISC0", 32, 0 },

  { "MISC1", 32, 0 },

  { "MISC2", 32, 0 },

  { "MISC3", 32, 0 },

  { "ACC", 40, 0 },

  { "InOCDMode", 1, 0 },

  { "INTENABLE", 32, 0 },

  { "DBREAKA0", 32, 0 },

  { "DBREAKC0", 8, 0 },

  { "DBREAKA1", 32, 0 },

  { "DBREAKC1", 8, 0 },

  { "IBREAKA0", 32, 0 },

  { "IBREAKA1", 32, 0 },

  { "IBREAKENABLE", 2, 0 },

  { "ICOUNTLEVEL", 4, 0 },

  { "DEBUGCAUSE", 6, 0 },

  { "DBNUM", 4, 0 },

  { "CCOMPARE0", 32, 0 },

  { "CCOMPARE1", 32, 0 },

  { "CCOMPARE2", 32, 0 },

  { "ASID3", 8, 0 },

  { "ASID2", 8, 0 },

  { "ASID1", 8, 0 },

  { "INSTPGSZID4", 2, 0 },

  { "DATAPGSZID4", 2, 0 },

  { "PTBASE", 10, 0 },

  { "CPENABLE", 1, 0 },

  { "SCOMPARE1", 32, 0 },

  { "RoundMode", 2, 0 },

  { "InvalidEnable", 1, 0 },

  { "DivZeroEnable", 1, 0 },

  { "OverflowEnable", 1, 0 },

  { "UnderflowEnable", 1, 0 },

  { "InexactEnable", 1, 0 },

  { "InvalidFlag", 1, 0 },

  { "DivZeroFlag", 1, 0 },

  { "OverflowFlag", 1, 0 },

  { "UnderflowFlag", 1, 0 },

  { "InexactFlag", 1, 0 },

  { "FPreserved20", 20, 0 },

  { "FPreserved20a", 20, 0 },

  { "FPreserved5", 5, 0 },

  { "FPreserved7", 7, 0 }

};

#define NUM_STATES 89

/* Macros for xtensa_state numbers (for use in iclasses because the

   state numbers are not available when the iclass table is generated).  */

#define STATE_LCOUNT 0

#define STATE_PC 1

#define STATE_ICOUNT 2

#define STATE_DDR 3

#define STATE_INTERRUPT 4

#define STATE_CCOUNT 5

#define STATE_XTSYNC 6

#define STATE_VECBASE 7

#define STATE_EPC1 8

#define STATE_EPC2 9

#define STATE_EPC3 10

#define STATE_EPC4 11

#define STATE_EPC5 12

#define STATE_EPC6 13

#define STATE_EPC7 14

#define STATE_EXCSAVE1 15

#define STATE_EXCSAVE2 16

#define STATE_EXCSAVE3 17

#define STATE_EXCSAVE4 18

#define STATE_EXCSAVE5 19

#define STATE_EXCSAVE6 20

#define STATE_EXCSAVE7 21

#define STATE_EPS2 22

#define STATE_EPS3 23

#define STATE_EPS4 24

#define STATE_EPS5 25

#define STATE_EPS6 26

#define STATE_EPS7 27

#define STATE_EXCCAUSE 28

#define STATE_PSINTLEVEL 29

#define STATE_PSUM 30

#define STATE_PSWOE 31

#define STATE_PSRING 32

#define STATE_PSEXCM 33

#define STATE_DEPC 34

#define STATE_EXCVADDR 35

#define STATE_WindowBase 36

#define STATE_WindowStart 37

#define STATE_PSCALLINC 38

#define STATE_PSOWB 39

#define STATE_LBEG 40

#define STATE_LEND 41

#define STATE_SAR 42

#define STATE_THREADPTR 43

#define STATE_LITBADDR 44

#define STATE_LITBEN 45

#define STATE_MISC0 46

#define STATE_MISC1 47

#define STATE_MISC2 48

#define STATE_MISC3 49

#define STATE_ACC 50

#define STATE_InOCDMode 51

#define STATE_INTENABLE 52

#define STATE_DBREAKA0 53

#define STATE_DBREAKC0 54

#define STATE_DBREAKA1 55

#define STATE_DBREAKC1 56

#define STATE_IBREAKA0 57

#define STATE_IBREAKA1 58

#define STATE_IBREAKENABLE 59

#define STATE_ICOUNTLEVEL 60

#define STATE_DEBUGCAUSE 61

#define STATE_DBNUM 62

#define STATE_CCOMPARE0 63

#define STATE_CCOMPARE1 64

#define STATE_CCOMPARE2 65

#define STATE_ASID3 66

#define STATE_ASID2 67

#define STATE_ASID1 68

#define STATE_INSTPGSZID4 69

#define STATE_DATAPGSZID4 70

#define STATE_PTBASE 71

#define STATE_CPENABLE 72

#define STATE_SCOMPARE1 73

#define STATE_RoundMode 74

#define STATE_InvalidEnable 75

#define STATE_DivZeroEnable 76

#define STATE_OverflowEnable 77

#define STATE_UnderflowEnable 78

#define STATE_InexactEnable 79

#define STATE_InvalidFlag 80

#define STATE_DivZeroFlag 81

#define STATE_OverflowFlag 82

#define STATE_UnderflowFlag 83

#define STATE_InexactFlag 84

#define STATE_FPreserved20 85

#define STATE_FPreserved20a 86

#define STATE_FPreserved5 87

#define STATE_FPreserved7 88

/* Field definitions.  */

static unsigned

Field_t_Slot_inst_get (const xtensa_insnbuf insn)

{

  unsigned tie_t = 0;

  tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);

  return tie_t;

}

static void

Field_t_Slot_inst_set (xtensa_insnbuf insn, uint32 val)

{

  uint32 tie_t;

  tie_t = (val << 28) >> 28;

  insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);

}

static unsigned

Field_t_Slot_inst16a_get (const xtensa_insnbuf insn)

{

  unsigned tie_t = 0;

  tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);

  return tie_t;

}

static void

Field_t_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)

{

  uint32 tie_t;

  tie_t = (val << 28) >> 28;

  insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);

}

static unsigned

Field_t_Slot_inst16b_get (const xtensa_insnbuf insn)

{

  unsigned tie_t = 0;

  tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);

  return tie_t;

}

static void

Field_t_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)

{

  uint32 tie_t;

  tie_t = (val << 28) >> 28;

  insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);

}

static unsigned

Field_t_Slot_xt_flix64_slot0_get (const xtensa_insnbuf insn)

{

  unsigned tie_t = 0;

  tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);

  return tie_t;

}

static void

Field_t_Slot_xt_flix64_slot0_set (xtensa_insnbuf insn, uint32 val)

{

  uint32 tie_t;

  tie_t = (val << 28) >> 28;

  insn[0] = (insn[0] & ~0xf) | (tie_t << 0);

}

static unsigned

Field_t_Slot_xt_flix64_slot1_get (const xtensa_insnbuf insn)

{

  unsigned tie_t = 0;

  tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);

  return tie_t;

}

static void

Field_t_Slot_xt_flix64_slot1_set (xtensa_insnbuf insn, uint32 val)

{

  uint32 tie_t;

  tie_t = (val << 28) >> 28;

  insn[0] = (insn[0] & ~0xf) | (tie_t << 0);

}

static unsigned

Field_t_Slot_xt_flix64_slot2_get (const xtensa_insnbuf insn)

{

  unsigned tie_t = 0;

  tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);

  return tie_t;

}

static void

Field_t_Slot_xt_flix64_slot2_set (xtensa_insnbuf insn, uint32 val)

{

  uint32 tie_t;

  tie_t = (val << 28) >> 28;

  insn[0] = (insn[0] & ~0xf) | (tie_t << 0);

}

static unsigned

Field_t_Slot_xt_flix64_slot3_get (const xtensa_insnbuf insn)

{

  unsigned tie_t = 0;

  tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);

  return tie_t;

}

static void

Field_t_Slot_xt_flix64_slot3_set (xtensa_insnbuf insn, uint32 val)

{

  uint32 tie_t;

  tie_t = (val << 28) >> 28;

  insn[0] = (insn[0] & ~0xf) | (tie_t << 0);

}

static unsigned

Field_bbi4_Slot_inst_get (const xtensa_insnbuf insn)

{

  unsigned tie_t = 0;

  tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31);

  return tie_t;

}

static void

Field_bbi4_Slot_inst_set (xtensa_insnbuf insn, uint32 val)

{

  uint32 tie_t;

  tie_t = (val << 31) >> 31;

  insn[0] = (insn[0] & ~0x1000) | (tie_t << 12);

}

static unsigned

Field_bbi_Slot_inst_get (const xtensa_insnbuf insn)

{

  unsigned tie_t = 0;

  tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31);

  tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);

  return tie_t;

}

static void

Field_bbi_Slot_inst_set (xtensa_insnbuf insn, uint32 val)

{

  uint32 tie_t;

  tie_t = (val << 28) >> 28;

  insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);

  tie_t = (val << 27) >> 31;

  insn[0] = (insn[0] & ~0x1000) | (tie_t << 12);

}

static unsigned

Field_bbi_Slot_xt_flix64_slot3_get (const xtensa_insnbuf insn)

{

  unsigned tie_t = 0;

  tie_t = (tie_t << 1) | ((insn[0] << 5) >> 31);

  tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);

  return tie_t;

}

static void

Field_bbi_Slot_xt_flix64_slot3_set (xtensa_insnbuf insn, uint32 val)

{

  uint32 tie_t;

  tie_t = (val << 28) >> 28;

  insn[0] = (insn[0] & ~0xf) | (tie_t << 0);

  tie_t = (val << 27) >> 31;

  insn[0] = (insn[0] & ~0x4000000) | (tie_t << 26);

}

static unsigned

Field_imm12_Slot_inst_get (const xtensa_insnbuf insn)

{

  unsigned tie_t = 0;

  tie_t = (tie_t << 12) | ((insn[0] << 8) >> 20);

  return tie_t;

}

static void

Field_imm12_Slot_inst_set (xtensa_insnbuf insn, uint32 val)

{

  uint32 tie_t;

  tie_t = (val << 20) >> 20;

  insn[0] = (insn[0] & ~0xfff000) | (tie_t << 12);

}

static unsigned

Field_imm8_Slot_inst_get (const xtensa_insnbuf insn)

{

  unsigned tie_t = 0;

  tie_t = (tie_t << 8) | ((insn[0] << 8) >> 24);

  return tie_t;

}

static void

Field_imm8_Slot_inst_set (xtensa_insnbuf insn, uint32 val)

{

  uint32 tie_t;

  tie_t = (val << 24) >> 24;

  insn[0] = (insn[0] & ~0xff0000) | (tie_t << 16);

}

static unsigned

Field_imm8_Slot_xt_flix64_slot0_get (const xtensa_insnbuf insn)

{

  unsigned tie_t = 0;

  tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);

  return tie_t;

}

static void

Field_imm8_Slot_xt_flix64_slot0_set (xtensa_insnbuf insn, uint32 val)

{

  uint32 tie_t;

  tie_t = (val << 24) >> 24;

  insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);

}

static unsigned

Field_imm8_Slot_xt_flix64_slot1_get (const xtensa_insnbuf insn)

{

  unsigned tie_t = 0;

  tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);

  tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);

  return tie_t;

}

static void

Field_imm8_Slot_xt_flix64_slot1_set (xtensa_insnbuf insn, uint32 val)

{

  uint32 tie_t;

  tie_t = (val << 28) >> 28;

  insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);

  tie_t = (val << 24) >> 28;

  insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);

}

static unsigned

Field_s_Slot_inst_get (const xtensa_insnbuf insn)

{

  unsigned tie_t = 0;

  tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);

  return tie_t;

}

static void

Field_s_Slot_inst_set (xtensa_insnbuf insn, uint32 val)

{

  uint32 tie_t;

  tie_t = (val << 28) >> 28;

  insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);

}

static unsigned

Field_s_Slot_inst16a_get (const xtensa_insnbuf insn)

{

  unsigned tie_t = 0;

  tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);

  return tie_t;

}

static void

Field_s_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)

{

  uint32 tie_t;

  tie_t = (val << 28) >> 28;

  insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);

}

static unsigned

Field_s_Slot_inst16b_get (const xtensa_insnbuf insn)

{

  unsigned tie_t = 0;