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/* Target-dependent code for the Fujitsu FR-V, for GDB, the GNU Debugger.

   Copyright (C) 2002, 2003, 2004, 2005, 2007, 2008, 2009, 2010

   Free Software Foundation, Inc.

   This file is part of GDB.

   This program is free software; you can redistribute it and/or modify

   it under the terms of the GNU General Public License as published by

   the Free Software Foundation; either version 3 of the License, or

   (at your option) any later version.

   This program is distributed in the hope that it will be useful,

   but WITHOUT ANY WARRANTY; without even the implied warranty of

   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

   GNU General Public License for more details.

   You should have received a copy of the GNU General Public License

   along with this program.  If not, see <http://www.gnu.org/licenses/>.  */

#include "defs.h"

#include "gdb_string.h"

#include "inferior.h"

#include "gdbcore.h"

#include "arch-utils.h"

#include "regcache.h"

#include "frame.h"

#include "frame-unwind.h"

#include "frame-base.h"

#include "trad-frame.h"

#include "dis-asm.h"

#include "gdb_assert.h"

#include "sim-regno.h"

#include "gdb/sim-frv.h"

#include "opcodes/frv-desc.h"   /* for the H_SPR_... enums */

#include "symtab.h"

#include "elf-bfd.h"

#include "elf/frv.h"

#include "osabi.h"

#include "infcall.h"

#include "solib.h"

#include "frv-tdep.h"

extern void _initialize_frv_tdep (void);

struct frv_unwind_cache         /* was struct frame_extra_info */

  {

    /* The previous frame's inner-most stack address.  Used as this

       frame ID's stack_addr.  */

    CORE_ADDR prev_sp;

    /* The frame's base, optionally used by the high-level debug info.  */

    CORE_ADDR base;

    /* Table indicating the location of each and every register.  */

    struct trad_frame_saved_reg *saved_regs;

  };

/* A structure describing a particular variant of the FRV.

   We allocate and initialize one of these structures when we create

   the gdbarch object for a variant.

   At the moment, all the FR variants we support differ only in which

   registers are present; the portable code of GDB knows that

   registers whose names are the empty string don't exist, so the

   `register_names' array captures all the per-variant information we

   need.

   in the future, if we need to have per-variant maps for raw size,

   virtual type, etc., we should replace register_names with an array

   of structures, each of which gives all the necessary info for one

   register.  Don't stick parallel arrays in here --- that's so

   Fortran.  */

struct gdbarch_tdep

{

  /* Which ABI is in use?  */

  enum frv_abi frv_abi;

  /* How many general-purpose registers does this variant have?  */

  int num_gprs;

  /* How many floating-point registers does this variant have?  */

  int num_fprs;

  /* How many hardware watchpoints can it support?  */

  int num_hw_watchpoints;

  /* How many hardware breakpoints can it support?  */

  int num_hw_breakpoints;

  /* Register names.  */

  char **register_names;

};

/* Return the FR-V ABI associated with GDBARCH.  */

enum frv_abi

frv_abi (struct gdbarch *gdbarch)

{

  return gdbarch_tdep (gdbarch)->frv_abi;

}

/* Fetch the interpreter and executable loadmap addresses (for shared

   library support) for the FDPIC ABI.  Return 0 if successful, -1 if

   not.  (E.g, -1 will be returned if the ABI isn't the FDPIC ABI.)  */

int

frv_fdpic_loadmap_addresses (struct gdbarch *gdbarch, CORE_ADDR *interp_addr,

                             CORE_ADDR *exec_addr)

{

  if (frv_abi (gdbarch) != FRV_ABI_FDPIC)

    return -1;

  else

    {

      struct regcache *regcache = get_current_regcache ();

      if (interp_addr != NULL)

        {

          ULONGEST val;

          regcache_cooked_read_unsigned (regcache,

                                         fdpic_loadmap_interp_regnum, &val);

          *interp_addr = val;

        }

      if (exec_addr != NULL)

        {

          ULONGEST val;

          regcache_cooked_read_unsigned (regcache,

                                         fdpic_loadmap_exec_regnum, &val);

          *exec_addr = val;

        }

      return 0;

    }

}

/* Allocate a new variant structure, and set up default values for all

   the fields.  */

static struct gdbarch_tdep *

new_variant (void)

{

  struct gdbarch_tdep *var;

  int r;

  char buf[20];

  var = xmalloc (sizeof (*var));

  memset (var, 0, sizeof (*var));

  var->frv_abi = FRV_ABI_EABI;

  var->num_gprs = 64;

  var->num_fprs = 64;

  var->num_hw_watchpoints = 0;

  var->num_hw_breakpoints = 0;

  /* By default, don't supply any general-purpose or floating-point

     register names.  */

  var->register_names

    = (char **) xmalloc ((frv_num_regs + frv_num_pseudo_regs)

                         * sizeof (char *));

  for (r = 0; r < frv_num_regs + frv_num_pseudo_regs; r++)

    var->register_names[r] = "";

  /* Do, however, supply default names for the known special-purpose

     registers.  */

  var->register_names[pc_regnum] = "pc";

  var->register_names[lr_regnum] = "lr";

  var->register_names[lcr_regnum] = "lcr";

  var->register_names[psr_regnum] = "psr";

  var->register_names[ccr_regnum] = "ccr";

  var->register_names[cccr_regnum] = "cccr";

  var->register_names[tbr_regnum] = "tbr";

  /* Debug registers.  */

  var->register_names[brr_regnum] = "brr";

  var->register_names[dbar0_regnum] = "dbar0";

  var->register_names[dbar1_regnum] = "dbar1";

  var->register_names[dbar2_regnum] = "dbar2";

  var->register_names[dbar3_regnum] = "dbar3";

  /* iacc0 (Only found on MB93405.)  */

  var->register_names[iacc0h_regnum] = "iacc0h";

  var->register_names[iacc0l_regnum] = "iacc0l";

  var->register_names[iacc0_regnum] = "iacc0";

  /* fsr0 (Found on FR555 and FR501.)  */

  var->register_names[fsr0_regnum] = "fsr0";

  /* acc0 - acc7.  The architecture provides for the possibility of many

     more (up to 64 total), but we don't want to make that big of a hole

     in the G packet.  If we need more in the future, we'll add them

     elsewhere.  */

  for (r = acc0_regnum; r <= acc7_regnum; r++)

    {

      char *buf;

      buf = xstrprintf ("acc%d", r - acc0_regnum);

      var->register_names[r] = buf;

    }

  /* accg0 - accg7: These are one byte registers.  The remote protocol

     provides the raw values packed four into a slot.  accg0123 and

     accg4567 correspond to accg0 - accg3 and accg4-accg7 respectively.

     We don't provide names for accg0123 and accg4567 since the user will

     likely not want to see these raw values.  */

  for (r = accg0_regnum; r <= accg7_regnum; r++)

    {

      char *buf;

      buf = xstrprintf ("accg%d", r - accg0_regnum);

      var->register_names[r] = buf;

    }

  /* msr0 and msr1.  */

  var->register_names[msr0_regnum] = "msr0";

  var->register_names[msr1_regnum] = "msr1";

  /* gner and fner registers.  */

  var->register_names[gner0_regnum] = "gner0";

  var->register_names[gner1_regnum] = "gner1";

  var->register_names[fner0_regnum] = "fner0";

  var->register_names[fner1_regnum] = "fner1";

  return var;

}

/* Indicate that the variant VAR has NUM_GPRS general-purpose

   registers, and fill in the names array appropriately.  */

static void

set_variant_num_gprs (struct gdbarch_tdep *var, int num_gprs)

{

  int r;

  var->num_gprs = num_gprs;

  for (r = 0; r < num_gprs; ++r)

    {

      char buf[20];

      sprintf (buf, "gr%d", r);

      var->register_names[first_gpr_regnum + r] = xstrdup (buf);

    }

}

/* Indicate that the variant VAR has NUM_FPRS floating-point

   registers, and fill in the names array appropriately.  */

static void

set_variant_num_fprs (struct gdbarch_tdep *var, int num_fprs)

{

  int r;

  var->num_fprs = num_fprs;

  for (r = 0; r < num_fprs; ++r)

    {

      char buf[20];

      sprintf (buf, "fr%d", r);

      var->register_names[first_fpr_regnum + r] = xstrdup (buf);

    }

}

static void

set_variant_abi_fdpic (struct gdbarch_tdep *var)

{

  var->frv_abi = FRV_ABI_FDPIC;

  var->register_names[fdpic_loadmap_exec_regnum] = xstrdup ("loadmap_exec");

  var->register_names[fdpic_loadmap_interp_regnum] = xstrdup ("loadmap_interp");

}

static void

set_variant_scratch_registers (struct gdbarch_tdep *var)

{

  var->register_names[scr0_regnum] = xstrdup ("scr0");

  var->register_names[scr1_regnum] = xstrdup ("scr1");

  var->register_names[scr2_regnum] = xstrdup ("scr2");

  var->register_names[scr3_regnum] = xstrdup ("scr3");

}

static const char *

frv_register_name (struct gdbarch *gdbarch, int reg)

{

  if (reg < 0)

    return "?toosmall?";

  if (reg >= frv_num_regs + frv_num_pseudo_regs)

    return "?toolarge?";

  return gdbarch_tdep (gdbarch)->register_names[reg];

}

static struct type *

frv_register_type (struct gdbarch *gdbarch, int reg)

{

  if (reg >= first_fpr_regnum && reg <= last_fpr_regnum)

    return builtin_type (gdbarch)->builtin_float;

  else if (reg == iacc0_regnum)

    return builtin_type (gdbarch)->builtin_int64;

  else

    return builtin_type (gdbarch)->builtin_int32;

}

static void

frv_pseudo_register_read (struct gdbarch *gdbarch, struct regcache *regcache,

                          int reg, gdb_byte *buffer)

{

  if (reg == iacc0_regnum)

    {

      regcache_raw_read (regcache, iacc0h_regnum, buffer);

      regcache_raw_read (regcache, iacc0l_regnum, (bfd_byte *) buffer + 4);

    }

  else if (accg0_regnum <= reg && reg <= accg7_regnum)

    {

      /* The accg raw registers have four values in each slot with the

         lowest register number occupying the first byte.  */

      int raw_regnum = accg0123_regnum + (reg - accg0_regnum) / 4;

      int byte_num = (reg - accg0_regnum) % 4;

      bfd_byte buf[4];

      regcache_raw_read (regcache, raw_regnum, buf);

      memset (buffer, 0, 4);

      /* FR-V is big endian, so put the requested byte in the first byte

         of the buffer allocated to hold the pseudo-register.  */

      ((bfd_byte *) buffer)[0] = buf[byte_num];

    }

}

static void

frv_pseudo_register_write (struct gdbarch *gdbarch, struct regcache *regcache,

                          int reg, const gdb_byte *buffer)

{

  if (reg == iacc0_regnum)

    {

      regcache_raw_write (regcache, iacc0h_regnum, buffer);

      regcache_raw_write (regcache, iacc0l_regnum, (bfd_byte *) buffer + 4);

    }

  else if (accg0_regnum <= reg && reg <= accg7_regnum)

    {

      /* The accg raw registers have four values in each slot with the

         lowest register number occupying the first byte.  */

      int raw_regnum = accg0123_regnum + (reg - accg0_regnum) / 4;

      int byte_num = (reg - accg0_regnum) % 4;

      char buf[4];

      regcache_raw_read (regcache, raw_regnum, buf);

      buf[byte_num] = ((bfd_byte *) buffer)[0];

      regcache_raw_write (regcache, raw_regnum, buf);

    }

}

static int

frv_register_sim_regno (struct gdbarch *gdbarch, int reg)

{

  static const int spr_map[] =

    {

      H_SPR_PSR,                /* psr_regnum */

      H_SPR_CCR,                /* ccr_regnum */

      H_SPR_CCCR,               /* cccr_regnum */

      -1,                       /* fdpic_loadmap_exec_regnum */

      -1,                       /* fdpic_loadmap_interp_regnum */

      -1,                       /* 134 */

      H_SPR_TBR,                /* tbr_regnum */

      H_SPR_BRR,                /* brr_regnum */

      H_SPR_DBAR0,              /* dbar0_regnum */

      H_SPR_DBAR1,              /* dbar1_regnum */

      H_SPR_DBAR2,              /* dbar2_regnum */

      H_SPR_DBAR3,              /* dbar3_regnum */

      H_SPR_SCR0,               /* scr0_regnum */

      H_SPR_SCR1,               /* scr1_regnum */

      H_SPR_SCR2,               /* scr2_regnum */

      H_SPR_SCR3,               /* scr3_regnum */

      H_SPR_LR,                 /* lr_regnum */

      H_SPR_LCR,                /* lcr_regnum */

      H_SPR_IACC0H,             /* iacc0h_regnum */

      H_SPR_IACC0L,             /* iacc0l_regnum */

      H_SPR_FSR0,               /* fsr0_regnum */

      /* FIXME: Add infrastructure for fetching/setting ACC and ACCG regs.  */

      -1,                       /* acc0_regnum */

      -1,                       /* acc1_regnum */

      -1,                       /* acc2_regnum */

      -1,                       /* acc3_regnum */

      -1,                       /* acc4_regnum */

      -1,                       /* acc5_regnum */

      -1,                       /* acc6_regnum */

      -1,                       /* acc7_regnum */

      -1,                       /* acc0123_regnum */

      -1,                       /* acc4567_regnum */

      H_SPR_MSR0,               /* msr0_regnum */

      H_SPR_MSR1,               /* msr1_regnum */

      H_SPR_GNER0,              /* gner0_regnum */

      H_SPR_GNER1,              /* gner1_regnum */

      H_SPR_FNER0,              /* fner0_regnum */

      H_SPR_FNER1,              /* fner1_regnum */

    };

  gdb_assert (reg >= 0 && reg < gdbarch_num_regs (gdbarch));

  if (first_gpr_regnum <= reg && reg <= last_gpr_regnum)

    return reg - first_gpr_regnum + SIM_FRV_GR0_REGNUM;

  else if (first_fpr_regnum <= reg && reg <= last_fpr_regnum)

    return reg - first_fpr_regnum + SIM_FRV_FR0_REGNUM;

  else if (pc_regnum == reg)

    return SIM_FRV_PC_REGNUM;

  else if (reg >= first_spr_regnum

           && reg < first_spr_regnum + sizeof (spr_map) / sizeof (spr_map[0]))

    {

      int spr_reg_offset = spr_map[reg - first_spr_regnum];

      if (spr_reg_offset < 0)

        return SIM_REGNO_DOES_NOT_EXIST;

      else

        return SIM_FRV_SPR0_REGNUM + spr_reg_offset;

    }

  internal_error (__FILE__, __LINE__, _("Bad register number %d"), reg);

}

static const unsigned char *

frv_breakpoint_from_pc (struct gdbarch *gdbarch, CORE_ADDR *pcptr, int *lenp)

{

  static unsigned char breakpoint[] = {0xc0, 0x70, 0x00, 0x01};

  *lenp = sizeof (breakpoint);

  return breakpoint;

}

/* Define the maximum number of instructions which may be packed into a

   bundle (VLIW instruction).  */

static const int max_instrs_per_bundle = 8;

/* Define the size (in bytes) of an FR-V instruction.  */

static const int frv_instr_size = 4;

/* Adjust a breakpoint's address to account for the FR-V architecture's

   constraint that a break instruction must not appear as any but the

   first instruction in the bundle.  */

static CORE_ADDR

frv_adjust_breakpoint_address (struct gdbarch *gdbarch, CORE_ADDR bpaddr)

{

  int count = max_instrs_per_bundle;

  CORE_ADDR addr = bpaddr - frv_instr_size;

  CORE_ADDR func_start = get_pc_function_start (bpaddr);

  /* Find the end of the previous packing sequence.  This will be indicated

     by either attempting to access some inaccessible memory or by finding

     an instruction word whose packing bit is set to one. */

  while (count-- > 0 && addr >= func_start)

    {

      char instr[frv_instr_size];

      int status;

      status = target_read_memory (addr, instr, sizeof instr);

      if (status != 0)

        break;

      /* This is a big endian architecture, so byte zero will have most

         significant byte.  The most significant bit of this byte is the

         packing bit.  */

      if (instr[0] & 0x80)

        break;

      addr -= frv_instr_size;

    }

  if (count > 0)

    bpaddr = addr + frv_instr_size;

  return bpaddr;

}

/* Return true if REG is a caller-saves ("scratch") register,

   false otherwise.  */

static int

is_caller_saves_reg (int reg)

{

  return ((4 <= reg && reg <= 7)

          || (14 <= reg && reg <= 15)

          || (32 <= reg && reg <= 47));

}

/* Return true if REG is a callee-saves register, false otherwise.  */

static int

is_callee_saves_reg (int reg)

{

  return ((16 <= reg && reg <= 31)

          || (48 <= reg && reg <= 63));

}

/* Return true if REG is an argument register, false otherwise.  */

static int

is_argument_reg (int reg)

{

  return (8 <= reg && reg <= 13);

}

/* Scan an FR-V prologue, starting at PC, until frame->PC.

   If FRAME is non-zero, fill in its saved_regs with appropriate addresses.

   We assume FRAME's saved_regs array has already been allocated and cleared.

   Return the first PC value after the prologue.

   Note that, for unoptimized code, we almost don't need this function

   at all; all arguments and locals live on the stack, so we just need

   the FP to find everything.  The catch: structures passed by value

   have their addresses living in registers; they're never spilled to

   the stack.  So if you ever want to be able to get to these

   arguments in any frame but the top, you'll need to do this serious

   prologue analysis.  */

static CORE_ADDR

frv_analyze_prologue (struct gdbarch *gdbarch, CORE_ADDR pc,

                      struct frame_info *this_frame,

                      struct frv_unwind_cache *info)

{

  enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);

  /* When writing out instruction bitpatterns, we use the following

     letters to label instruction fields:

     P - The parallel bit.  We don't use this.

     J - The register number of GRj in the instruction description.

     K - The register number of GRk in the instruction description.

     I - The register number of GRi.

     S - a signed imediate offset.

     U - an unsigned immediate offset.

     The dots below the numbers indicate where hex digit boundaries

     fall, to make it easier to check the numbers.  */

  /* Non-zero iff we've seen the instruction that initializes the

     frame pointer for this function's frame.  */

  int fp_set = 0;

  /* If fp_set is non_zero, then this is the distance from

     the stack pointer to frame pointer: fp = sp + fp_offset.  */

  int fp_offset = 0;

  /* Total size of frame prior to any alloca operations. */

  int framesize = 0;

  /* Flag indicating if lr has been saved on the stack.  */

  int lr_saved_on_stack = 0;

  /* The number of the general-purpose register we saved the return

     address ("link register") in, or -1 if we haven't moved it yet.  */

  int lr_save_reg = -1;

  /* Offset (from sp) at which lr has been saved on the stack.  */

  int lr_sp_offset = 0;

  /* If gr_saved[i] is non-zero, then we've noticed that general

     register i has been saved at gr_sp_offset[i] from the stack

     pointer.  */

  char gr_saved[64];

  int gr_sp_offset[64];

  /* The address of the most recently scanned prologue instruction.  */

  CORE_ADDR last_prologue_pc;

  /* The address of the next instruction. */

  CORE_ADDR next_pc;

  /* The upper bound to of the pc values to scan.  */

  CORE_ADDR lim_pc;

  memset (gr_saved, 0, sizeof (gr_saved));

  last_prologue_pc = pc;

  /* Try to compute an upper limit (on how far to scan) based on the

     line number info.  */

  lim_pc = skip_prologue_using_sal (gdbarch, pc);

  /* If there's no line number info, lim_pc will be 0.  In that case,

     set the limit to be 100 instructions away from pc.  Hopefully, this

     will be far enough away to account for the entire prologue.  Don't

     worry about overshooting the end of the function.  The scan loop

     below contains some checks to avoid scanning unreasonably far.  */

  if (lim_pc == 0)

    lim_pc = pc + 400;

  /* If we have a frame, we don't want to scan past the frame's pc.  This

     will catch those cases where the pc is in the prologue.  */

  if (this_frame)

    {

      CORE_ADDR frame_pc = get_frame_pc (this_frame);

      if (frame_pc < lim_pc)

        lim_pc = frame_pc;

    }

  /* Scan the prologue.  */

  while (pc < lim_pc)

    {

      char buf[frv_instr_size];

      LONGEST op;

      if (target_read_memory (pc, buf, sizeof buf) != 0)

        break;

      op = extract_signed_integer (buf, sizeof buf, byte_order);

      next_pc = pc + 4;

      /* The tests in this chain of ifs should be in order of

         decreasing selectivity, so that more particular patterns get

         to fire before less particular patterns.  */

      /* Some sort of control transfer instruction: stop scanning prologue.

         Integer Conditional Branch:

          X XXXX XX 0000110 XX XXXXXXXXXXXXXXXX

         Floating-point / media Conditional Branch:

          X XXXX XX 0000111 XX XXXXXXXXXXXXXXXX

         LCR Conditional Branch to LR

          X XXXX XX 0001110 XX XX 001 X XXXXXXXXXX

         Integer conditional Branches to LR

          X XXXX XX 0001110 XX XX 010 X XXXXXXXXXX

          X XXXX XX 0001110 XX XX 011 X XXXXXXXXXX

         Floating-point/Media Branches to LR

          X XXXX XX 0001110 XX XX 110 X XXXXXXXXXX

          X XXXX XX 0001110 XX XX 111 X XXXXXXXXXX

         Jump and Link

          X XXXXX X 0001100 XXXXXX XXXXXX XXXXXX

          X XXXXX X 0001101 XXXXXX XXXXXX XXXXXX

         Call

          X XXXXXX 0001111 XXXXXXXXXXXXXXXXXX

         Return from Trap

          X XXXXX X 0000101 XXXXXX XXXXXX XXXXXX

         Integer Conditional Trap

          X XXXX XX 0000100 XXXXXX XXXX 00 XXXXXX

          X XXXX XX 0011100 XXXXXX XXXXXXXXXXXX

         Floating-point /media Conditional Trap

          X XXXX XX 0000100 XXXXXX XXXX 01 XXXXXX

          X XXXX XX 0011101 XXXXXX XXXXXXXXXXXX

         Break

          X XXXX XX 0000100 XXXXXX XXXX 11 XXXXXX

         Media Trap

          X XXXX XX 0000100 XXXXXX XXXX 10 XXXXXX */

      if ((op & 0x01d80000) == 0x00180000 /* Conditional branches and Call */

          || (op & 0x01f80000) == 0x00300000  /* Jump and Link */

          || (op & 0x01f80000) == 0x00100000  /* Return from Trap, Trap */

          || (op & 0x01f80000) == 0x00700000) /* Trap immediate */

        {

          /* Stop scanning; not in prologue any longer.  */

          break;

        }

      /* Loading something from memory into fp probably means that

         we're in the epilogue.  Stop scanning the prologue.

         ld @(GRi, GRk), fp

         X 000010 0000010 XXXXXX 000100 XXXXXX

         ldi @(GRi, d12), fp

         X 000010 0110010 XXXXXX XXXXXXXXXXXX */

      else if ((op & 0x7ffc0fc0) == 0x04080100

               || (op & 0x7ffc0000) == 0x04c80000)

        {

          break;

        }

      /* Setting the FP from the SP:

         ori sp, 0, fp

         P 000010 0100010 000001 000000000000 = 0x04881000

             .    .   .    .   .    .   .   .

         We treat this as part of the prologue.  */

      else if ((op & 0x7fffffff) == 0x04881000)

        {

          fp_set = 1;

          fp_offset = 0;

          last_prologue_pc = next_pc;

        }

      /* Move the link register to the scratch register grJ, before saving:

         movsg lr, grJ

         P 000100 0000011 010000 000111 JJJJJJ = 0x080d01c0

             .    .   .    .   .    .    .   .

         We treat this as part of the prologue.  */

      else if ((op & 0x7fffffc0) == 0x080d01c0)

        {

          int gr_j = op & 0x3f;

          /* If we're moving it to a scratch register, that's fine.  */

          if (is_caller_saves_reg (gr_j))

            {

              lr_save_reg = gr_j;

              last_prologue_pc = next_pc;

            }

        }

      /* To save multiple callee-saves registers on the stack, at

         offset zero:

         std grK,@(sp,gr0)

         P KKKKKK 0000011 000001 000011 000000 = 0x000c10c0

         stq grK,@(sp,gr0)

         P KKKKKK 0000011 000001 000100 000000 = 0x000c1100

             .    .   .    .   .    .    .   .

         We treat this as part of the prologue, and record the register's

         saved address in the frame structure.  */

      else if ((op & 0x01ffffff) == 0x000c10c0

            || (op & 0x01ffffff) == 0x000c1100)

        {

          int gr_k = ((op >> 25) & 0x3f);

          int ope  = ((op >> 6)  & 0x3f);

          int count;

          int i;

          /* Is it an std or an stq?  */

          if (ope == 0x03)

            count = 2;

          else

            count = 4;