OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [gnu-stable/] [gdb-7.2/] [gdb/] [gdbserver/] [i386-low.c] - Blame information for rev 841

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 330 jeremybenn
/* Debug register code for the i386.
2
 
3
   Copyright (C) 2009, 2010 Free Software Foundation, Inc.
4
 
5
   This file is part of GDB.
6
 
7
   This program is free software; you can redistribute it and/or modify
8
   it under the terms of the GNU General Public License as published by
9
   the Free Software Foundation; either version 3 of the License, or
10
   (at your option) any later version.
11
 
12
   This program is distributed in the hope that it will be useful,
13
   but WITHOUT ANY WARRANTY; without even the implied warranty of
14
   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
15
   GNU General Public License for more details.
16
 
17
   You should have received a copy of the GNU General Public License
18
   along with this program.  If not, see <http://www.gnu.org/licenses/>.  */
19
 
20
#include "server.h"
21
#include "target.h"
22
#include "i386-low.h"
23
 
24
/* Support for 8-byte wide hw watchpoints.  */
25
#ifndef TARGET_HAS_DR_LEN_8
26
/* NOTE: sizeof (long) == 4 on win64.  */
27
#define TARGET_HAS_DR_LEN_8 (sizeof (void *) == 8)
28
#endif
29
 
30
enum target_hw_bp_type
31
  {
32
    hw_write   = 0,      /* Common  HW watchpoint */
33
    hw_read    = 1,     /* Read    HW watchpoint */
34
    hw_access  = 2,     /* Access  HW watchpoint */
35
    hw_execute = 3      /* Execute HW breakpoint */
36
  };
37
 
38
/* DR7 Debug Control register fields.  */
39
 
40
/* How many bits to skip in DR7 to get to R/W and LEN fields.  */
41
#define DR_CONTROL_SHIFT        16
42
/* How many bits in DR7 per R/W and LEN field for each watchpoint.  */
43
#define DR_CONTROL_SIZE         4
44
 
45
/* Watchpoint/breakpoint read/write fields in DR7.  */
46
#define DR_RW_EXECUTE   (0x0)   /* Break on instruction execution.  */
47
#define DR_RW_WRITE     (0x1)   /* Break on data writes.  */
48
#define DR_RW_READ      (0x3)   /* Break on data reads or writes.  */
49
 
50
/* This is here for completeness.  No platform supports this
51
   functionality yet (as of March 2001).  Note that the DE flag in the
52
   CR4 register needs to be set to support this.  */
53
#ifndef DR_RW_IORW
54
#define DR_RW_IORW      (0x2)   /* Break on I/O reads or writes.  */
55
#endif
56
 
57
/* Watchpoint/breakpoint length fields in DR7.  The 2-bit left shift
58
   is so we could OR this with the read/write field defined above.  */
59
#define DR_LEN_1        (0x0 << 2) /* 1-byte region watch or breakpoint.  */
60
#define DR_LEN_2        (0x1 << 2) /* 2-byte region watch.  */
61
#define DR_LEN_4        (0x3 << 2) /* 4-byte region watch.  */
62
#define DR_LEN_8        (0x2 << 2) /* 8-byte region watch (AMD64).  */
63
 
64
/* Local and Global Enable flags in DR7.
65
 
66
   When the Local Enable flag is set, the breakpoint/watchpoint is
67
   enabled only for the current task; the processor automatically
68
   clears this flag on every task switch.  When the Global Enable flag
69
   is set, the breakpoint/watchpoint is enabled for all tasks; the
70
   processor never clears this flag.
71
 
72
   Currently, all watchpoint are locally enabled.  If you need to
73
   enable them globally, read the comment which pertains to this in
74
   i386_insert_aligned_watchpoint below.  */
75
#define DR_LOCAL_ENABLE_SHIFT   0 /* Extra shift to the local enable bit.  */
76
#define DR_GLOBAL_ENABLE_SHIFT  1 /* Extra shift to the global enable bit.  */
77
#define DR_ENABLE_SIZE          2 /* Two enable bits per debug register.  */
78
 
79
/* Local and global exact breakpoint enable flags (a.k.a. slowdown
80
   flags).  These are only required on i386, to allow detection of the
81
   exact instruction which caused a watchpoint to break; i486 and
82
   later processors do that automatically.  We set these flags for
83
   backwards compatibility.  */
84
#define DR_LOCAL_SLOWDOWN       (0x100)
85
#define DR_GLOBAL_SLOWDOWN      (0x200)
86
 
87
/* Fields reserved by Intel.  This includes the GD (General Detect
88
   Enable) flag, which causes a debug exception to be generated when a
89
   MOV instruction accesses one of the debug registers.
90
 
91
   FIXME: My Intel manual says we should use 0xF800, not 0xFC00.  */
92
#define DR_CONTROL_RESERVED     (0xFC00)
93
 
94
/* Auxiliary helper macros.  */
95
 
96
/* A value that masks all fields in DR7 that are reserved by Intel.  */
97
#define I386_DR_CONTROL_MASK    (~DR_CONTROL_RESERVED)
98
 
99
/* The I'th debug register is vacant if its Local and Global Enable
100
   bits are reset in the Debug Control register.  */
101
#define I386_DR_VACANT(state, i) \
102
  (((state)->dr_control_mirror & (3 << (DR_ENABLE_SIZE * (i)))) == 0)
103
 
104
/* Locally enable the break/watchpoint in the I'th debug register.  */
105
#define I386_DR_LOCAL_ENABLE(state, i) \
106
  do { \
107
    (state)->dr_control_mirror |= \
108
      (1 << (DR_LOCAL_ENABLE_SHIFT + DR_ENABLE_SIZE * (i))); \
109
  } while (0)
110
 
111
/* Globally enable the break/watchpoint in the I'th debug register.  */
112
#define I386_DR_GLOBAL_ENABLE(state, i) \
113
  do { \
114
    (state)->dr_control_mirror |= \
115
      (1 << (DR_GLOBAL_ENABLE_SHIFT + DR_ENABLE_SIZE * (i))); \
116
  } while (0)
117
 
118
/* Disable the break/watchpoint in the I'th debug register.  */
119
#define I386_DR_DISABLE(state, i) \
120
  do { \
121
    (state)->dr_control_mirror &= \
122
      ~(3 << (DR_ENABLE_SIZE * (i))); \
123
  } while (0)
124
 
125
/* Set in DR7 the RW and LEN fields for the I'th debug register.  */
126
#define I386_DR_SET_RW_LEN(state, i,rwlen) \
127
  do { \
128
    (state)->dr_control_mirror &= \
129
      ~(0x0f << (DR_CONTROL_SHIFT + DR_CONTROL_SIZE * (i))); \
130
    (state)->dr_control_mirror |= \
131
      ((rwlen) << (DR_CONTROL_SHIFT + DR_CONTROL_SIZE * (i))); \
132
  } while (0)
133
 
134
/* Get from DR7 the RW and LEN fields for the I'th debug register.  */
135
#define I386_DR_GET_RW_LEN(state, i) \
136
  (((state)->dr_control_mirror \
137
    >> (DR_CONTROL_SHIFT + DR_CONTROL_SIZE * (i))) & 0x0f)
138
 
139
/* Did the watchpoint whose address is in the I'th register break?  */
140
#define I386_DR_WATCH_HIT(state,i) ((state)->dr_status_mirror & (1 << (i)))
141
 
142
/* A macro to loop over all debug registers.  */
143
#define ALL_DEBUG_REGISTERS(i)  for (i = 0; i < DR_NADDR; i++)
144
 
145
/* Types of operations supported by i386_handle_nonaligned_watchpoint.  */
146
typedef enum { WP_INSERT, WP_REMOVE, WP_COUNT } i386_wp_op_t;
147
 
148
/* Implementation.  */
149
 
150
/* Clear the reference counts and forget everything we knew about the
151
   debug registers.  */
152
 
153
void
154
i386_low_init_dregs (struct i386_debug_reg_state *state)
155
{
156
  int i;
157
 
158
  ALL_DEBUG_REGISTERS (i)
159
    {
160
      state->dr_mirror[i] = 0;
161
      state->dr_ref_count[i] = 0;
162
    }
163
  state->dr_control_mirror = 0;
164
  state->dr_status_mirror  = 0;
165
}
166
 
167
/* Print the values of the mirrored debug registers.  This is enabled via
168
   the "set debug-hw-points 1" monitor command.  */
169
 
170
static void
171
i386_show_dr (struct i386_debug_reg_state *state,
172
              const char *func, CORE_ADDR addr,
173
              int len, enum target_hw_bp_type type)
174
{
175
  int i;
176
 
177
  fprintf (stderr, "%s", func);
178
  if (addr || len)
179
    fprintf (stderr, " (addr=%lx, len=%d, type=%s)",
180
             (unsigned long) addr, len,
181
             type == hw_write ? "data-write"
182
             : (type == hw_read ? "data-read"
183
                : (type == hw_access ? "data-read/write"
184
                   : (type == hw_execute ? "instruction-execute"
185
                      /* FIXME: if/when I/O read/write
186
                         watchpoints are supported, add them
187
                         here.  */
188
                      : "??unknown??"))));
189
  fprintf (stderr, ":\n");
190
  fprintf (stderr, "\tCONTROL (DR7): %08x          STATUS (DR6): %08x\n",
191
           state->dr_control_mirror, state->dr_status_mirror);
192
  ALL_DEBUG_REGISTERS (i)
193
    {
194
      fprintf (stderr, "\
195
\tDR%d: addr=0x%s, ref.count=%d  DR%d: addr=0x%s, ref.count=%d\n",
196
              i, paddress (state->dr_mirror[i]),
197
              state->dr_ref_count[i],
198
              i + 1, paddress (state->dr_mirror[i + 1]),
199
              state->dr_ref_count[i + 1]);
200
      i++;
201
    }
202
}
203
 
204
/* Return the value of a 4-bit field for DR7 suitable for watching a
205
   region of LEN bytes for accesses of type TYPE.  LEN is assumed to
206
   have the value of 1, 2, or 4.  */
207
 
208
static unsigned
209
i386_length_and_rw_bits (int len, enum target_hw_bp_type type)
210
{
211
  unsigned rw;
212
 
213
  switch (type)
214
    {
215
      case hw_execute:
216
        rw = DR_RW_EXECUTE;
217
        break;
218
      case hw_write:
219
        rw = DR_RW_WRITE;
220
        break;
221
      case hw_read:
222
        fatal ("The i386 doesn't support data-read watchpoints.\n");
223
      case hw_access:
224
        rw = DR_RW_READ;
225
        break;
226
#if 0
227
        /* Not yet supported.  */
228
      case hw_io_access:
229
        rw = DR_RW_IORW;
230
        break;
231
#endif
232
      default:
233
        error ("\
234
Invalid hardware breakpoint type %d in i386_length_and_rw_bits.\n",
235
                        (int) type);
236
    }
237
 
238
  switch (len)
239
    {
240
      case 1:
241
        return (DR_LEN_1 | rw);
242
      case 2:
243
        return (DR_LEN_2 | rw);
244
      case 4:
245
        return (DR_LEN_4 | rw);
246
      case 8:
247
        if (TARGET_HAS_DR_LEN_8)
248
          return (DR_LEN_8 | rw);
249
      default:
250
        error ("\
251
Invalid hardware breakpoint length %d in i386_length_and_rw_bits.\n", len);
252
    }
253
}
254
 
255
/* Insert a watchpoint at address ADDR, which is assumed to be aligned
256
   according to the length of the region to watch.  LEN_RW_BITS is the
257
   value of the bits from DR7 which describes the length and access
258
   type of the region to be watched by this watchpoint.  Return 0 on
259
   success, -1 on failure.  */
260
 
261
static int
262
i386_insert_aligned_watchpoint (struct i386_debug_reg_state *state,
263
                                CORE_ADDR addr, unsigned len_rw_bits)
264
{
265
  int i;
266
 
267
  /* First, look for an occupied debug register with the same address
268
     and the same RW and LEN definitions.  If we find one, we can
269
     reuse it for this watchpoint as well (and save a register).  */
270
  ALL_DEBUG_REGISTERS (i)
271
    {
272
      if (!I386_DR_VACANT (state, i)
273
          && state->dr_mirror[i] == addr
274
          && I386_DR_GET_RW_LEN (state, i) == len_rw_bits)
275
        {
276
          state->dr_ref_count[i]++;
277
          return 0;
278
        }
279
    }
280
 
281
  /* Next, look for a vacant debug register.  */
282
  ALL_DEBUG_REGISTERS (i)
283
    {
284
      if (I386_DR_VACANT (state, i))
285
        break;
286
    }
287
 
288
  /* No more debug registers!  */
289
  if (i >= DR_NADDR)
290
    return -1;
291
 
292
  /* Now set up the register I to watch our region.  */
293
 
294
  /* Record the info in our local mirrored array.  */
295
  state->dr_mirror[i] = addr;
296
  state->dr_ref_count[i] = 1;
297
  I386_DR_SET_RW_LEN (state, i, len_rw_bits);
298
  /* Note: we only enable the watchpoint locally, i.e. in the current
299
     task.  Currently, no i386 target allows or supports global
300
     watchpoints; however, if any target would want that in the
301
     future, GDB should probably provide a command to control whether
302
     to enable watchpoints globally or locally, and the code below
303
     should use global or local enable and slow-down flags as
304
     appropriate.  */
305
  I386_DR_LOCAL_ENABLE (state, i);
306
  state->dr_control_mirror |= DR_LOCAL_SLOWDOWN;
307
  state->dr_control_mirror &= I386_DR_CONTROL_MASK;
308
 
309
  /* Finally, actually pass the info to the inferior.  */
310
  i386_dr_low_set_addr (state, i);
311
  i386_dr_low_set_control (state);
312
 
313
  return 0;
314
}
315
 
316
/* Remove a watchpoint at address ADDR, which is assumed to be aligned
317
   according to the length of the region to watch.  LEN_RW_BITS is the
318
   value of the bits from DR7 which describes the length and access
319
   type of the region watched by this watchpoint.  Return 0 on
320
   success, -1 on failure.  */
321
 
322
static int
323
i386_remove_aligned_watchpoint (struct i386_debug_reg_state *state,
324
                                CORE_ADDR addr, unsigned len_rw_bits)
325
{
326
  int i, retval = -1;
327
 
328
  ALL_DEBUG_REGISTERS (i)
329
    {
330
      if (!I386_DR_VACANT (state, i)
331
          && state->dr_mirror[i] == addr
332
          && I386_DR_GET_RW_LEN (state, i) == len_rw_bits)
333
        {
334
          if (--state->dr_ref_count[i] == 0) /* No longer in use?  */
335
            {
336
              /* Reset our mirror.  */
337
              state->dr_mirror[i] = 0;
338
              I386_DR_DISABLE (state, i);
339
              /* Reset it in the inferior.  */
340
              i386_dr_low_set_control (state);
341
              i386_dr_low_set_addr (state, i);
342
            }
343
          retval = 0;
344
        }
345
    }
346
 
347
  return retval;
348
}
349
 
350
/* Insert or remove a (possibly non-aligned) watchpoint, or count the
351
   number of debug registers required to watch a region at address
352
   ADDR whose length is LEN for accesses of type TYPE.  Return 0 on
353
   successful insertion or removal, a positive number when queried
354
   about the number of registers, or -1 on failure.  If WHAT is not a
355
   valid value, bombs through internal_error.  */
356
 
357
static int
358
i386_handle_nonaligned_watchpoint (struct i386_debug_reg_state *state,
359
                                   i386_wp_op_t what, CORE_ADDR addr, int len,
360
                                   enum target_hw_bp_type type)
361
{
362
  int retval = 0, status = 0;
363
  int max_wp_len = TARGET_HAS_DR_LEN_8 ? 8 : 4;
364
 
365
  static const int size_try_array[8][8] =
366
  {
367
    {1, 1, 1, 1, 1, 1, 1, 1},   /* Trying size one.  */
368
    {2, 1, 2, 1, 2, 1, 2, 1},   /* Trying size two.  */
369
    {2, 1, 2, 1, 2, 1, 2, 1},   /* Trying size three.  */
370
    {4, 1, 2, 1, 4, 1, 2, 1},   /* Trying size four.  */
371
    {4, 1, 2, 1, 4, 1, 2, 1},   /* Trying size five.  */
372
    {4, 1, 2, 1, 4, 1, 2, 1},   /* Trying size six.  */
373
    {4, 1, 2, 1, 4, 1, 2, 1},   /* Trying size seven.  */
374
    {8, 1, 2, 1, 4, 1, 2, 1},   /* Trying size eight.  */
375
  };
376
 
377
  while (len > 0)
378
    {
379
      int align = addr % max_wp_len;
380
      /* Four (eight on AMD64) is the maximum length a debug register
381
         can watch.  */
382
      int try = (len > max_wp_len ? (max_wp_len - 1) : len - 1);
383
      int size = size_try_array[try][align];
384
 
385
      if (what == WP_COUNT)
386
        {
387
          /* size_try_array[] is defined such that each iteration
388
             through the loop is guaranteed to produce an address and a
389
             size that can be watched with a single debug register.
390
             Thus, for counting the registers required to watch a
391
             region, we simply need to increment the count on each
392
             iteration.  */
393
          retval++;
394
        }
395
      else
396
        {
397
          unsigned len_rw = i386_length_and_rw_bits (size, type);
398
 
399
          if (what == WP_INSERT)
400
            status = i386_insert_aligned_watchpoint (state, addr, len_rw);
401
          else if (what == WP_REMOVE)
402
            status = i386_remove_aligned_watchpoint (state, addr, len_rw);
403
          else
404
            fatal ("\
405
Invalid value %d of operation in i386_handle_nonaligned_watchpoint.\n",
406
                   (int) what);
407
 
408
          /* We keep the loop going even after a failure, because some
409
             of the other aligned watchpoints might still succeed
410
             (e.g. if they watch addresses that are already watched,
411
             in which case we just increment the reference counts of
412
             occupied debug registers).  If we break out of the loop
413
             too early, we could cause those addresses watched by
414
             other watchpoints to be disabled when breakpoint.c reacts
415
             to our failure to insert this watchpoint and tries to
416
             remove it.  */
417
          if (status)
418
            retval = status;
419
        }
420
 
421
      addr += size;
422
      len -= size;
423
    }
424
 
425
  return retval;
426
}
427
 
428
#define Z_PACKET_WRITE_WP '2'
429
#define Z_PACKET_READ_WP '3'
430
#define Z_PACKET_ACCESS_WP '4'
431
 
432
/* Map the protocol watchpoint type TYPE to enum target_hw_bp_type.  */
433
 
434
static enum target_hw_bp_type
435
Z_packet_to_hw_type (char type)
436
{
437
  switch (type)
438
    {
439
    case Z_PACKET_WRITE_WP:
440
      return hw_write;
441
    case Z_PACKET_READ_WP:
442
      return hw_read;
443
    case Z_PACKET_ACCESS_WP:
444
      return hw_access;
445
    default:
446
      fatal ("Z_packet_to_hw_type: bad watchpoint type %c", type);
447
    }
448
}
449
 
450
/* Insert a watchpoint to watch a memory region which starts at
451
   address ADDR and whose length is LEN bytes.  Watch memory accesses
452
   of the type TYPE_FROM_PACKET.  Return 0 on success, -1 on failure.  */
453
 
454
int
455
i386_low_insert_watchpoint (struct i386_debug_reg_state *state,
456
                            char type_from_packet, CORE_ADDR addr, int len)
457
{
458
  int retval;
459
  enum target_hw_bp_type type = Z_packet_to_hw_type (type_from_packet);
460
 
461
  if (type == hw_read)
462
    return 1; /* unsupported */
463
 
464
  if (((len != 1 && len != 2 && len != 4)
465
       && !(TARGET_HAS_DR_LEN_8 && len == 8))
466
      || addr % len != 0)
467
    {
468
      retval = i386_handle_nonaligned_watchpoint (state, WP_INSERT,
469
                                                  addr, len, type);
470
    }
471
  else
472
    {
473
      unsigned len_rw = i386_length_and_rw_bits (len, type);
474
 
475
      retval = i386_insert_aligned_watchpoint (state, addr, len_rw);
476
    }
477
 
478
  if (debug_hw_points)
479
    i386_show_dr (state, "insert_watchpoint", addr, len, type);
480
 
481
  return retval;
482
}
483
 
484
/* Remove a watchpoint that watched the memory region which starts at
485
   address ADDR, whose length is LEN bytes, and for accesses of the
486
   type TYPE_FROM_PACKET.  Return 0 on success, -1 on failure.  */
487
 
488
int
489
i386_low_remove_watchpoint (struct i386_debug_reg_state *state,
490
                            char type_from_packet, CORE_ADDR addr, int len)
491
{
492
  int retval;
493
  enum target_hw_bp_type type = Z_packet_to_hw_type (type_from_packet);
494
 
495
  if (((len != 1 && len != 2 && len != 4)
496
       && !(TARGET_HAS_DR_LEN_8 && len == 8))
497
      || addr % len != 0)
498
    {
499
      retval = i386_handle_nonaligned_watchpoint (state, WP_REMOVE,
500
                                                  addr, len, type);
501
    }
502
  else
503
    {
504
      unsigned len_rw = i386_length_and_rw_bits (len, type);
505
 
506
      retval = i386_remove_aligned_watchpoint (state, addr, len_rw);
507
    }
508
 
509
  if (debug_hw_points)
510
    i386_show_dr (state, "remove_watchpoint", addr, len, type);
511
 
512
  return retval;
513
}
514
 
515
/* Return non-zero if we can watch a memory region that starts at
516
   address ADDR and whose length is LEN bytes.  */
517
 
518
int
519
i386_low_region_ok_for_watchpoint (struct i386_debug_reg_state *state,
520
                                   CORE_ADDR addr, int len)
521
{
522
  int nregs;
523
 
524
  /* Compute how many aligned watchpoints we would need to cover this
525
     region.  */
526
  nregs = i386_handle_nonaligned_watchpoint (state, WP_COUNT,
527
                                             addr, len, hw_write);
528
  return nregs <= DR_NADDR ? 1 : 0;
529
}
530
 
531
/* If the inferior has some break/watchpoint that triggered, set the
532
   address associated with that break/watchpoint and return true.
533
   Otherwise, return false.  */
534
 
535
int
536
i386_low_stopped_data_address (struct i386_debug_reg_state *state,
537
                               CORE_ADDR *addr_p)
538
{
539
  CORE_ADDR addr = 0;
540
  int i;
541
  int rc = 0;
542
 
543
  /* Get dr_status_mirror for use by I386_DR_WATCH_HIT.  */
544
  i386_dr_low_get_status (state);
545
 
546
  ALL_DEBUG_REGISTERS (i)
547
    {
548
      if (I386_DR_WATCH_HIT (state, i)
549
          /* This second condition makes sure DRi is set up for a data
550
             watchpoint, not a hardware breakpoint.  The reason is
551
             that GDB doesn't call the target_stopped_data_address
552
             method except for data watchpoints.  In other words, I'm
553
             being paranoiac.  */
554
          && I386_DR_GET_RW_LEN (state, i) != 0)
555
        {
556
          addr = state->dr_mirror[i];
557
          rc = 1;
558
          if (debug_hw_points)
559
            i386_show_dr (state, "watchpoint_hit", addr, -1, hw_write);
560
        }
561
    }
562
 
563
  if (debug_hw_points && addr == 0)
564
    i386_show_dr (state, "stopped_data_addr", 0, 0, hw_write);
565
 
566
  if (rc)
567
    *addr_p = addr;
568
  return rc;
569
}
570
 
571
/* Return true if the inferior has some watchpoint that triggered.
572
   Otherwise return false.  */
573
 
574
int
575
i386_low_stopped_by_watchpoint (struct i386_debug_reg_state *state)
576
{
577
  CORE_ADDR addr = 0;
578
  return i386_low_stopped_data_address (state, &addr);
579
}

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.