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jeremybenn |
/* Debug register code for the i386.
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Copyright (C) 2009, 2010 Free Software Foundation, Inc.
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This file is part of GDB.
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <http://www.gnu.org/licenses/>. */
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#include "server.h"
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#include "target.h"
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#include "i386-low.h"
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/* Support for 8-byte wide hw watchpoints. */
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#ifndef TARGET_HAS_DR_LEN_8
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/* NOTE: sizeof (long) == 4 on win64. */
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#define TARGET_HAS_DR_LEN_8 (sizeof (void *) == 8)
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#endif
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enum target_hw_bp_type
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{
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hw_write = 0, /* Common HW watchpoint */
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hw_read = 1, /* Read HW watchpoint */
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hw_access = 2, /* Access HW watchpoint */
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hw_execute = 3 /* Execute HW breakpoint */
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};
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/* DR7 Debug Control register fields. */
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/* How many bits to skip in DR7 to get to R/W and LEN fields. */
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#define DR_CONTROL_SHIFT 16
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/* How many bits in DR7 per R/W and LEN field for each watchpoint. */
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#define DR_CONTROL_SIZE 4
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/* Watchpoint/breakpoint read/write fields in DR7. */
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#define DR_RW_EXECUTE (0x0) /* Break on instruction execution. */
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#define DR_RW_WRITE (0x1) /* Break on data writes. */
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#define DR_RW_READ (0x3) /* Break on data reads or writes. */
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/* This is here for completeness. No platform supports this
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functionality yet (as of March 2001). Note that the DE flag in the
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CR4 register needs to be set to support this. */
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#ifndef DR_RW_IORW
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#define DR_RW_IORW (0x2) /* Break on I/O reads or writes. */
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#endif
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/* Watchpoint/breakpoint length fields in DR7. The 2-bit left shift
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is so we could OR this with the read/write field defined above. */
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#define DR_LEN_1 (0x0 << 2) /* 1-byte region watch or breakpoint. */
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#define DR_LEN_2 (0x1 << 2) /* 2-byte region watch. */
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#define DR_LEN_4 (0x3 << 2) /* 4-byte region watch. */
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#define DR_LEN_8 (0x2 << 2) /* 8-byte region watch (AMD64). */
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/* Local and Global Enable flags in DR7.
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When the Local Enable flag is set, the breakpoint/watchpoint is
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enabled only for the current task; the processor automatically
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clears this flag on every task switch. When the Global Enable flag
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is set, the breakpoint/watchpoint is enabled for all tasks; the
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processor never clears this flag.
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Currently, all watchpoint are locally enabled. If you need to
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enable them globally, read the comment which pertains to this in
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i386_insert_aligned_watchpoint below. */
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#define DR_LOCAL_ENABLE_SHIFT 0 /* Extra shift to the local enable bit. */
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#define DR_GLOBAL_ENABLE_SHIFT 1 /* Extra shift to the global enable bit. */
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#define DR_ENABLE_SIZE 2 /* Two enable bits per debug register. */
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/* Local and global exact breakpoint enable flags (a.k.a. slowdown
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flags). These are only required on i386, to allow detection of the
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exact instruction which caused a watchpoint to break; i486 and
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later processors do that automatically. We set these flags for
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backwards compatibility. */
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#define DR_LOCAL_SLOWDOWN (0x100)
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#define DR_GLOBAL_SLOWDOWN (0x200)
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/* Fields reserved by Intel. This includes the GD (General Detect
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Enable) flag, which causes a debug exception to be generated when a
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MOV instruction accesses one of the debug registers.
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FIXME: My Intel manual says we should use 0xF800, not 0xFC00. */
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#define DR_CONTROL_RESERVED (0xFC00)
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/* Auxiliary helper macros. */
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/* A value that masks all fields in DR7 that are reserved by Intel. */
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#define I386_DR_CONTROL_MASK (~DR_CONTROL_RESERVED)
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/* The I'th debug register is vacant if its Local and Global Enable
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bits are reset in the Debug Control register. */
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#define I386_DR_VACANT(state, i) \
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(((state)->dr_control_mirror & (3 << (DR_ENABLE_SIZE * (i)))) == 0)
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/* Locally enable the break/watchpoint in the I'th debug register. */
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#define I386_DR_LOCAL_ENABLE(state, i) \
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do { \
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(state)->dr_control_mirror |= \
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(1 << (DR_LOCAL_ENABLE_SHIFT + DR_ENABLE_SIZE * (i))); \
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} while (0)
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/* Globally enable the break/watchpoint in the I'th debug register. */
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#define I386_DR_GLOBAL_ENABLE(state, i) \
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do { \
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(state)->dr_control_mirror |= \
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(1 << (DR_GLOBAL_ENABLE_SHIFT + DR_ENABLE_SIZE * (i))); \
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} while (0)
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/* Disable the break/watchpoint in the I'th debug register. */
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#define I386_DR_DISABLE(state, i) \
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do { \
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(state)->dr_control_mirror &= \
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~(3 << (DR_ENABLE_SIZE * (i))); \
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} while (0)
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/* Set in DR7 the RW and LEN fields for the I'th debug register. */
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#define I386_DR_SET_RW_LEN(state, i,rwlen) \
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do { \
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(state)->dr_control_mirror &= \
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~(0x0f << (DR_CONTROL_SHIFT + DR_CONTROL_SIZE * (i))); \
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(state)->dr_control_mirror |= \
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((rwlen) << (DR_CONTROL_SHIFT + DR_CONTROL_SIZE * (i))); \
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} while (0)
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/* Get from DR7 the RW and LEN fields for the I'th debug register. */
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#define I386_DR_GET_RW_LEN(state, i) \
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(((state)->dr_control_mirror \
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>> (DR_CONTROL_SHIFT + DR_CONTROL_SIZE * (i))) & 0x0f)
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/* Did the watchpoint whose address is in the I'th register break? */
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#define I386_DR_WATCH_HIT(state,i) ((state)->dr_status_mirror & (1 << (i)))
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/* A macro to loop over all debug registers. */
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#define ALL_DEBUG_REGISTERS(i) for (i = 0; i < DR_NADDR; i++)
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/* Types of operations supported by i386_handle_nonaligned_watchpoint. */
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typedef enum { WP_INSERT, WP_REMOVE, WP_COUNT } i386_wp_op_t;
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/* Implementation. */
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/* Clear the reference counts and forget everything we knew about the
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debug registers. */
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void
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i386_low_init_dregs (struct i386_debug_reg_state *state)
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{
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int i;
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ALL_DEBUG_REGISTERS (i)
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{
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state->dr_mirror[i] = 0;
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state->dr_ref_count[i] = 0;
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}
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state->dr_control_mirror = 0;
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state->dr_status_mirror = 0;
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}
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/* Print the values of the mirrored debug registers. This is enabled via
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the "set debug-hw-points 1" monitor command. */
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static void
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i386_show_dr (struct i386_debug_reg_state *state,
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const char *func, CORE_ADDR addr,
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int len, enum target_hw_bp_type type)
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{
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int i;
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fprintf (stderr, "%s", func);
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if (addr || len)
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fprintf (stderr, " (addr=%lx, len=%d, type=%s)",
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(unsigned long) addr, len,
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type == hw_write ? "data-write"
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: (type == hw_read ? "data-read"
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: (type == hw_access ? "data-read/write"
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: (type == hw_execute ? "instruction-execute"
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/* FIXME: if/when I/O read/write
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watchpoints are supported, add them
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here. */
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: "??unknown??"))));
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fprintf (stderr, ":\n");
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fprintf (stderr, "\tCONTROL (DR7): %08x STATUS (DR6): %08x\n",
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state->dr_control_mirror, state->dr_status_mirror);
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ALL_DEBUG_REGISTERS (i)
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{
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fprintf (stderr, "\
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\tDR%d: addr=0x%s, ref.count=%d DR%d: addr=0x%s, ref.count=%d\n",
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i, paddress (state->dr_mirror[i]),
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state->dr_ref_count[i],
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i + 1, paddress (state->dr_mirror[i + 1]),
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state->dr_ref_count[i + 1]);
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i++;
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}
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}
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/* Return the value of a 4-bit field for DR7 suitable for watching a
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region of LEN bytes for accesses of type TYPE. LEN is assumed to
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have the value of 1, 2, or 4. */
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static unsigned
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i386_length_and_rw_bits (int len, enum target_hw_bp_type type)
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{
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unsigned rw;
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switch (type)
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{
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case hw_execute:
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rw = DR_RW_EXECUTE;
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break;
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case hw_write:
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rw = DR_RW_WRITE;
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break;
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case hw_read:
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fatal ("The i386 doesn't support data-read watchpoints.\n");
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case hw_access:
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rw = DR_RW_READ;
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break;
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#if 0
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/* Not yet supported. */
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case hw_io_access:
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rw = DR_RW_IORW;
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break;
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#endif
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default:
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error ("\
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Invalid hardware breakpoint type %d in i386_length_and_rw_bits.\n",
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(int) type);
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}
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switch (len)
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{
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case 1:
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return (DR_LEN_1 | rw);
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case 2:
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return (DR_LEN_2 | rw);
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case 4:
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return (DR_LEN_4 | rw);
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case 8:
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if (TARGET_HAS_DR_LEN_8)
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return (DR_LEN_8 | rw);
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default:
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error ("\
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Invalid hardware breakpoint length %d in i386_length_and_rw_bits.\n", len);
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}
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}
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/* Insert a watchpoint at address ADDR, which is assumed to be aligned
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according to the length of the region to watch. LEN_RW_BITS is the
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value of the bits from DR7 which describes the length and access
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type of the region to be watched by this watchpoint. Return 0 on
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success, -1 on failure. */
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static int
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i386_insert_aligned_watchpoint (struct i386_debug_reg_state *state,
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CORE_ADDR addr, unsigned len_rw_bits)
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{
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int i;
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/* First, look for an occupied debug register with the same address
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and the same RW and LEN definitions. If we find one, we can
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reuse it for this watchpoint as well (and save a register). */
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ALL_DEBUG_REGISTERS (i)
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{
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if (!I386_DR_VACANT (state, i)
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&& state->dr_mirror[i] == addr
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&& I386_DR_GET_RW_LEN (state, i) == len_rw_bits)
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{
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state->dr_ref_count[i]++;
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return 0;
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}
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}
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/* Next, look for a vacant debug register. */
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ALL_DEBUG_REGISTERS (i)
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{
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284 |
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if (I386_DR_VACANT (state, i))
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break;
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}
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/* No more debug registers! */
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if (i >= DR_NADDR)
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return -1;
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291 |
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292 |
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/* Now set up the register I to watch our region. */
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293 |
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294 |
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/* Record the info in our local mirrored array. */
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state->dr_mirror[i] = addr;
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296 |
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state->dr_ref_count[i] = 1;
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297 |
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I386_DR_SET_RW_LEN (state, i, len_rw_bits);
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/* Note: we only enable the watchpoint locally, i.e. in the current
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299 |
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task. Currently, no i386 target allows or supports global
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300 |
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watchpoints; however, if any target would want that in the
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future, GDB should probably provide a command to control whether
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to enable watchpoints globally or locally, and the code below
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should use global or local enable and slow-down flags as
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appropriate. */
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305 |
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I386_DR_LOCAL_ENABLE (state, i);
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306 |
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state->dr_control_mirror |= DR_LOCAL_SLOWDOWN;
|
307 |
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state->dr_control_mirror &= I386_DR_CONTROL_MASK;
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308 |
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309 |
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/* Finally, actually pass the info to the inferior. */
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310 |
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i386_dr_low_set_addr (state, i);
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311 |
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i386_dr_low_set_control (state);
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313 |
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return 0;
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314 |
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}
|
315 |
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316 |
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/* Remove a watchpoint at address ADDR, which is assumed to be aligned
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317 |
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according to the length of the region to watch. LEN_RW_BITS is the
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318 |
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value of the bits from DR7 which describes the length and access
|
319 |
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type of the region watched by this watchpoint. Return 0 on
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320 |
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success, -1 on failure. */
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321 |
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322 |
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static int
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323 |
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i386_remove_aligned_watchpoint (struct i386_debug_reg_state *state,
|
324 |
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CORE_ADDR addr, unsigned len_rw_bits)
|
325 |
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{
|
326 |
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int i, retval = -1;
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327 |
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|
328 |
|
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ALL_DEBUG_REGISTERS (i)
|
329 |
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{
|
330 |
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if (!I386_DR_VACANT (state, i)
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&& state->dr_mirror[i] == addr
|
332 |
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&& I386_DR_GET_RW_LEN (state, i) == len_rw_bits)
|
333 |
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{
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334 |
|
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if (--state->dr_ref_count[i] == 0) /* No longer in use? */
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335 |
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{
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336 |
|
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/* Reset our mirror. */
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337 |
|
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state->dr_mirror[i] = 0;
|
338 |
|
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I386_DR_DISABLE (state, i);
|
339 |
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/* Reset it in the inferior. */
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340 |
|
|
i386_dr_low_set_control (state);
|
341 |
|
|
i386_dr_low_set_addr (state, i);
|
342 |
|
|
}
|
343 |
|
|
retval = 0;
|
344 |
|
|
}
|
345 |
|
|
}
|
346 |
|
|
|
347 |
|
|
return retval;
|
348 |
|
|
}
|
349 |
|
|
|
350 |
|
|
/* Insert or remove a (possibly non-aligned) watchpoint, or count the
|
351 |
|
|
number of debug registers required to watch a region at address
|
352 |
|
|
ADDR whose length is LEN for accesses of type TYPE. Return 0 on
|
353 |
|
|
successful insertion or removal, a positive number when queried
|
354 |
|
|
about the number of registers, or -1 on failure. If WHAT is not a
|
355 |
|
|
valid value, bombs through internal_error. */
|
356 |
|
|
|
357 |
|
|
static int
|
358 |
|
|
i386_handle_nonaligned_watchpoint (struct i386_debug_reg_state *state,
|
359 |
|
|
i386_wp_op_t what, CORE_ADDR addr, int len,
|
360 |
|
|
enum target_hw_bp_type type)
|
361 |
|
|
{
|
362 |
|
|
int retval = 0, status = 0;
|
363 |
|
|
int max_wp_len = TARGET_HAS_DR_LEN_8 ? 8 : 4;
|
364 |
|
|
|
365 |
|
|
static const int size_try_array[8][8] =
|
366 |
|
|
{
|
367 |
|
|
{1, 1, 1, 1, 1, 1, 1, 1}, /* Trying size one. */
|
368 |
|
|
{2, 1, 2, 1, 2, 1, 2, 1}, /* Trying size two. */
|
369 |
|
|
{2, 1, 2, 1, 2, 1, 2, 1}, /* Trying size three. */
|
370 |
|
|
{4, 1, 2, 1, 4, 1, 2, 1}, /* Trying size four. */
|
371 |
|
|
{4, 1, 2, 1, 4, 1, 2, 1}, /* Trying size five. */
|
372 |
|
|
{4, 1, 2, 1, 4, 1, 2, 1}, /* Trying size six. */
|
373 |
|
|
{4, 1, 2, 1, 4, 1, 2, 1}, /* Trying size seven. */
|
374 |
|
|
{8, 1, 2, 1, 4, 1, 2, 1}, /* Trying size eight. */
|
375 |
|
|
};
|
376 |
|
|
|
377 |
|
|
while (len > 0)
|
378 |
|
|
{
|
379 |
|
|
int align = addr % max_wp_len;
|
380 |
|
|
/* Four (eight on AMD64) is the maximum length a debug register
|
381 |
|
|
can watch. */
|
382 |
|
|
int try = (len > max_wp_len ? (max_wp_len - 1) : len - 1);
|
383 |
|
|
int size = size_try_array[try][align];
|
384 |
|
|
|
385 |
|
|
if (what == WP_COUNT)
|
386 |
|
|
{
|
387 |
|
|
/* size_try_array[] is defined such that each iteration
|
388 |
|
|
through the loop is guaranteed to produce an address and a
|
389 |
|
|
size that can be watched with a single debug register.
|
390 |
|
|
Thus, for counting the registers required to watch a
|
391 |
|
|
region, we simply need to increment the count on each
|
392 |
|
|
iteration. */
|
393 |
|
|
retval++;
|
394 |
|
|
}
|
395 |
|
|
else
|
396 |
|
|
{
|
397 |
|
|
unsigned len_rw = i386_length_and_rw_bits (size, type);
|
398 |
|
|
|
399 |
|
|
if (what == WP_INSERT)
|
400 |
|
|
status = i386_insert_aligned_watchpoint (state, addr, len_rw);
|
401 |
|
|
else if (what == WP_REMOVE)
|
402 |
|
|
status = i386_remove_aligned_watchpoint (state, addr, len_rw);
|
403 |
|
|
else
|
404 |
|
|
fatal ("\
|
405 |
|
|
Invalid value %d of operation in i386_handle_nonaligned_watchpoint.\n",
|
406 |
|
|
(int) what);
|
407 |
|
|
|
408 |
|
|
/* We keep the loop going even after a failure, because some
|
409 |
|
|
of the other aligned watchpoints might still succeed
|
410 |
|
|
(e.g. if they watch addresses that are already watched,
|
411 |
|
|
in which case we just increment the reference counts of
|
412 |
|
|
occupied debug registers). If we break out of the loop
|
413 |
|
|
too early, we could cause those addresses watched by
|
414 |
|
|
other watchpoints to be disabled when breakpoint.c reacts
|
415 |
|
|
to our failure to insert this watchpoint and tries to
|
416 |
|
|
remove it. */
|
417 |
|
|
if (status)
|
418 |
|
|
retval = status;
|
419 |
|
|
}
|
420 |
|
|
|
421 |
|
|
addr += size;
|
422 |
|
|
len -= size;
|
423 |
|
|
}
|
424 |
|
|
|
425 |
|
|
return retval;
|
426 |
|
|
}
|
427 |
|
|
|
428 |
|
|
#define Z_PACKET_WRITE_WP '2'
|
429 |
|
|
#define Z_PACKET_READ_WP '3'
|
430 |
|
|
#define Z_PACKET_ACCESS_WP '4'
|
431 |
|
|
|
432 |
|
|
/* Map the protocol watchpoint type TYPE to enum target_hw_bp_type. */
|
433 |
|
|
|
434 |
|
|
static enum target_hw_bp_type
|
435 |
|
|
Z_packet_to_hw_type (char type)
|
436 |
|
|
{
|
437 |
|
|
switch (type)
|
438 |
|
|
{
|
439 |
|
|
case Z_PACKET_WRITE_WP:
|
440 |
|
|
return hw_write;
|
441 |
|
|
case Z_PACKET_READ_WP:
|
442 |
|
|
return hw_read;
|
443 |
|
|
case Z_PACKET_ACCESS_WP:
|
444 |
|
|
return hw_access;
|
445 |
|
|
default:
|
446 |
|
|
fatal ("Z_packet_to_hw_type: bad watchpoint type %c", type);
|
447 |
|
|
}
|
448 |
|
|
}
|
449 |
|
|
|
450 |
|
|
/* Insert a watchpoint to watch a memory region which starts at
|
451 |
|
|
address ADDR and whose length is LEN bytes. Watch memory accesses
|
452 |
|
|
of the type TYPE_FROM_PACKET. Return 0 on success, -1 on failure. */
|
453 |
|
|
|
454 |
|
|
int
|
455 |
|
|
i386_low_insert_watchpoint (struct i386_debug_reg_state *state,
|
456 |
|
|
char type_from_packet, CORE_ADDR addr, int len)
|
457 |
|
|
{
|
458 |
|
|
int retval;
|
459 |
|
|
enum target_hw_bp_type type = Z_packet_to_hw_type (type_from_packet);
|
460 |
|
|
|
461 |
|
|
if (type == hw_read)
|
462 |
|
|
return 1; /* unsupported */
|
463 |
|
|
|
464 |
|
|
if (((len != 1 && len != 2 && len != 4)
|
465 |
|
|
&& !(TARGET_HAS_DR_LEN_8 && len == 8))
|
466 |
|
|
|| addr % len != 0)
|
467 |
|
|
{
|
468 |
|
|
retval = i386_handle_nonaligned_watchpoint (state, WP_INSERT,
|
469 |
|
|
addr, len, type);
|
470 |
|
|
}
|
471 |
|
|
else
|
472 |
|
|
{
|
473 |
|
|
unsigned len_rw = i386_length_and_rw_bits (len, type);
|
474 |
|
|
|
475 |
|
|
retval = i386_insert_aligned_watchpoint (state, addr, len_rw);
|
476 |
|
|
}
|
477 |
|
|
|
478 |
|
|
if (debug_hw_points)
|
479 |
|
|
i386_show_dr (state, "insert_watchpoint", addr, len, type);
|
480 |
|
|
|
481 |
|
|
return retval;
|
482 |
|
|
}
|
483 |
|
|
|
484 |
|
|
/* Remove a watchpoint that watched the memory region which starts at
|
485 |
|
|
address ADDR, whose length is LEN bytes, and for accesses of the
|
486 |
|
|
type TYPE_FROM_PACKET. Return 0 on success, -1 on failure. */
|
487 |
|
|
|
488 |
|
|
int
|
489 |
|
|
i386_low_remove_watchpoint (struct i386_debug_reg_state *state,
|
490 |
|
|
char type_from_packet, CORE_ADDR addr, int len)
|
491 |
|
|
{
|
492 |
|
|
int retval;
|
493 |
|
|
enum target_hw_bp_type type = Z_packet_to_hw_type (type_from_packet);
|
494 |
|
|
|
495 |
|
|
if (((len != 1 && len != 2 && len != 4)
|
496 |
|
|
&& !(TARGET_HAS_DR_LEN_8 && len == 8))
|
497 |
|
|
|| addr % len != 0)
|
498 |
|
|
{
|
499 |
|
|
retval = i386_handle_nonaligned_watchpoint (state, WP_REMOVE,
|
500 |
|
|
addr, len, type);
|
501 |
|
|
}
|
502 |
|
|
else
|
503 |
|
|
{
|
504 |
|
|
unsigned len_rw = i386_length_and_rw_bits (len, type);
|
505 |
|
|
|
506 |
|
|
retval = i386_remove_aligned_watchpoint (state, addr, len_rw);
|
507 |
|
|
}
|
508 |
|
|
|
509 |
|
|
if (debug_hw_points)
|
510 |
|
|
i386_show_dr (state, "remove_watchpoint", addr, len, type);
|
511 |
|
|
|
512 |
|
|
return retval;
|
513 |
|
|
}
|
514 |
|
|
|
515 |
|
|
/* Return non-zero if we can watch a memory region that starts at
|
516 |
|
|
address ADDR and whose length is LEN bytes. */
|
517 |
|
|
|
518 |
|
|
int
|
519 |
|
|
i386_low_region_ok_for_watchpoint (struct i386_debug_reg_state *state,
|
520 |
|
|
CORE_ADDR addr, int len)
|
521 |
|
|
{
|
522 |
|
|
int nregs;
|
523 |
|
|
|
524 |
|
|
/* Compute how many aligned watchpoints we would need to cover this
|
525 |
|
|
region. */
|
526 |
|
|
nregs = i386_handle_nonaligned_watchpoint (state, WP_COUNT,
|
527 |
|
|
addr, len, hw_write);
|
528 |
|
|
return nregs <= DR_NADDR ? 1 : 0;
|
529 |
|
|
}
|
530 |
|
|
|
531 |
|
|
/* If the inferior has some break/watchpoint that triggered, set the
|
532 |
|
|
address associated with that break/watchpoint and return true.
|
533 |
|
|
Otherwise, return false. */
|
534 |
|
|
|
535 |
|
|
int
|
536 |
|
|
i386_low_stopped_data_address (struct i386_debug_reg_state *state,
|
537 |
|
|
CORE_ADDR *addr_p)
|
538 |
|
|
{
|
539 |
|
|
CORE_ADDR addr = 0;
|
540 |
|
|
int i;
|
541 |
|
|
int rc = 0;
|
542 |
|
|
|
543 |
|
|
/* Get dr_status_mirror for use by I386_DR_WATCH_HIT. */
|
544 |
|
|
i386_dr_low_get_status (state);
|
545 |
|
|
|
546 |
|
|
ALL_DEBUG_REGISTERS (i)
|
547 |
|
|
{
|
548 |
|
|
if (I386_DR_WATCH_HIT (state, i)
|
549 |
|
|
/* This second condition makes sure DRi is set up for a data
|
550 |
|
|
watchpoint, not a hardware breakpoint. The reason is
|
551 |
|
|
that GDB doesn't call the target_stopped_data_address
|
552 |
|
|
method except for data watchpoints. In other words, I'm
|
553 |
|
|
being paranoiac. */
|
554 |
|
|
&& I386_DR_GET_RW_LEN (state, i) != 0)
|
555 |
|
|
{
|
556 |
|
|
addr = state->dr_mirror[i];
|
557 |
|
|
rc = 1;
|
558 |
|
|
if (debug_hw_points)
|
559 |
|
|
i386_show_dr (state, "watchpoint_hit", addr, -1, hw_write);
|
560 |
|
|
}
|
561 |
|
|
}
|
562 |
|
|
|
563 |
|
|
if (debug_hw_points && addr == 0)
|
564 |
|
|
i386_show_dr (state, "stopped_data_addr", 0, 0, hw_write);
|
565 |
|
|
|
566 |
|
|
if (rc)
|
567 |
|
|
*addr_p = addr;
|
568 |
|
|
return rc;
|
569 |
|
|
}
|
570 |
|
|
|
571 |
|
|
/* Return true if the inferior has some watchpoint that triggered.
|
572 |
|
|
Otherwise return false. */
|
573 |
|
|
|
574 |
|
|
int
|
575 |
|
|
i386_low_stopped_by_watchpoint (struct i386_debug_reg_state *state)
|
576 |
|
|
{
|
577 |
|
|
CORE_ADDR addr = 0;
|
578 |
|
|
return i386_low_stopped_data_address (state, &addr);
|
579 |
|
|
}
|