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jeremybenn |
/* GNU/Linux/MIPS specific low level interface, for the remote server for GDB.
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Copyright (C) 1995, 1996, 1998, 1999, 2000, 2001, 2002, 2005, 2006, 2007,
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2008, 2009, 2010 Free Software Foundation, Inc.
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This file is part of GDB.
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <http://www.gnu.org/licenses/>. */
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#include "server.h"
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#include "linux-low.h"
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#include <sys/ptrace.h>
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#include <endian.h>
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#include "gdb_proc_service.h"
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/* Defined in auto-generated file mips-linux.c. */
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void init_registers_mips_linux (void);
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/* Defined in auto-generated file mips64-linux.c. */
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void init_registers_mips64_linux (void);
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#ifndef PTRACE_GET_THREAD_AREA
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#define PTRACE_GET_THREAD_AREA 25
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#endif
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#ifdef HAVE_SYS_REG_H
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#include <sys/reg.h>
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#endif
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#define mips_num_regs 73
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#include <asm/ptrace.h>
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union mips_register
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{
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unsigned char buf[8];
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/* Deliberately signed, for proper sign extension. */
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int reg32;
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long long reg64;
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};
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/* Return the ptrace ``address'' of register REGNO. */
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static int mips_regmap[] = {
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-1, 1, 2, 3, 4, 5, 6, 7,
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8, 9, 10, 11, 12, 13, 14, 15,
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16, 17, 18, 19, 20, 21, 22, 23,
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24, 25, 26, 27, 28, 29, 30, 31,
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-1, MMLO, MMHI, BADVADDR, CAUSE, PC,
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64 |
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FPR_BASE, FPR_BASE + 1, FPR_BASE + 2, FPR_BASE + 3,
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FPR_BASE + 4, FPR_BASE + 5, FPR_BASE + 6, FPR_BASE + 7,
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FPR_BASE + 8, FPR_BASE + 8, FPR_BASE + 10, FPR_BASE + 11,
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FPR_BASE + 12, FPR_BASE + 13, FPR_BASE + 14, FPR_BASE + 15,
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FPR_BASE + 16, FPR_BASE + 17, FPR_BASE + 18, FPR_BASE + 19,
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FPR_BASE + 20, FPR_BASE + 21, FPR_BASE + 22, FPR_BASE + 23,
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FPR_BASE + 24, FPR_BASE + 25, FPR_BASE + 26, FPR_BASE + 27,
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FPR_BASE + 28, FPR_BASE + 29, FPR_BASE + 30, FPR_BASE + 31,
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FPC_CSR, FPC_EIR,
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};
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/* From mips-linux-nat.c. */
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/* Pseudo registers can not be read. ptrace does not provide a way to
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read (or set) PS_REGNUM, and there's no point in reading or setting
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ZERO_REGNUM. We also can not set BADVADDR, CAUSE, or FCRIR via
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ptrace(). */
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static int
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mips_cannot_fetch_register (int regno)
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{
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if (mips_regmap[regno] == -1)
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return 1;
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if (find_regno ("r0") == regno)
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return 1;
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return 0;
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}
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static int
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mips_cannot_store_register (int regno)
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{
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if (mips_regmap[regno] == -1)
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return 1;
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if (find_regno ("r0") == regno)
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return 1;
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if (find_regno ("cause") == regno)
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return 1;
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if (find_regno ("badvaddr") == regno)
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return 1;
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if (find_regno ("fir") == regno)
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return 1;
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return 0;
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}
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static CORE_ADDR
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mips_get_pc (struct regcache *regcache)
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{
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union mips_register pc;
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collect_register_by_name (regcache, "pc", pc.buf);
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return register_size (0) == 4 ? pc.reg32 : pc.reg64;
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}
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static void
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mips_set_pc (struct regcache *regcache, CORE_ADDR pc)
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{
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union mips_register newpc;
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if (register_size (0) == 4)
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newpc.reg32 = pc;
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else
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newpc.reg64 = pc;
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supply_register_by_name (regcache, "pc", newpc.buf);
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}
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/* Correct in either endianness. */
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static const unsigned int mips_breakpoint = 0x0005000d;
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#define mips_breakpoint_len 4
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/* We only place breakpoints in empty marker functions, and thread locking
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is outside of the function. So rather than importing software single-step,
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we can just run until exit. */
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static CORE_ADDR
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mips_reinsert_addr (void)
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{
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struct regcache *regcache = get_thread_regcache (current_inferior, 1);
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union mips_register ra;
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collect_register_by_name (regcache, "r31", ra.buf);
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return register_size (0) == 4 ? ra.reg32 : ra.reg64;
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}
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static int
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mips_breakpoint_at (CORE_ADDR where)
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{
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unsigned int insn;
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(*the_target->read_memory) (where, (unsigned char *) &insn, 4);
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if (insn == mips_breakpoint)
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return 1;
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/* If necessary, recognize more trap instructions here. GDB only uses the
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one. */
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return 0;
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}
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/* Fetch the thread-local storage pointer for libthread_db. */
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ps_err_e
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ps_get_thread_area (const struct ps_prochandle *ph,
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lwpid_t lwpid, int idx, void **base)
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{
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if (ptrace (PTRACE_GET_THREAD_AREA, lwpid, NULL, base) != 0)
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return PS_ERR;
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/* IDX is the bias from the thread pointer to the beginning of the
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thread descriptor. It has to be subtracted due to implementation
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quirks in libthread_db. */
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*base = (void *) ((char *)*base - idx);
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return PS_OK;
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}
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#ifdef HAVE_PTRACE_GETREGS
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static void
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mips_collect_register (struct regcache *regcache,
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int use_64bit, int regno, union mips_register *reg)
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{
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union mips_register tmp_reg;
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if (use_64bit)
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{
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collect_register (regcache, regno, &tmp_reg.reg64);
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*reg = tmp_reg;
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}
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else
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{
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collect_register (regcache, regno, &tmp_reg.reg32);
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reg->reg64 = tmp_reg.reg32;
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}
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}
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static void
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mips_supply_register (struct regcache *regcache,
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int use_64bit, int regno, const union mips_register *reg)
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{
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int offset = 0;
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/* For big-endian 32-bit targets, ignore the high four bytes of each
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eight-byte slot. */
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if (__BYTE_ORDER == __BIG_ENDIAN && !use_64bit)
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offset = 4;
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supply_register (regcache, regno, reg->buf + offset);
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}
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static void
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mips_collect_register_32bit (struct regcache *regcache,
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int use_64bit, int regno, unsigned char *buf)
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{
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union mips_register tmp_reg;
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int reg32;
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mips_collect_register (regcache, use_64bit, regno, &tmp_reg);
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reg32 = tmp_reg.reg64;
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memcpy (buf, ®32, 4);
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}
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static void
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mips_supply_register_32bit (struct regcache *regcache,
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int use_64bit, int regno, const unsigned char *buf)
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{
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union mips_register tmp_reg;
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int reg32;
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memcpy (®32, buf, 4);
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tmp_reg.reg64 = reg32;
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mips_supply_register (regcache, use_64bit, regno, &tmp_reg);
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}
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static void
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mips_fill_gregset (struct regcache *regcache, void *buf)
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{
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union mips_register *regset = buf;
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int i, use_64bit;
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use_64bit = (register_size (0) == 8);
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for (i = 1; i < 32; i++)
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mips_collect_register (regcache, use_64bit, i, regset + i);
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mips_collect_register (regcache, use_64bit,
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find_regno ("lo"), regset + 32);
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mips_collect_register (regcache, use_64bit,
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find_regno ("hi"), regset + 33);
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mips_collect_register (regcache, use_64bit,
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find_regno ("pc"), regset + 34);
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mips_collect_register (regcache, use_64bit,
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find_regno ("badvaddr"), regset + 35);
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mips_collect_register (regcache, use_64bit,
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find_regno ("status"), regset + 36);
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mips_collect_register (regcache, use_64bit,
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find_regno ("cause"), regset + 37);
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mips_collect_register (regcache, use_64bit,
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find_regno ("restart"), regset + 0);
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}
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static void
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mips_store_gregset (struct regcache *regcache, const void *buf)
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{
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const union mips_register *regset = buf;
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int i, use_64bit;
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use_64bit = (register_size (0) == 8);
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for (i = 0; i < 32; i++)
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mips_supply_register (regcache, use_64bit, i, regset + i);
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mips_supply_register (regcache, use_64bit, find_regno ("lo"), regset + 32);
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mips_supply_register (regcache, use_64bit, find_regno ("hi"), regset + 33);
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mips_supply_register (regcache, use_64bit, find_regno ("pc"), regset + 34);
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mips_supply_register (regcache, use_64bit,
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find_regno ("badvaddr"), regset + 35);
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mips_supply_register (regcache, use_64bit,
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find_regno ("status"), regset + 36);
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mips_supply_register (regcache, use_64bit,
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find_regno ("cause"), regset + 37);
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mips_supply_register (regcache, use_64bit,
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find_regno ("restart"), regset + 0);
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}
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294 |
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static void
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mips_fill_fpregset (struct regcache *regcache, void *buf)
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{
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298 |
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union mips_register *regset = buf;
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int i, use_64bit, first_fp, big_endian;
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use_64bit = (register_size (0) == 8);
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first_fp = find_regno ("f0");
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big_endian = (__BYTE_ORDER == __BIG_ENDIAN);
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304 |
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305 |
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/* See GDB for a discussion of this peculiar layout. */
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for (i = 0; i < 32; i++)
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if (use_64bit)
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collect_register (regcache, first_fp + i, regset[i].buf);
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else
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collect_register (regcache, first_fp + i,
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regset[i & ~1].buf + 4 * (big_endian != (i & 1)));
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312 |
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313 |
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mips_collect_register_32bit (regcache, use_64bit,
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find_regno ("fcsr"), regset[32].buf);
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315 |
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mips_collect_register_32bit (regcache, use_64bit, find_regno ("fir"),
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regset[32].buf + 4);
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317 |
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}
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318 |
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319 |
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static void
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320 |
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mips_store_fpregset (struct regcache *regcache, const void *buf)
|
321 |
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{
|
322 |
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const union mips_register *regset = buf;
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323 |
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int i, use_64bit, first_fp, big_endian;
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324 |
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325 |
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use_64bit = (register_size (0) == 8);
|
326 |
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first_fp = find_regno ("f0");
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327 |
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big_endian = (__BYTE_ORDER == __BIG_ENDIAN);
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328 |
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329 |
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/* See GDB for a discussion of this peculiar layout. */
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330 |
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for (i = 0; i < 32; i++)
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if (use_64bit)
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supply_register (regcache, first_fp + i, regset[i].buf);
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else
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supply_register (regcache, first_fp + i,
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regset[i & ~1].buf + 4 * (big_endian != (i & 1)));
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336 |
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337 |
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mips_supply_register_32bit (regcache, use_64bit,
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find_regno ("fcsr"), regset[32].buf);
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mips_supply_register_32bit (regcache, use_64bit, find_regno ("fir"),
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regset[32].buf + 4);
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}
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342 |
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|
#endif /* HAVE_PTRACE_GETREGS */
|
343 |
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344 |
|
|
struct regset_info target_regsets[] = {
|
345 |
|
|
#ifdef HAVE_PTRACE_GETREGS
|
346 |
|
|
{ PTRACE_GETREGS, PTRACE_SETREGS, 0, 38 * 8, GENERAL_REGS,
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347 |
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mips_fill_gregset, mips_store_gregset },
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348 |
|
|
{ PTRACE_GETFPREGS, PTRACE_SETFPREGS, 0, 33 * 8, FP_REGS,
|
349 |
|
|
mips_fill_fpregset, mips_store_fpregset },
|
350 |
|
|
#endif /* HAVE_PTRACE_GETREGS */
|
351 |
|
|
{ 0, 0, 0, -1, -1, NULL, NULL }
|
352 |
|
|
};
|
353 |
|
|
|
354 |
|
|
struct linux_target_ops the_low_target = {
|
355 |
|
|
#ifdef __mips64
|
356 |
|
|
init_registers_mips64_linux,
|
357 |
|
|
#else
|
358 |
|
|
init_registers_mips_linux,
|
359 |
|
|
#endif
|
360 |
|
|
mips_num_regs,
|
361 |
|
|
mips_regmap,
|
362 |
|
|
mips_cannot_fetch_register,
|
363 |
|
|
mips_cannot_store_register,
|
364 |
|
|
mips_get_pc,
|
365 |
|
|
mips_set_pc,
|
366 |
|
|
(const unsigned char *) &mips_breakpoint,
|
367 |
|
|
mips_breakpoint_len,
|
368 |
|
|
mips_reinsert_addr,
|
369 |
|
|
0,
|
370 |
|
|
mips_breakpoint_at,
|
371 |
|
|
};
|