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[/] [openrisc/] [trunk/] [gnu-stable/] [gdb-7.2/] [include/] [opcode/] [crx.h] - Blame information for rev 853

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1 330 jeremybenn
/* crx.h -- Header file for CRX opcode and register tables.
2
   Copyright 2004, 2010 Free Software Foundation, Inc.
3
   Contributed by Tomer Levi, NSC, Israel.
4
   Originally written for GAS 2.12 by Tomer Levi, NSC, Israel.
5
   Updates, BFDizing, GNUifying and ELF support by Tomer Levi.
6
 
7
   This file is part of GAS, GDB and the GNU binutils.
8
 
9
   GAS, GDB, and GNU binutils is free software; you can redistribute it
10
   and/or modify it under the terms of the GNU General Public License as
11
   published by the Free Software Foundation; either version 3, or (at your
12
   option) any later version.
13
 
14
   GAS, GDB, and GNU binutils are distributed in the hope that they will be
15
   useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
16
   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
17
   GNU General Public License for more details.
18
 
19
   You should have received a copy of the GNU General Public License
20
   along with this program; if not, write to the Free Software
21
   Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
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   MA 02110-1301, USA.  */
23
 
24
#ifndef _CRX_H_
25
#define _CRX_H_
26
 
27
/* CRX core/debug Registers :
28
   The enums are used as indices to CRX registers table (crx_regtab).
29
   Therefore, order MUST be preserved.  */
30
 
31
typedef enum
32
  {
33
    /* 32-bit general purpose registers.  */
34
    r0, r1, r2, r3, r4, r5, r6, r7, r8, r9,
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    r10, r11, r12, r13, r14, r15, ra, sp,
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    /* 32-bit user registers.  */
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    u0, u1, u2, u3, u4, u5, u6, u7, u8, u9,
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    u10, u11, u12, u13, u14, u15, ura, usp,
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    /* hi and lo registers.  */
40
    hi, lo,
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    /* hi and lo user registers.  */
42
    uhi, ulo,
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    /* Processor Status Register.  */
44
    psr,
45
    /* Interrupt Base Register.  */
46
    intbase,
47
    /* Interrupt Stack Pointer Register.  */
48
    isp,
49
    /* Configuration Register.  */
50
    cfg,
51
    /* Coprocessor Configuration Register.  */
52
    cpcfg,
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    /* Coprocessor Enable Register.  */
54
    cen,
55
    /* Not a register.  */
56
    nullregister,
57
    MAX_REG
58
  }
59
reg;
60
 
61
/* CRX Coprocessor registers and special registers :
62
   The enums are used as indices to CRX coprocessor registers table
63
   (crx_copregtab). Therefore, order MUST be preserved.  */
64
 
65
typedef enum
66
  {
67
    /* Coprocessor registers.  */
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    c0 = MAX_REG, c1, c2, c3, c4, c5, c6, c7, c8,
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    c9, c10, c11, c12, c13, c14, c15,
70
    /* Coprocessor special registers.  */
71
    cs0, cs1 ,cs2, cs3, cs4, cs5, cs6, cs7, cs8,
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    cs9, cs10, cs11, cs12, cs13, cs14, cs15,
73
    /* Not a Coprocessor register.  */
74
    nullcopregister,
75
    MAX_COPREG
76
  }
77
copreg;
78
 
79
/* CRX Register types. */
80
 
81
typedef enum
82
  {
83
    CRX_R_REGTYPE,    /*  r<N>    */
84
    CRX_U_REGTYPE,    /*  u<N>    */
85
    CRX_C_REGTYPE,    /*  c<N>    */
86
    CRX_CS_REGTYPE,   /*  cs<N>   */
87
    CRX_CFG_REGTYPE   /*  configuration register   */
88
  }
89
reg_type;
90
 
91
/* CRX argument types :
92
   The argument types correspond to instructions operands
93
 
94
   Argument types :
95
   r - register
96
   c - constant
97
   i - immediate
98
   idxr - index register
99
   rbase - register base
100
   s - star ('*')
101
   copr - coprocessor register
102
   copsr - coprocessor special register.  */
103
 
104
typedef enum
105
  {
106
    arg_r, arg_c, arg_cr, arg_ic, arg_icr, arg_sc,
107
    arg_idxr, arg_rbase, arg_copr, arg_copsr,
108
    /* Not an argument.  */
109
    nullargs
110
  }
111
argtype;
112
 
113
/* CRX operand types :
114
   The operand types correspond to instructions operands.  */
115
 
116
typedef enum
117
  {
118
    dummy,
119
    /* 4-bit encoded constant.  */
120
    cst4,
121
    /* N-bit immediate.  */
122
    i16, i32,
123
    /* N-bit unsigned immediate.  */
124
    ui3, ui4, ui5, ui16,
125
    /* N-bit signed displacement.  */
126
    disps9, disps17, disps25, disps32,
127
    /* N-bit unsigned displacement.  */
128
    dispu5,
129
    /* N-bit escaped displacement.  */
130
    dispe9,
131
    /* N-bit absolute address.  */
132
    abs16, abs32,
133
    /* Register relative.  */
134
    rbase, rbase_dispu4,
135
    rbase_disps12, rbase_disps16, rbase_disps28, rbase_disps32,
136
    /* Register index.  */
137
    rindex_disps6, rindex_disps22,
138
    /* 4-bit genaral-purpose register specifier.  */
139
    regr,
140
    /* 8-bit register address space.  */
141
    regr8,
142
    /* coprocessor register.  */
143
    copregr,
144
    /* coprocessor special register.  */
145
    copsregr,
146
    /* Not an operand.  */
147
    nulloperand,
148
    /* Maximum supported operand.  */
149
    MAX_OPRD
150
  }
151
operand_type;
152
 
153
/* CRX instruction types.  */
154
 
155
#define NO_TYPE_INS       0
156
#define ARITH_INS         1
157
#define LD_STOR_INS       2
158
#define BRANCH_INS        3
159
#define ARITH_BYTE_INS    4
160
#define CMPBR_INS         5
161
#define SHIFT_INS         6
162
#define BRANCH_NEQ_INS    7
163
#define LD_STOR_INS_INC   8
164
#define STOR_IMM_INS      9
165
#define CSTBIT_INS       10
166
#define COP_BRANCH_INS   11
167
#define COP_REG_INS      12
168
#define COPS_REG_INS     13
169
#define DCR_BRANCH_INS   14
170
 
171
/* Maximum value supported for instruction types.  */
172
#define CRX_INS_MAX     (1 << 4)
173
/* Mask to record an instruction type.  */
174
#define CRX_INS_MASK    (CRX_INS_MAX - 1)
175
/* Return instruction type, given instruction's attributes.  */
176
#define CRX_INS_TYPE(attr) ((attr) & CRX_INS_MASK)
177
 
178
/* Indicates whether this instruction has a register list as parameter.  */
179
#define REG_LIST        CRX_INS_MAX
180
/* The operands in binary and assembly are placed in reverse order.
181
   load - (REVERSE_MATCH)/store - (! REVERSE_MATCH).  */
182
#define REVERSE_MATCH  (1 << 5)
183
 
184
/* Kind of displacement map used DISPU[BWD]4.  */
185
#define DISPUB4        (1 << 6)
186
#define DISPUW4        (1 << 7)
187
#define DISPUD4        (1 << 8)
188
#define DISPU4MAP      (DISPUB4 | DISPUW4 | DISPUD4)
189
 
190
/* Printing formats, where the instruction prefix isn't consecutive.  */
191
#define FMT_1          (1 << 9)   /* 0xF0F00000 */
192
#define FMT_2          (1 << 10)   /* 0xFFF0FF00 */
193
#define FMT_3          (1 << 11)   /* 0xFFF00F00 */
194
#define FMT_4          (1 << 12)   /* 0xFFF0F000 */
195
#define FMT_5          (1 << 13)   /* 0xFFF0FFF0 */
196
#define FMT_CRX        (FMT_1 | FMT_2 | FMT_3 | FMT_4 | FMT_5)
197
 
198
/* Indicates whether this instruction can be relaxed.  */
199
#define RELAXABLE      (1 << 14)
200
 
201
/* Indicates that instruction uses user registers (and not
202
   general-purpose registers) as operands.  */
203
#define USER_REG       (1 << 15)
204
 
205
/* Indicates that instruction can perfom a cst4 mapping.  */
206
#define CST4MAP        (1 << 16)
207
 
208
/* Instruction shouldn't allow 'sp' usage.  */
209
#define NO_SP          (1 << 17)
210
 
211
/* Instruction shouldn't allow to push a register which is used as a rptr.  */
212
#define NO_RPTR        (1 << 18)
213
 
214
/* Maximum operands per instruction.  */
215
#define MAX_OPERANDS      5
216
/* Maximum register name length. */
217
#define MAX_REGNAME_LEN   10
218
/* Maximum instruction length. */
219
#define MAX_INST_LEN      256
220
 
221
 
222
/* Values defined for the flags field of a struct operand_entry.  */
223
 
224
/* Operand must be an unsigned number.  */
225
#define OP_UNSIGNED   (1 << 0)
226
/* Operand must be a signed number.  */
227
#define OP_SIGNED     (1 << 1)
228
/* A special arithmetic 4-bit constant operand.  */
229
#define OP_CST4       (1 << 2)
230
/* A special load/stor 4-bit unsigned displacement operand.  */
231
#define OP_DISPU4     (1 << 3)
232
/* Operand must be an even number.  */
233
#define OP_EVEN       (1 << 4)
234
/* Operand is shifted right.  */
235
#define OP_SHIFT      (1 << 5)
236
/* Operand is shifted right and decremented.  */
237
#define OP_SHIFT_DEC  (1 << 6)
238
/* Operand has reserved escape sequences.  */
239
#define OP_ESC        (1 << 7)
240
/* Operand is used only for the upper 64 KB (FFFF0000 to FFFFFFFF).  */
241
#define OP_UPPER_64KB (1 << 8)
242
 
243
/* Single operand description.  */
244
 
245
typedef struct
246
  {
247
    /* Operand type.  */
248
    operand_type op_type;
249
    /* Operand location within the opcode.  */
250
    unsigned int shift;
251
  }
252
operand_desc;
253
 
254
/* Instruction data structure used in instruction table.  */
255
 
256
typedef struct
257
  {
258
    /* Name.  */
259
    const char *mnemonic;
260
    /* Size (in words).  */
261
    unsigned int size;
262
    /* Constant prefix (matched by the disassembler).  */
263
    unsigned long match;
264
    /* Match size (in bits).  */
265
    int match_bits;
266
    /* Attributes.  */
267
    unsigned int flags;
268
    /* Operands (always last, so unreferenced operands are initialized).  */
269
    operand_desc operands[MAX_OPERANDS];
270
  }
271
inst;
272
 
273
/* Data structure for a single instruction's arguments (Operands).  */
274
 
275
typedef struct
276
  {
277
    /* Register or base register.  */
278
    reg r;
279
    /* Index register.  */
280
    reg i_r;
281
    /* Coprocessor register.  */
282
    copreg cr;
283
    /* Constant/immediate/absolute value.  */
284
    long constant;
285
    /* Scaled index mode.  */
286
    unsigned int scale;
287
    /* Argument type.  */
288
    argtype type;
289
    /* Size of the argument (in bits) required to represent.  */
290
    int size;
291
  /* The type of the expression.  */
292
    unsigned char X_op;
293
  }
294
argument;
295
 
296
/* Internal structure to hold the various entities
297
   corresponding to the current assembling instruction.  */
298
 
299
typedef struct
300
  {
301
    /* Number of arguments.  */
302
    int nargs;
303
    /* The argument data structure for storing args (operands).  */
304
    argument arg[MAX_OPERANDS];
305
/* The following fields are required only by CRX-assembler.  */
306
#ifdef TC_CRX
307
    /* Expression used for setting the fixups (if any).  */
308
    expressionS exp;
309
    bfd_reloc_code_real_type rtype;
310
#endif /* TC_CRX */
311
    /* Instruction size (in bytes).  */
312
    int size;
313
  }
314
ins;
315
 
316
/* Structure to hold information about predefined operands.  */
317
 
318
typedef struct
319
  {
320
    /* Size (in bits).  */
321
    unsigned int bit_size;
322
    /* Argument type.  */
323
    argtype arg_type;
324
    /* One bit syntax flags.  */
325
    int flags;
326
  }
327
operand_entry;
328
 
329
/* Structure to hold trap handler information.  */
330
 
331
typedef struct
332
  {
333
    /* Trap name.  */
334
    char *name;
335
    /* Index in dispatch table.  */
336
    unsigned int entry;
337
  }
338
trap_entry;
339
 
340
/* Structure to hold information about predefined registers.  */
341
 
342
typedef struct
343
  {
344
    /* Name (string representation).  */
345
    char *name;
346
    /* Value (enum representation).  */
347
    union
348
    {
349
      /* Register.  */
350
      reg reg_val;
351
      /* Coprocessor register.  */
352
      copreg copreg_val;
353
    } value;
354
    /* Register image.  */
355
    int image;
356
    /* Register type.  */
357
    reg_type type;
358
  }
359
reg_entry;
360
 
361
/* Structure to hold a cst4 operand mapping.  */
362
 
363
/* CRX opcode table.  */
364
extern const inst crx_instruction[];
365
extern const int crx_num_opcodes;
366
#define NUMOPCODES crx_num_opcodes
367
 
368
/* CRX operands table.  */
369
extern const operand_entry crx_optab[];
370
 
371
/* CRX registers table.  */
372
extern const reg_entry crx_regtab[];
373
extern const int crx_num_regs;
374
#define NUMREGS crx_num_regs
375
 
376
/* CRX coprocessor registers table.  */
377
extern const reg_entry crx_copregtab[];
378
extern const int crx_num_copregs;
379
#define NUMCOPREGS crx_num_copregs
380
 
381
/* CRX trap/interrupt table.  */
382
extern const trap_entry crx_traps[];
383
extern const int crx_num_traps;
384
#define NUMTRAPS crx_num_traps
385
 
386
/* cst4 operand mapping.  */
387
extern const long cst4_map[];
388
extern const int cst4_maps;
389
 
390
/* Table of instructions with no operands.  */
391
extern const char* no_op_insn[];
392
 
393
/* Current instruction we're assembling.  */
394
extern const inst *instruction;
395
 
396
/* A macro for representing the instruction "constant" opcode, that is,
397
   the FIXED part of the instruction. The "constant" opcode is represented
398
   as a 32-bit unsigned long, where OPC is expanded (by a left SHIFT)
399
   over that range.  */
400
#define BIN(OPC,SHIFT)  (OPC << SHIFT)
401
 
402
/* Is the current instruction type is TYPE ?  */
403
#define IS_INSN_TYPE(TYPE)            \
404
  (CRX_INS_TYPE(instruction->flags) == TYPE)
405
 
406
/* Is the current instruction mnemonic is MNEMONIC ?  */
407
#define IS_INSN_MNEMONIC(MNEMONIC)    \
408
  (strcmp(instruction->mnemonic,MNEMONIC) == 0)
409
 
410
/* Does the current instruction has register list ?  */
411
#define INST_HAS_REG_LIST             \
412
  (instruction->flags & REG_LIST)
413
 
414
/* Long long type handling.  */
415
/* Replace all appearances of 'long long int' with LONGLONG.  */
416
typedef long long int LONGLONG;
417
typedef unsigned long long ULONGLONG;
418
 
419
#endif /* _CRX_H_ */

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