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[/] [openrisc/] [trunk/] [gnu-stable/] [gdb-7.2/] [opcodes/] [bfin-dis.c] - Blame information for rev 860

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1 330 jeremybenn 
/* Disassemble ADI Blackfin Instructions.
2 
   Copyright 2005, 2006, 2007, 2008, 2009, 2010 Free Software Foundation, Inc.
3 
 
4 
   This file is part of libopcodes.
5 
 
6 
   This library is free software; you can redistribute it and/or modify
7 
   it under the terms of the GNU General Public License as published by
8 
   the Free Software Foundation; either version 3, or (at your option)
9 
   any later version.
10 
 
11 
   It is distributed in the hope that it will be useful, but WITHOUT
12 
   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
13 
   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
14 
   License for more details.
15 
 
16 
   You should have received a copy of the GNU General Public License
17 
   along with this program; if not, write to the Free Software
18 
   Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
19 
   MA 02110-1301, USA.  */
20 
 
21 
#include <stdio.h>
22 
#include <stdlib.h>
23 
#include <string.h>
24 
 
25 
#include "opcode/bfin.h"
26 
 
27 
#define M_S2RND 1
28 
#define M_T     2
29 
#define M_W32   3
30 
#define M_FU    4
31 
#define M_TFU   6
32 
#define M_IS    8
33 
#define M_ISS2  9
34 
#define M_IH    11
35 
#define M_IU    12
36 
 
37 
#ifndef PRINTF
38 
#define PRINTF printf
39 
#endif
40 
 
41 
#ifndef EXIT
42 
#define EXIT exit
43 
#endif
44 
 
45 
typedef long TIword;
46 
 
47 
#define HOST_LONG_WORD_SIZE (sizeof (long) * 8)
48 
#define XFIELD(w,p,s)       (((w) & ((1 << (s)) - 1) << (p)) >> (p))
49 
#define SIGNEXTEND(v, n)    ((v << (HOST_LONG_WORD_SIZE - (n))) >> (HOST_LONG_WORD_SIZE - (n)))
50 
#define MASKBITS(val, bits) (val & ((1 << bits) - 1))
51 
 
52 
#include "dis-asm.h"
53 
 
54 
typedef unsigned int bu32;
55 
 
56 
typedef enum
57 
{
58 
  c_0, c_1, c_4, c_2, c_uimm2, c_uimm3, c_imm3, c_pcrel4,
59 
  c_imm4, c_uimm4s4, c_uimm4s4d, c_uimm4, c_uimm4s2, c_negimm5s4, c_imm5, c_imm5d, c_uimm5, c_imm6,
60 
  c_imm7, c_imm7d, c_imm8, c_uimm8, c_pcrel8, c_uimm8s4, c_pcrel8s4, c_lppcrel10, c_pcrel10,
61 
  c_pcrel12, c_imm16s4, c_luimm16, c_imm16, c_imm16d, c_huimm16, c_rimm16, c_imm16s2, c_uimm16s4,
62 
  c_uimm16s4d, c_uimm16, c_pcrel24, c_uimm32, c_imm32, c_huimm32, c_huimm32e,
63 
} const_forms_t;
64 
 
65 
static struct
66 
{
67 
  char *name;
68 
  int nbits;
69 
  char reloc;
70 
  char issigned;
71 
  char pcrel;
72 
  char scale;
73 
  char offset;
74 
  char negative;
75 
  char positive;
76 
  char decimal;
77 
  char leading;
78 
  char exact;
79 
} constant_formats[] =
80 
{
81 
  { "0",          0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0},
82 
  { "1",          0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0},
83 
  { "4",          0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0},
84 
  { "2",          0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0},
85 
  { "uimm2",      2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
86 
  { "uimm3",      3, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
87 
  { "imm3",       3, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0},
88 
  { "pcrel4",     4, 1, 0, 1, 1, 0, 0, 0, 0, 0, 0},
89 
  { "imm4",       4, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0},
90 
  { "uimm4s4",    4, 0, 0, 0, 2, 0, 0, 1, 0, 0, 0},
91 
  { "uimm4s4d",   4, 0, 0, 0, 2, 0, 0, 1, 1, 0, 0},
92 
  { "uimm4",      4, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
93 
  { "uimm4s2",    4, 0, 0, 0, 1, 0, 0, 1, 0, 0, 0},
94 
  { "negimm5s4",  5, 0, 1, 0, 2, 0, 1, 0, 0, 0, 0},
95 
  { "imm5",       5, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0},
96 
  { "imm5d",      5, 0, 1, 0, 0, 0, 0, 0, 1, 0, 0},
97 
  { "uimm5",      5, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
98 
  { "imm6",       6, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0},
99 
  { "imm7",       7, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0},
100 
  { "imm7d",      7, 0, 1, 0, 0, 0, 0, 0, 1, 3, 0},
101 
  { "imm8",       8, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0},
102 
  { "uimm8",      8, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
103 
  { "pcrel8",     8, 1, 0, 1, 1, 0, 0, 0, 0, 0, 0},
104 
  { "uimm8s4",    8, 0, 0, 0, 2, 0, 0, 0, 0, 0, 0},
105 
  { "pcrel8s4",   8, 1, 1, 1, 2, 0, 0, 0, 0, 0, 0},
106 
  { "lppcrel10", 10, 1, 0, 1, 1, 0, 0, 0, 0, 0, 0},
107 
  { "pcrel10",   10, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0},
108 
  { "pcrel12",   12, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0},
109 
  { "imm16s4",   16, 0, 1, 0, 2, 0, 0, 0, 0, 0, 0},
110 
  { "luimm16",   16, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0},
111 
  { "imm16",     16, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0},
112 
  { "imm16d",    16, 0, 1, 0, 0, 0, 0, 0, 1, 3, 0},
113 
  { "huimm16",   16, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0},
114 
  { "rimm16",    16, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0},
115 
  { "imm16s2",   16, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0},
116 
  { "uimm16s4",  16, 0, 0, 0, 2, 0, 0, 0, 0, 0, 0},
117 
  { "uimm16s4d", 16, 0, 0, 0, 2, 0, 0, 0, 1, 0, 0},
118 
  { "uimm16",    16, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
119 
  { "pcrel24",   24, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0},
120 
  { "uimm32",    32, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
121 
  { "imm32",     32, 0, 1, 0, 0, 0, 0, 0, 1, 3, 0},
122 
  { "huimm32",   32, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0},
123 
  { "huimm32e",  32, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1},
124 
};
125 
 
126 
static char comment = 0;
127 
static char parallel = 0;
128 
 
129 
static char *
130 
fmtconst (const_forms_t cf, TIword x, bfd_vma pc, disassemble_info * outf)
131 
{
132 
  static char buf[60];
133 
 
134 
  if (constant_formats[cf].reloc)
135 
    {
136 
      bfd_vma ea = (((constant_formats[cf].pcrel ? SIGNEXTEND (x, constant_formats[cf].nbits)
137 
                      : x) + constant_formats[cf].offset) << constant_formats[cf].scale);
138 
      if (constant_formats[cf].pcrel)
139 
        ea += pc;
140 
 
141 
     if (outf->symbol_at_address_func (ea, outf) || !constant_formats[cf].exact)
142 
       {
143 
          outf->print_address_func (ea, outf);
144 
          return "";
145 
       }
146 
     else
147 
       {
148 
          sprintf (buf, "%lx", (unsigned long) x);
149 
          return buf;
150 
       }
151 
    }
152 
 
153 
  /* Negative constants have an implied sign bit.  */
154 
  if (constant_formats[cf].negative)
155 
    {
156 
      int nb = constant_formats[cf].nbits + 1;
157 
 
158 
      x = x | (1 << constant_formats[cf].nbits);
159 
      x = SIGNEXTEND (x, nb);
160 
    }
161 
  else
162 
    x = constant_formats[cf].issigned ? SIGNEXTEND (x, constant_formats[cf].nbits) : x;
163 
 
164 
  if (constant_formats[cf].offset)
165 
    x += constant_formats[cf].offset;
166 
 
167 
  if (constant_formats[cf].scale)
168 
    x <<= constant_formats[cf].scale;
169 
 
170 
  if (constant_formats[cf].decimal)
171 
    {
172 
      if (constant_formats[cf].leading)
173 
        {
174 
          char ps[10];
175 
          sprintf (ps, "%%%ii", constant_formats[cf].leading);
176 
          sprintf (buf, ps, x);
177 
        }
178 
      else
179 
        sprintf (buf, "%li", x);
180 
    }
181 
  else
182 
    {
183 
      if (constant_formats[cf].issigned && x < 0)
184 
        sprintf (buf, "-0x%x", abs (x));
185 
      else
186 
        sprintf (buf, "0x%lx", (unsigned long) x);
187 
    }
188 
 
189 
  return buf;
190 
}
191 
 
192 
static bu32
193 
fmtconst_val (const_forms_t cf, unsigned int x, unsigned int pc)
194 
{
195 
  if (0 && constant_formats[cf].reloc)
196 
    {
197 
      bu32 ea = (((constant_formats[cf].pcrel
198 
                   ? SIGNEXTEND (x, constant_formats[cf].nbits)
199 
                   : x) + constant_formats[cf].offset)
200 
                 << constant_formats[cf].scale);
201 
      if (constant_formats[cf].pcrel)
202 
        ea += pc;
203 
 
204 
      return ea;
205 
    }
206 
 
207 
  /* Negative constants have an implied sign bit.  */
208 
  if (constant_formats[cf].negative)
209 
    {
210 
      int nb = constant_formats[cf].nbits + 1;
211 
      x = x | (1 << constant_formats[cf].nbits);
212 
      x = SIGNEXTEND (x, nb);
213 
    }
214 
  else if (constant_formats[cf].issigned)
215 
    x = SIGNEXTEND (x, constant_formats[cf].nbits);
216 
 
217 
  x += constant_formats[cf].offset;
218 
  x <<= constant_formats[cf].scale;
219 
 
220 
  return x;
221 
}
222 
 
223 
enum machine_registers
224 
{
225 
  REG_RL0, REG_RL1, REG_RL2, REG_RL3, REG_RL4, REG_RL5, REG_RL6, REG_RL7,
226 
  REG_RH0, REG_RH1, REG_RH2, REG_RH3, REG_RH4, REG_RH5, REG_RH6, REG_RH7,
227 
  REG_R0, REG_R1, REG_R2, REG_R3, REG_R4, REG_R5, REG_R6, REG_R7,
228 
  REG_R1_0, REG_R3_2, REG_R5_4, REG_R7_6, REG_P0, REG_P1, REG_P2, REG_P3,
229 
  REG_P4, REG_P5, REG_SP, REG_FP, REG_A0x, REG_A1x, REG_A0w, REG_A1w,
230 
  REG_A0, REG_A1, REG_I0, REG_I1, REG_I2, REG_I3, REG_M0, REG_M1,
231 
  REG_M2, REG_M3, REG_B0, REG_B1, REG_B2, REG_B3, REG_L0, REG_L1,
232 
  REG_L2, REG_L3,
233 
  REG_AZ, REG_AN, REG_AC0, REG_AC1, REG_AV0, REG_AV1, REG_AV0S, REG_AV1S,
234 
  REG_AQ, REG_V, REG_VS,
235 
  REG_sftreset, REG_omode, REG_excause, REG_emucause, REG_idle_req, REG_hwerrcause, REG_CC, REG_LC0,
236 
  REG_LC1, REG_GP, REG_ASTAT, REG_RETS, REG_LT0, REG_LB0, REG_LT1, REG_LB1,
237 
  REG_CYCLES, REG_CYCLES2, REG_USP, REG_SEQSTAT, REG_SYSCFG, REG_RETI, REG_RETX, REG_RETN,
238 
  REG_RETE, REG_EMUDAT, REG_BR0, REG_BR1, REG_BR2, REG_BR3, REG_BR4, REG_BR5, REG_BR6,
239 
  REG_BR7, REG_PL0, REG_PL1, REG_PL2, REG_PL3, REG_PL4, REG_PL5, REG_SLP, REG_FLP,
240 
  REG_PH0, REG_PH1, REG_PH2, REG_PH3, REG_PH4, REG_PH5, REG_SHP, REG_FHP,
241 
  REG_IL0, REG_IL1, REG_IL2, REG_IL3, REG_ML0, REG_ML1, REG_ML2, REG_ML3,
242 
  REG_BL0, REG_BL1, REG_BL2, REG_BL3, REG_LL0, REG_LL1, REG_LL2, REG_LL3,
243 
  REG_IH0, REG_IH1, REG_IH2, REG_IH3, REG_MH0, REG_MH1, REG_MH2, REG_MH3,
244 
  REG_BH0, REG_BH1, REG_BH2, REG_BH3, REG_LH0, REG_LH1, REG_LH2, REG_LH3,
245 
  REG_LASTREG,
246 
};
247 
 
248 
enum reg_class
249 
{
250 
  rc_dregs_lo, rc_dregs_hi, rc_dregs, rc_dregs_pair, rc_pregs, rc_spfp, rc_dregs_hilo, rc_accum_ext,
251 
  rc_accum_word, rc_accum, rc_iregs, rc_mregs, rc_bregs, rc_lregs, rc_dpregs, rc_gregs,
252 
  rc_regs, rc_statbits, rc_ignore_bits, rc_ccstat, rc_counters, rc_dregs2_sysregs1, rc_open, rc_sysregs2,
253 
  rc_sysregs3, rc_allregs,
254 
  LIM_REG_CLASSES
255 
};
256 
 
257 
static char *reg_names[] =
258 
{
259 
  "R0.L", "R1.L", "R2.L", "R3.L", "R4.L", "R5.L", "R6.L", "R7.L",
260 
  "R0.H", "R1.H", "R2.H", "R3.H", "R4.H", "R5.H", "R6.H", "R7.H",
261 
  "R0", "R1", "R2", "R3", "R4", "R5", "R6", "R7",
262 
  "R1:0", "R3:2", "R5:4", "R7:6", "P0", "P1", "P2", "P3",
263 
  "P4", "P5", "SP", "FP", "A0.X", "A1.X", "A0.W", "A1.W",
264 
  "A0", "A1", "I0", "I1", "I2", "I3", "M0", "M1",
265 
  "M2", "M3", "B0", "B1", "B2", "B3", "L0", "L1",
266 
  "L2", "L3",
267 
  "AZ", "AN", "AC0", "AC1", "AV0", "AV1", "AV0S", "AV1S",
268 
  "AQ", "V", "VS",
269 
  "sftreset", "omode", "excause", "emucause", "idle_req", "hwerrcause", "CC", "LC0",
270 
  "LC1", "GP", "ASTAT", "RETS", "LT0", "LB0", "LT1", "LB1",
271 
  "CYCLES", "CYCLES2", "USP", "SEQSTAT", "SYSCFG", "RETI", "RETX", "RETN",
272 
  "RETE", "EMUDAT",
273 
  "R0.B", "R1.B", "R2.B", "R3.B", "R4.B", "R5.B", "R6.B", "R7.B",
274 
  "P0.L", "P1.L", "P2.L", "P3.L", "P4.L", "P5.L", "SP.L", "FP.L",
275 
  "P0.H", "P1.H", "P2.H", "P3.H", "P4.H", "P5.H", "SP.H", "FP.H",
276 
  "I0.L", "I1.L", "I2.L", "I3.L", "M0.L", "M1.L", "M2.L", "M3.L",
277 
  "B0.L", "B1.L", "B2.L", "B3.L", "L0.L", "L1.L", "L2.L", "L3.L",
278 
  "I0.H", "I1.H", "I2.H", "I3.H", "M0.H", "M1.H", "M2.H", "M3.H",
279 
  "B0.H", "B1.H", "B2.H", "B3.H", "L0.H", "L1.H", "L2.H", "L3.H",
280 
  "LASTREG",
281 
 
282 
};
283 
 
284 
#define REGNAME(x) ((x) < REG_LASTREG ? (reg_names[x]) : "...... Illegal register .......")
285 
 
286 
/* RL(0..7).  */
287 
static enum machine_registers decode_dregs_lo[] =
288 
{
289 
  REG_RL0, REG_RL1, REG_RL2, REG_RL3, REG_RL4, REG_RL5, REG_RL6, REG_RL7,
290 
};
291 
 
292 
#define dregs_lo(x) REGNAME (decode_dregs_lo[(x) & 7])
293 
 
294 
/* RH(0..7).  */
295 
static enum machine_registers decode_dregs_hi[] =
296 
{
297 
  REG_RH0, REG_RH1, REG_RH2, REG_RH3, REG_RH4, REG_RH5, REG_RH6, REG_RH7,
298 
};
299 
 
300 
#define dregs_hi(x) REGNAME (decode_dregs_hi[(x) & 7])
301 
 
302 
/* R(0..7).  */
303 
static enum machine_registers decode_dregs[] =
304 
{
305 
  REG_R0, REG_R1, REG_R2, REG_R3, REG_R4, REG_R5, REG_R6, REG_R7,
306 
};
307 
 
308 
#define dregs(x) REGNAME (decode_dregs[(x) & 7])
309 
 
310 
/* R BYTE(0..7).  */
311 
static enum machine_registers decode_dregs_byte[] =
312 
{
313 
  REG_BR0, REG_BR1, REG_BR2, REG_BR3, REG_BR4, REG_BR5, REG_BR6, REG_BR7,
314 
};
315 
 
316 
#define dregs_byte(x) REGNAME (decode_dregs_byte[(x) & 7])
317 
 
318 
/* P(0..5) SP FP.  */
319 
static enum machine_registers decode_pregs[] =
320 
{
321 
  REG_P0, REG_P1, REG_P2, REG_P3, REG_P4, REG_P5, REG_SP, REG_FP,
322 
};
323 
 
324 
#define pregs(x)        REGNAME (decode_pregs[(x) & 7])
325 
#define spfp(x)         REGNAME (decode_spfp[(x) & 1])
326 
#define dregs_hilo(x,i) REGNAME (decode_dregs_hilo[((i) << 3)|x])
327 
#define accum_ext(x)    REGNAME (decode_accum_ext[(x) & 1])
328 
#define accum_word(x)   REGNAME (decode_accum_word[(x) & 1])
329 
#define accum(x)        REGNAME (decode_accum[(x) & 1])
330 
 
331 
/* I(0..3).  */
332 
static enum machine_registers decode_iregs[] =
333 
{
334 
  REG_I0, REG_I1, REG_I2, REG_I3,
335 
};
336 
 
337 
#define iregs(x) REGNAME (decode_iregs[(x) & 3])
338 
 
339 
/* M(0..3).  */
340 
static enum machine_registers decode_mregs[] =
341 
{
342 
  REG_M0, REG_M1, REG_M2, REG_M3,
343 
};
344 
 
345 
#define mregs(x) REGNAME (decode_mregs[(x) & 3])
346 
#define bregs(x) REGNAME (decode_bregs[(x) & 3])
347 
#define lregs(x) REGNAME (decode_lregs[(x) & 3])
348 
 
349 
/* dregs pregs.  */
350 
static enum machine_registers decode_dpregs[] =
351 
{
352 
  REG_R0, REG_R1, REG_R2, REG_R3, REG_R4, REG_R5, REG_R6, REG_R7,
353 
  REG_P0, REG_P1, REG_P2, REG_P3, REG_P4, REG_P5, REG_SP, REG_FP,
354 
};
355 
 
356 
#define dpregs(x) REGNAME (decode_dpregs[(x) & 15])
357 
 
358 
/* [dregs pregs].  */
359 
static enum machine_registers decode_gregs[] =
360 
{
361 
  REG_R0, REG_R1, REG_R2, REG_R3, REG_R4, REG_R5, REG_R6, REG_R7,
362 
  REG_P0, REG_P1, REG_P2, REG_P3, REG_P4, REG_P5, REG_SP, REG_FP,
363 
};
364 
 
365 
#define gregs(x,i) REGNAME (decode_gregs[((i) << 3)|x])
366 
 
367 
/* [dregs pregs (iregs mregs) (bregs lregs)].  */
368 
static enum machine_registers decode_regs[] =
369 
{
370 
  REG_R0, REG_R1, REG_R2, REG_R3, REG_R4, REG_R5, REG_R6, REG_R7,
371 
  REG_P0, REG_P1, REG_P2, REG_P3, REG_P4, REG_P5, REG_SP, REG_FP,
372 
  REG_I0, REG_I1, REG_I2, REG_I3, REG_M0, REG_M1, REG_M2, REG_M3,
373 
  REG_B0, REG_B1, REG_B2, REG_B3, REG_L0, REG_L1, REG_L2, REG_L3,
374 
};
375 
 
376 
#define regs(x,i) REGNAME (decode_regs[((i) << 3)|x])
377 
 
378 
/* [dregs pregs (iregs mregs) (bregs lregs) Low Half].  */
379 
static enum machine_registers decode_regs_lo[] =
380 
{
381 
  REG_RL0, REG_RL1, REG_RL2, REG_RL3, REG_RL4, REG_RL5, REG_RL6, REG_RL7,
382 
  REG_PL0, REG_PL1, REG_PL2, REG_PL3, REG_PL4, REG_PL5, REG_SLP, REG_FLP,
383 
  REG_IL0, REG_IL1, REG_IL2, REG_IL3, REG_ML0, REG_ML1, REG_ML2, REG_ML3,
384 
  REG_BL0, REG_BL1, REG_BL2, REG_BL3, REG_LL0, REG_LL1, REG_LL2, REG_LL3,
385 
};
386 
 
387 
#define regs_lo(x,i) REGNAME (decode_regs_lo[((i) << 3)|x])
388 
/* [dregs pregs (iregs mregs) (bregs lregs) High Half].  */
389 
static enum machine_registers decode_regs_hi[] =
390 
{
391 
  REG_RH0, REG_RH1, REG_RH2, REG_RH3, REG_RH4, REG_RH5, REG_RH6, REG_RH7,
392 
  REG_PH0, REG_PH1, REG_PH2, REG_PH3, REG_PH4, REG_PH5, REG_SHP, REG_FHP,
393 
  REG_IH0, REG_IH1, REG_IH2, REG_IH3, REG_MH0, REG_MH1, REG_MH2, REG_MH3,
394 
  REG_BH0, REG_BH1, REG_BH2, REG_BH3, REG_LH0, REG_LH1, REG_LH2, REG_LH3,
395 
};
396 
 
397 
#define regs_hi(x,i) REGNAME (decode_regs_hi[((i) << 3)|x])
398 
 
399 
static enum machine_registers decode_statbits[] =
400 
{
401 
  REG_AZ, REG_AN, REG_LASTREG, REG_LASTREG, REG_LASTREG, REG_LASTREG, REG_AQ, REG_LASTREG,
402 
  REG_LASTREG, REG_LASTREG, REG_LASTREG, REG_LASTREG, REG_AC0, REG_AC1, REG_LASTREG, REG_LASTREG,
403 
  REG_AV0, REG_AV0S, REG_AV1, REG_AV1S, REG_LASTREG, REG_LASTREG, REG_LASTREG, REG_LASTREG,
404 
  REG_V, REG_VS, REG_LASTREG, REG_LASTREG, REG_LASTREG, REG_LASTREG, REG_LASTREG, REG_LASTREG,
405 
};
406 
 
407 
#define statbits(x) REGNAME (decode_statbits[(x) & 31])
408 
 
409 
/* LC0 LC1.  */
410 
static enum machine_registers decode_counters[] =
411 
{
412 
  REG_LC0, REG_LC1,
413 
};
414 
 
415 
#define counters(x)        REGNAME (decode_counters[(x) & 1])
416 
#define dregs2_sysregs1(x) REGNAME (decode_dregs2_sysregs1[(x) & 7])
417 
 
418 
/* [dregs pregs (iregs mregs) (bregs lregs)
419 
   dregs2_sysregs1 open sysregs2 sysregs3].  */
420 
static enum machine_registers decode_allregs[] =
421 
{
422 
  REG_R0, REG_R1, REG_R2, REG_R3, REG_R4, REG_R5, REG_R6, REG_R7,
423 
  REG_P0, REG_P1, REG_P2, REG_P3, REG_P4, REG_P5, REG_SP, REG_FP,
424 
  REG_I0, REG_I1, REG_I2, REG_I3, REG_M0, REG_M1, REG_M2, REG_M3,
425 
  REG_B0, REG_B1, REG_B2, REG_B3, REG_L0, REG_L1, REG_L2, REG_L3,
426 
  REG_A0x, REG_A0w, REG_A1x, REG_A1w, REG_GP, REG_LASTREG, REG_ASTAT, REG_RETS,
427 
  REG_LASTREG, REG_LASTREG, REG_LASTREG, REG_LASTREG, REG_LASTREG, REG_LASTREG, REG_LASTREG, REG_LASTREG,
428 
  REG_LC0, REG_LT0, REG_LB0, REG_LC1, REG_LT1, REG_LB1, REG_CYCLES, REG_CYCLES2,
429 
  REG_USP, REG_SEQSTAT, REG_SYSCFG, REG_RETI, REG_RETX, REG_RETN, REG_RETE, REG_EMUDAT,
430 
  REG_LASTREG,
431 
};
432 
 
433 
#define IS_DREG(g,r)    ((g) == 0)
434 
#define IS_PREG(g,r)    ((g) == 1)
435 
#define IS_AREG(g,r)    ((g) == 4 && (r) >= 0 && (r) < 4)
436 
#define IS_GENREG(g,r)  ((g) == 0 || (g) == 1 || IS_AREG (g, r))
437 
#define IS_DAGREG(g,r)  ((g) == 2 || (g) == 3)
438 
#define IS_SYSREG(g,r) \
439 
  (((g) == 4 && ((r) == 6 || (r) == 7)) || (g) == 6 || (g) == 7)
440 
 
441 
#define allregs(x,i)    REGNAME (decode_allregs[((i) << 3) | x])
442 
#define uimm16s4(x)     fmtconst (c_uimm16s4, x, 0, outf)
443 
#define uimm16s4d(x)    fmtconst (c_uimm16s4d, x, 0, outf)
444 
#define pcrel4(x)       fmtconst (c_pcrel4, x, pc, outf)
445 
#define pcrel8(x)       fmtconst (c_pcrel8, x, pc, outf)
446 
#define pcrel8s4(x)     fmtconst (c_pcrel8s4, x, pc, outf)
447 
#define pcrel10(x)      fmtconst (c_pcrel10, x, pc, outf)
448 
#define pcrel12(x)      fmtconst (c_pcrel12, x, pc, outf)
449 
#define negimm5s4(x)    fmtconst (c_negimm5s4, x, 0, outf)
450 
#define rimm16(x)       fmtconst (c_rimm16, x, 0, outf)
451 
#define huimm16(x)      fmtconst (c_huimm16, x, 0, outf)
452 
#define imm16(x)        fmtconst (c_imm16, x, 0, outf)
453 
#define imm16d(x)       fmtconst (c_imm16d, x, 0, outf)
454 
#define uimm2(x)        fmtconst (c_uimm2, x, 0, outf)
455 
#define uimm3(x)        fmtconst (c_uimm3, x, 0, outf)
456 
#define luimm16(x)      fmtconst (c_luimm16, x, 0, outf)
457 
#define uimm4(x)        fmtconst (c_uimm4, x, 0, outf)
458 
#define uimm5(x)        fmtconst (c_uimm5, x, 0, outf)
459 
#define imm16s2(x)      fmtconst (c_imm16s2, x, 0, outf)
460 
#define uimm8(x)        fmtconst (c_uimm8, x, 0, outf)
461 
#define imm16s4(x)      fmtconst (c_imm16s4, x, 0, outf)
462 
#define uimm4s2(x)      fmtconst (c_uimm4s2, x, 0, outf)
463 
#define uimm4s4(x)      fmtconst (c_uimm4s4, x, 0, outf)
464 
#define uimm4s4d(x)     fmtconst (c_uimm4s4d, x, 0, outf)
465 
#define lppcrel10(x)    fmtconst (c_lppcrel10, x, pc, outf)
466 
#define imm3(x)         fmtconst (c_imm3, x, 0, outf)
467 
#define imm4(x)         fmtconst (c_imm4, x, 0, outf)
468 
#define uimm8s4(x)      fmtconst (c_uimm8s4, x, 0, outf)
469 
#define imm5(x)         fmtconst (c_imm5, x, 0, outf)
470 
#define imm5d(x)        fmtconst (c_imm5d, x, 0, outf)
471 
#define imm6(x)         fmtconst (c_imm6, x, 0, outf)
472 
#define imm7(x)         fmtconst (c_imm7, x, 0, outf)
473 
#define imm7d(x)        fmtconst (c_imm7d, x, 0, outf)
474 
#define imm8(x)         fmtconst (c_imm8, x, 0, outf)
475 
#define pcrel24(x)      fmtconst (c_pcrel24, x, pc, outf)
476 
#define uimm16(x)       fmtconst (c_uimm16, x, 0, outf)
477 
#define uimm32(x)       fmtconst (c_uimm32, x, 0, outf)
478 
#define imm32(x)        fmtconst (c_imm32, x, 0, outf)
479 
#define huimm32(x)      fmtconst (c_huimm32, x, 0, outf)
480 
#define huimm32e(x)     fmtconst (c_huimm32e, x, 0, outf)
481 
#define imm7_val(x)     fmtconst_val (c_imm7, x, 0)
482 
#define imm16_val(x)    fmtconst_val (c_uimm16, x, 0)
483 
#define luimm16_val(x)  fmtconst_val (c_luimm16, x, 0)
484 
 
485 
/* (arch.pm)arch_disassembler_functions.  */
486 
#ifndef OUTS
487 
#define OUTS(p, txt) ((p) ? (((txt)[0]) ? (p->fprintf_func)(p->stream, "%s", txt) :0) :0)
488 
#endif
489 
 
490 
static void
491 
amod0 (int s0, int x0, disassemble_info *outf)
492 
{
493 
  if (s0 == 1 && x0 == 0)
494 
    OUTS (outf, " (S)");
495 
  else if (s0 == 0 && x0 == 1)
496 
    OUTS (outf, " (CO)");
497 
  else if (s0 == 1 && x0 == 1)
498 
    OUTS (outf, " (SCO)");
499 
}
500 
 
501 
static void
502 
amod1 (int s0, int x0, disassemble_info *outf)
503 
{
504 
  if (s0 == 0 && x0 == 0)
505 
    OUTS (outf, " (NS)");
506 
  else if (s0 == 1 && x0 == 0)
507 
    OUTS (outf, " (S)");
508 
}
509 
 
510 
static void
511 
amod0amod2 (int s0, int x0, int aop0, disassemble_info *outf)
512 
{
513 
  if (s0 == 1 && x0 == 0 && aop0 == 0)
514 
    OUTS (outf, " (S)");
515 
  else if (s0 == 0 && x0 == 1 && aop0 == 0)
516 
    OUTS (outf, " (CO)");
517 
  else if (s0 == 1 && x0 == 1 && aop0 == 0)
518 
    OUTS (outf, " (SCO)");
519 
  else if (s0 == 0 && x0 == 0 && aop0 == 2)
520 
    OUTS (outf, " (ASR)");
521 
  else if (s0 == 1 && x0 == 0 && aop0 == 2)
522 
    OUTS (outf, " (S, ASR)");
523 
  else if (s0 == 0 && x0 == 1 && aop0 == 2)
524 
    OUTS (outf, " (CO, ASR)");
525 
  else if (s0 == 1 && x0 == 1 && aop0 == 2)
526 
    OUTS (outf, " (SCO, ASR)");
527 
  else if (s0 == 0 && x0 == 0 && aop0 == 3)
528 
    OUTS (outf, " (ASL)");
529 
  else if (s0 == 1 && x0 == 0 && aop0 == 3)
530 
    OUTS (outf, " (S, ASL)");
531 
  else if (s0 == 0 && x0 == 1 && aop0 == 3)
532 
    OUTS (outf, " (CO, ASL)");
533 
  else if (s0 == 1 && x0 == 1 && aop0 == 3)
534 
    OUTS (outf, " (SCO, ASL)");
535 
}
536 
 
537 
static void
538 
searchmod (int r0, disassemble_info *outf)
539 
{
540 
  if (r0 == 0)
541 
    OUTS (outf, "GT");
542 
  else if (r0 == 1)
543 
    OUTS (outf, "GE");
544 
  else if (r0 == 2)
545 
    OUTS (outf, "LT");
546 
  else if (r0 == 3)
547 
    OUTS (outf, "LE");
548 
}
549 
 
550 
static void
551 
aligndir (int r0, disassemble_info *outf)
552 
{
553 
  if (r0 == 1)
554 
    OUTS (outf, " (R)");
555 
}
556 
 
557 
static int
558 
decode_multfunc (int h0, int h1, int src0, int src1, disassemble_info * outf)
559 
{
560 
  char *s0, *s1;
561 
 
562 
  if (h0)
563 
    s0 = dregs_hi (src0);
564 
  else
565 
    s0 = dregs_lo (src0);
566 
 
567 
  if (h1)
568 
    s1 = dregs_hi (src1);
569 
  else
570 
    s1 = dregs_lo (src1);
571 
 
572 
  OUTS (outf, s0);
573 
  OUTS (outf, " * ");
574 
  OUTS (outf, s1);
575 
  return 0;
576 
}
577 
 
578 
static int
579 
decode_macfunc (int which, int op, int h0, int h1, int src0, int src1, disassemble_info * outf)
580 
{
581 
  char *a;
582 
  char *sop = "<unknown op>";
583 
 
584 
  if (which)
585 
    a = "A1";
586 
  else
587 
    a = "A0";
588 
 
589 
  if (op == 3)
590 
    {
591 
      OUTS (outf, a);
592 
      return 0;
593 
    }
594 
 
595 
  switch (op)
596 
    {
597 
    case 0: sop = " = ";   break;
598 
    case 1: sop = " += ";  break;
599 
    case 2: sop = " -= ";  break;
600 
    default: break;
601 
    }
602 
 
603 
  OUTS (outf, a);
604 
  OUTS (outf, sop);
605 
  decode_multfunc (h0, h1, src0, src1, outf);
606 
 
607 
  return 0;
608 
}
609 
 
610 
static void
611 
decode_optmode (int mod, int MM, disassemble_info *outf)
612 
{
613 
  if (mod == 0 && MM == 0)
614 
    return;
615 
 
616 
  OUTS (outf, " (");
617 
 
618 
  if (MM && !mod)
619 
    {
620 
      OUTS (outf, "M)");
621 
      return;
622 
    }
623 
 
624 
  if (MM)
625 
    OUTS (outf, "M, ");
626 
 
627 
  if (mod == M_S2RND)
628 
    OUTS (outf, "S2RND");
629 
  else if (mod == M_T)
630 
    OUTS (outf, "T");
631 
  else if (mod == M_W32)
632 
    OUTS (outf, "W32");
633 
  else if (mod == M_FU)
634 
    OUTS (outf, "FU");
635 
  else if (mod == M_TFU)
636 
    OUTS (outf, "TFU");
637 
  else if (mod == M_IS)
638 
    OUTS (outf, "IS");
639 
  else if (mod == M_ISS2)
640 
    OUTS (outf, "ISS2");
641 
  else if (mod == M_IH)
642 
    OUTS (outf, "IH");
643 
  else if (mod == M_IU)
644 
    OUTS (outf, "IU");
645 
  else
646 
    abort ();
647 
 
648 
  OUTS (outf, ")");
649 
}
650 
 
651 
struct saved_state
652 
{
653 
  bu32 dpregs[16], iregs[4], mregs[4], bregs[4], lregs[4];
654 
  bu32 a0x, a0w, a1x, a1w;
655 
  bu32 lt[2], lc[2], lb[2];
656 
  int ac0, ac0_copy, ac1, an, aq;
657 
  int av0, av0s, av1, av1s, az, cc, v, v_copy, vs;
658 
  int rnd_mod;
659 
  int v_internal;
660 
  bu32 pc, rets;
661 
 
662 
  int ticks;
663 
  int insts;
664 
 
665 
  int exception;
666 
 
667 
  int end_of_registers;
668 
 
669 
  int msize;
670 
  unsigned char *memory;
671 
  unsigned long bfd_mach;
672 
}  saved_state;
673 
 
674 
#define DREG(x)         (saved_state.dpregs[x])
675 
#define GREG(x,i)       DPREG ((x) | (i << 3))
676 
#define DPREG(x)        (saved_state.dpregs[x])
677 
#define DREG(x)         (saved_state.dpregs[x])
678 
#define PREG(x)         (saved_state.dpregs[x + 8])
679 
#define SPREG           PREG (6)
680 
#define FPREG           PREG (7)
681 
#define IREG(x)         (saved_state.iregs[x])
682 
#define MREG(x)         (saved_state.mregs[x])
683 
#define BREG(x)         (saved_state.bregs[x])
684 
#define LREG(x)         (saved_state.lregs[x])
685 
#define A0XREG          (saved_state.a0x)
686 
#define A0WREG          (saved_state.a0w)
687 
#define A1XREG          (saved_state.a1x)
688 
#define A1WREG          (saved_state.a1w)
689 
#define CCREG           (saved_state.cc)
690 
#define LC0REG          (saved_state.lc[0])
691 
#define LT0REG          (saved_state.lt[0])
692 
#define LB0REG          (saved_state.lb[0])
693 
#define LC1REG          (saved_state.lc[1])
694 
#define LT1REG          (saved_state.lt[1])
695 
#define LB1REG          (saved_state.lb[1])
696 
#define RETSREG         (saved_state.rets)
697 
#define PCREG           (saved_state.pc)
698 
 
699 
static bu32 *
700 
get_allreg (int grp, int reg)
701 
{
702 
  int fullreg = (grp << 3) | reg;
703 
  /* REG_R0, REG_R1, REG_R2, REG_R3, REG_R4, REG_R5, REG_R6, REG_R7,
704 
     REG_P0, REG_P1, REG_P2, REG_P3, REG_P4, REG_P5, REG_SP, REG_FP,
705 
     REG_I0, REG_I1, REG_I2, REG_I3, REG_M0, REG_M1, REG_M2, REG_M3,
706 
     REG_B0, REG_B1, REG_B2, REG_B3, REG_L0, REG_L1, REG_L2, REG_L3,
707 
     REG_A0x, REG_A0w, REG_A1x, REG_A1w, , , REG_ASTAT, REG_RETS,
708 
     , , , , , , , ,
709 
     REG_LC0, REG_LT0, REG_LB0, REG_LC1, REG_LT1, REG_LB1, REG_CYCLES,
710 
     REG_CYCLES2,
711 
     REG_USP, REG_SEQSTAT, REG_SYSCFG, REG_RETI, REG_RETX, REG_RETN, REG_RETE,
712 
     REG_LASTREG */
713 
  switch (fullreg >> 2)
714 
    {
715 
    case 0: case 1: return &DREG (reg); break;
716 
    case 2: case 3: return &PREG (reg); break;
717 
    case 4: return &IREG (reg & 3); break;
718 
    case 5: return &MREG (reg & 3); break;
719 
    case 6: return &BREG (reg & 3); break;
720 
    case 7: return &LREG (reg & 3); break;
721 
    default:
722 
      switch (fullreg)
723 
        {
724 
        case 32: return &saved_state.a0x;
725 
        case 33: return &saved_state.a0w;
726 
        case 34: return &saved_state.a1x;
727 
        case 35: return &saved_state.a1w;
728 
        case 39: return &saved_state.rets;
729 
        case 48: return &LC0REG;
730 
        case 49: return &LT0REG;
731 
        case 50: return &LB0REG;
732 
        case 51: return &LC1REG;
733 
        case 52: return &LT1REG;
734 
        case 53: return &LB1REG;
735 
        }
736 
      return 0;
737 
    }
738 
}
739 
 
740 
static int
741 
decode_ProgCtrl_0 (TIword iw0, disassemble_info *outf)
742 
{
743 
  /* ProgCtrl
744 
     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
745 
     | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |.prgfunc.......|.poprnd........|
746 
     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+  */
747 
  int poprnd  = ((iw0 >> ProgCtrl_poprnd_bits) & ProgCtrl_poprnd_mask);
748 
  int prgfunc = ((iw0 >> ProgCtrl_prgfunc_bits) & ProgCtrl_prgfunc_mask);
749 
 
750 
  if (prgfunc == 0 && poprnd == 0)
751 
    OUTS (outf, "NOP");
752 
  else if (prgfunc == 1 && poprnd == 0)
753 
    OUTS (outf, "RTS");
754 
  else if (prgfunc == 1 && poprnd == 1)
755 
    OUTS (outf, "RTI");
756 
  else if (prgfunc == 1 && poprnd == 2)
757 
    OUTS (outf, "RTX");
758 
  else if (prgfunc == 1 && poprnd == 3)
759 
    OUTS (outf, "RTN");
760 
  else if (prgfunc == 1 && poprnd == 4)
761 
    OUTS (outf, "RTE");
762 
  else if (prgfunc == 2 && poprnd == 0)
763 
    OUTS (outf, "IDLE");
764 
  else if (prgfunc == 2 && poprnd == 3)
765 
    OUTS (outf, "CSYNC");
766 
  else if (prgfunc == 2 && poprnd == 4)
767 
    OUTS (outf, "SSYNC");
768 
  else if (prgfunc == 2 && poprnd == 5)
769 
    OUTS (outf, "EMUEXCPT");
770 
  else if (prgfunc == 3)
771 
    {
772 
      OUTS (outf, "CLI ");
773 
      OUTS (outf, dregs (poprnd));
774 
    }
775 
  else if (prgfunc == 4)
776 
    {
777 
      OUTS (outf, "STI ");
778 
      OUTS (outf, dregs (poprnd));
779 
    }
780 
  else if (prgfunc == 5)
781 
    {
782 
      OUTS (outf, "JUMP (");
783 
      OUTS (outf, pregs (poprnd));
784 
      OUTS (outf, ")");
785 
    }
786 
  else if (prgfunc == 6)
787 
    {
788 
      OUTS (outf, "CALL (");
789 
      OUTS (outf, pregs (poprnd));
790 
      OUTS (outf, ")");
791 
    }
792 
  else if (prgfunc == 7)
793 
    {
794 
      OUTS (outf, "CALL (PC + ");
795 
      OUTS (outf, pregs (poprnd));
796 
      OUTS (outf, ")");
797 
    }
798 
  else if (prgfunc == 8)
799 
    {
800 
      OUTS (outf, "JUMP (PC + ");
801 
      OUTS (outf, pregs (poprnd));
802 
      OUTS (outf, ")");
803 
    }
804 
  else if (prgfunc == 9)
805 
    {
806 
      OUTS (outf, "RAISE ");
807 
      OUTS (outf, uimm4 (poprnd));
808 
    }
809 
  else if (prgfunc == 10)
810 
    {
811 
      OUTS (outf, "EXCPT ");
812 
      OUTS (outf, uimm4 (poprnd));
813 
    }
814 
  else if (prgfunc == 11)
815 
    {
816 
      OUTS (outf, "TESTSET (");
817 
      OUTS (outf, pregs (poprnd));
818 
      OUTS (outf, ")");
819 
    }
820 
  else
821 
    return 0;
822 
  return 2;
823 
}
824 
 
825 
static int
826 
decode_CaCTRL_0 (TIword iw0, disassemble_info *outf)
827 
{
828 
  /* CaCTRL
829 
     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
830 
     | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 |.a.|.op....|.reg.......|
831 
     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+  */
832 
  int a   = ((iw0 >> CaCTRL_a_bits) & CaCTRL_a_mask);
833 
  int op  = ((iw0 >> CaCTRL_op_bits) & CaCTRL_op_mask);
834 
  int reg = ((iw0 >> CaCTRL_reg_bits) & CaCTRL_reg_mask);
835 
 
836 
  if (a == 0 && op == 0)
837 
    {
838 
      OUTS (outf, "PREFETCH[");
839 
      OUTS (outf, pregs (reg));
840 
      OUTS (outf, "]");
841 
    }
842 
  else if (a == 0 && op == 1)
843 
    {
844 
      OUTS (outf, "FLUSHINV[");
845 
      OUTS (outf, pregs (reg));
846 
      OUTS (outf, "]");
847 
    }
848 
  else if (a == 0 && op == 2)
849 
    {
850 
      OUTS (outf, "FLUSH[");
851 
      OUTS (outf, pregs (reg));
852 
      OUTS (outf, "]");
853 
    }
854 
  else if (a == 0 && op == 3)
855 
    {
856 
      OUTS (outf, "IFLUSH[");
857 
      OUTS (outf, pregs (reg));
858 
      OUTS (outf, "]");
859 
    }
860 
  else if (a == 1 && op == 0)
861 
    {
862 
      OUTS (outf, "PREFETCH[");
863 
      OUTS (outf, pregs (reg));
864 
      OUTS (outf, "++]");
865 
    }
866 
  else if (a == 1 && op == 1)
867 
    {
868 
      OUTS (outf, "FLUSHINV[");
869 
      OUTS (outf, pregs (reg));
870 
      OUTS (outf, "++]");
871 
    }
872 
  else if (a == 1 && op == 2)
873 
    {
874 
      OUTS (outf, "FLUSH[");
875 
      OUTS (outf, pregs (reg));
876 
      OUTS (outf, "++]");
877 
    }
878 
  else if (a == 1 && op == 3)
879 
    {
880 
      OUTS (outf, "IFLUSH[");
881 
      OUTS (outf, pregs (reg));
882 
      OUTS (outf, "++]");
883 
    }
884 
  else
885 
    return 0;
886 
  return 2;
887 
}
888 
 
889 
static int
890 
decode_PushPopReg_0 (TIword iw0, disassemble_info *outf)
891 
{
892 
  /* PushPopReg
893 
     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
894 
     | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 |.W.|.grp.......|.reg.......|
895 
     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+  */
896 
  int W   = ((iw0 >> PushPopReg_W_bits) & PushPopReg_W_mask);
897 
  int grp = ((iw0 >> PushPopReg_grp_bits) & PushPopReg_grp_mask);
898 
  int reg = ((iw0 >> PushPopReg_reg_bits) & PushPopReg_reg_mask);
899 
 
900 
  if (W == 0)
901 
    {
902 
      OUTS (outf, allregs (reg, grp));
903 
      OUTS (outf, " = [SP++]");
904 
    }
905 
  else if (W == 1)
906 
    {
907 
      OUTS (outf, "[--SP] = ");
908 
      OUTS (outf, allregs (reg, grp));
909 
    }
910 
  else
911 
    return 0;
912 
  return 2;
913 
}
914 
 
915 
static int
916 
decode_PushPopMultiple_0 (TIword iw0, disassemble_info *outf)
917 
{
918 
  /* PushPopMultiple
919 
     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
920 
     | 0 | 0 | 0 | 0 | 0 | 1 | 0 |.d.|.p.|.W.|.dr........|.pr........|
921 
     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+  */
922 
  int p  = ((iw0 >> PushPopMultiple_p_bits) & PushPopMultiple_p_mask);
923 
  int d  = ((iw0 >> PushPopMultiple_d_bits) & PushPopMultiple_d_mask);
924 
  int W  = ((iw0 >> PushPopMultiple_W_bits) & PushPopMultiple_W_mask);
925 
  int dr = ((iw0 >> PushPopMultiple_dr_bits) & PushPopMultiple_dr_mask);
926 
  int pr = ((iw0 >> PushPopMultiple_pr_bits) & PushPopMultiple_pr_mask);
927 
 
928 
  if (W == 1 && d == 1 && p == 1)
929 
    {
930 
      OUTS (outf, "[--SP] = (R7:");
931 
      OUTS (outf, imm5d (dr));
932 
      OUTS (outf, ", P5:");
933 
      OUTS (outf, imm5d (pr));
934 
      OUTS (outf, ")");
935 
    }
936 
  else if (W == 1 && d == 1 && p == 0)
937 
    {
938 
      OUTS (outf, "[--SP] = (R7:");
939 
      OUTS (outf, imm5d (dr));
940 
      OUTS (outf, ")");
941 
    }
942 
  else if (W == 1 && d == 0 && p == 1)
943 
    {
944 
      OUTS (outf, "[--SP] = (P5:");
945 
      OUTS (outf, imm5d (pr));
946 
      OUTS (outf, ")");
947 
    }
948 
  else if (W == 0 && d == 1 && p == 1)
949 
    {
950 
      OUTS (outf, "(R7:");
951 
      OUTS (outf, imm5d (dr));
952 
      OUTS (outf, ", P5:");
953 
      OUTS (outf, imm5d (pr));
954 
      OUTS (outf, ") = [SP++]");
955 
    }
956 
  else if (W == 0 && d == 1 && p == 0)
957 
    {
958 
      OUTS (outf, "(R7:");
959 
      OUTS (outf, imm5d (dr));
960 
      OUTS (outf, ") = [SP++]");
961 
    }
962 
  else if (W == 0 && d == 0 && p == 1)
963 
    {
964 
      OUTS (outf, "(P5:");
965 
      OUTS (outf, imm5d (pr));
966 
      OUTS (outf, ") = [SP++]");
967 
    }
968 
  else
969 
    return 0;
970 
  return 2;
971 
}
972 
 
973 
static int
974 
decode_ccMV_0 (TIword iw0, disassemble_info *outf)
975 
{
976 
  /* ccMV
977 
     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
978 
     | 0 | 0 | 0 | 0 | 0 | 1 | 1 |.T.|.d.|.s.|.dst.......|.src.......|
979 
     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+  */
980 
  int s  = ((iw0 >> CCmv_s_bits) & CCmv_s_mask);
981 
  int d  = ((iw0 >> CCmv_d_bits) & CCmv_d_mask);
982 
  int T  = ((iw0 >> CCmv_T_bits) & CCmv_T_mask);
983 
  int src = ((iw0 >> CCmv_src_bits) & CCmv_src_mask);
984 
  int dst = ((iw0 >> CCmv_dst_bits) & CCmv_dst_mask);
985 
 
986 
  if (T == 1)
987 
    {
988 
      OUTS (outf, "IF CC ");
989 
      OUTS (outf, gregs (dst, d));
990 
      OUTS (outf, " = ");
991 
      OUTS (outf, gregs (src, s));
992 
    }
993 
  else if (T == 0)
994 
    {
995 
      OUTS (outf, "IF !CC ");
996 
      OUTS (outf, gregs (dst, d));
997 
      OUTS (outf, " = ");
998 
      OUTS (outf, gregs (src, s));
999 
    }
1000 
  else
1001 
    return 0;
1002 
  return 2;
1003 
}
1004 
 
1005 
static int
1006 
decode_CCflag_0 (TIword iw0, disassemble_info *outf)
1007 
{
1008 
  /* CCflag
1009 
     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1010 
     | 0 | 0 | 0 | 0 | 1 |.I.|.opc.......|.G.|.y.........|.x.........|
1011 
     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+  */
1012 
  int x = ((iw0 >> CCflag_x_bits) & CCflag_x_mask);
1013 
  int y = ((iw0 >> CCflag_y_bits) & CCflag_y_mask);
1014 
  int I = ((iw0 >> CCflag_I_bits) & CCflag_I_mask);
1015 
  int G = ((iw0 >> CCflag_G_bits) & CCflag_G_mask);
1016 
  int opc = ((iw0 >> CCflag_opc_bits) & CCflag_opc_mask);
1017 
 
1018 
  if (opc == 0 && I == 0 && G == 0)
1019 
    {
1020 
      OUTS (outf, "CC = ");
1021 
      OUTS (outf, dregs (x));
1022 
      OUTS (outf, " == ");
1023 
      OUTS (outf, dregs (y));
1024 
    }
1025 
  else if (opc == 1 && I == 0 && G == 0)
1026 
    {
1027 
      OUTS (outf, "CC = ");
1028 
      OUTS (outf, dregs (x));
1029 
      OUTS (outf, " < ");
1030 
      OUTS (outf, dregs (y));
1031 
    }
1032 
  else if (opc == 2 && I == 0 && G == 0)
1033 
    {
1034 
      OUTS (outf, "CC = ");
1035 
      OUTS (outf, dregs (x));
1036 
      OUTS (outf, " <= ");
1037 
      OUTS (outf, dregs (y));
1038 
    }
1039 
  else if (opc == 3 && I == 0 && G == 0)
1040 
    {
1041 
      OUTS (outf, "CC = ");
1042 
      OUTS (outf, dregs (x));
1043 
      OUTS (outf, " < ");
1044 
      OUTS (outf, dregs (y));
1045 
      OUTS (outf, " (IU)");
1046 
    }
1047 
  else if (opc == 4 && I == 0 && G == 0)
1048 
    {
1049 
      OUTS (outf, "CC = ");
1050 
      OUTS (outf, dregs (x));
1051 
      OUTS (outf, " <= ");
1052 
      OUTS (outf, dregs (y));
1053 
      OUTS (outf, " (IU)");
1054 
    }
1055 
  else if (opc == 0 && I == 1 && G == 0)
1056 
    {
1057 
      OUTS (outf, "CC = ");
1058 
      OUTS (outf, dregs (x));
1059 
      OUTS (outf, " == ");
1060 
      OUTS (outf, imm3 (y));
1061 
    }
1062 
  else if (opc == 1 && I == 1 && G == 0)
1063 
    {
1064 
      OUTS (outf, "CC = ");
1065 
      OUTS (outf, dregs (x));
1066 
      OUTS (outf, " < ");
1067 
      OUTS (outf, imm3 (y));
1068 
    }
1069 
  else if (opc == 2 && I == 1 && G == 0)
1070 
    {
1071 
      OUTS (outf, "CC = ");
1072 
      OUTS (outf, dregs (x));
1073 
      OUTS (outf, " <= ");
1074 
      OUTS (outf, imm3 (y));
1075 
    }
1076 
  else if (opc == 3 && I == 1 && G == 0)
1077 
    {
1078 
      OUTS (outf, "CC = ");
1079 
      OUTS (outf, dregs (x));
1080 
      OUTS (outf, " < ");
1081 
      OUTS (outf, uimm3 (y));
1082 
      OUTS (outf, " (IU)");
1083 
    }
1084 
  else if (opc == 4 && I == 1 && G == 0)
1085 
    {
1086 
      OUTS (outf, "CC = ");
1087 
      OUTS (outf, dregs (x));
1088 
      OUTS (outf, " <= ");
1089 
      OUTS (outf, uimm3 (y));
1090 
      OUTS (outf, " (IU)");
1091 
    }
1092 
  else if (opc == 0 && I == 0 && G == 1)
1093 
    {
1094 
      OUTS (outf, "CC = ");
1095 
      OUTS (outf, pregs (x));
1096 
      OUTS (outf, " == ");
1097 
      OUTS (outf, pregs (y));
1098 
    }
1099 
  else if (opc == 1 && I == 0 && G == 1)
1100 
    {
1101 
      OUTS (outf, "CC = ");
1102 
      OUTS (outf, pregs (x));
1103 
      OUTS (outf, " < ");
1104 
      OUTS (outf, pregs (y));
1105 
    }
1106 
  else if (opc == 2 && I == 0 && G == 1)
1107 
    {
1108 
      OUTS (outf, "CC = ");
1109 
      OUTS (outf, pregs (x));
1110 
      OUTS (outf, " <= ");
1111 
      OUTS (outf, pregs (y));
1112 
    }
1113 
  else if (opc == 3 && I == 0 && G == 1)
1114 
    {
1115 
      OUTS (outf, "CC = ");
1116 
      OUTS (outf, pregs (x));
1117 
      OUTS (outf, " < ");
1118 
      OUTS (outf, pregs (y));
1119 
      OUTS (outf, " (IU)");
1120 
    }
1121 
  else if (opc == 4 && I == 0 && G == 1)
1122 
    {
1123 
      OUTS (outf, "CC = ");
1124 
      OUTS (outf, pregs (x));
1125 
      OUTS (outf, " <= ");
1126 
      OUTS (outf, pregs (y));
1127 
      OUTS (outf, " (IU)");
1128 
    }
1129 
  else if (opc == 0 && I == 1 && G == 1)
1130 
    {
1131 
      OUTS (outf, "CC = ");
1132 
      OUTS (outf, pregs (x));
1133 
      OUTS (outf, " == ");
1134 
      OUTS (outf, imm3 (y));
1135 
    }
1136 
  else if (opc == 1 && I == 1 && G == 1)
1137 
    {
1138 
      OUTS (outf, "CC = ");
1139 
      OUTS (outf, pregs (x));
1140 
      OUTS (outf, " < ");
1141 
      OUTS (outf, imm3 (y));
1142 
    }
1143 
  else if (opc == 2 && I == 1 && G == 1)
1144 
    {
1145 
      OUTS (outf, "CC = ");
1146 
      OUTS (outf, pregs (x));
1147 
      OUTS (outf, " <= ");
1148 
      OUTS (outf, imm3 (y));
1149 
    }
1150 
  else if (opc == 3 && I == 1 && G == 1)
1151 
    {
1152 
      OUTS (outf, "CC = ");
1153 
      OUTS (outf, pregs (x));
1154 
      OUTS (outf, " < ");
1155 
      OUTS (outf, uimm3 (y));
1156 
      OUTS (outf, " (IU)");
1157 
    }
1158 
  else if (opc == 4 && I == 1 && G == 1)
1159 
    {
1160 
      OUTS (outf, "CC = ");
1161 
      OUTS (outf, pregs (x));
1162 
      OUTS (outf, " <= ");
1163 
      OUTS (outf, uimm3 (y));
1164 
      OUTS (outf, " (IU)");
1165 
    }
1166 
  else if (opc == 5 && I == 0 && G == 0)
1167 
    OUTS (outf, "CC = A0 == A1");
1168 
 
1169 
  else if (opc == 6 && I == 0 && G == 0)
1170 
    OUTS (outf, "CC = A0 < A1");
1171 
 
1172 
  else if (opc == 7 && I == 0 && G == 0)
1173 
    OUTS (outf, "CC = A0 <= A1");
1174 
 
1175 
  else
1176 
    return 0;
1177 
  return 2;
1178 
}
1179 
 
1180 
static int
1181 
decode_CC2dreg_0 (TIword iw0, disassemble_info *outf)
1182 
{
1183 
  /* CC2dreg
1184 
     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1185 
     | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 |.op....|.reg.......|
1186 
     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+  */
1187 
  int op  = ((iw0 >> CC2dreg_op_bits) & CC2dreg_op_mask);
1188 
  int reg = ((iw0 >> CC2dreg_reg_bits) & CC2dreg_reg_mask);
1189 
 
1190 
  if (op == 0)
1191 
    {
1192 
      OUTS (outf, dregs (reg));
1193 
      OUTS (outf, " = CC");
1194 
    }
1195 
  else if (op == 1)
1196 
    {
1197 
      OUTS (outf, "CC = ");
1198 
      OUTS (outf, dregs (reg));
1199 
    }
1200 
  else if (op == 3)
1201 
    OUTS (outf, "CC = !CC");
1202 
  else
1203 
    return 0;
1204 
 
1205 
  return 2;
1206 
}
1207 
 
1208 
static int
1209 
decode_CC2stat_0 (TIword iw0, disassemble_info *outf)
1210 
{
1211 
  /* CC2stat
1212 
     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1213 
     | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 |.D.|.op....|.cbit..............|
1214 
     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+  */
1215 
  int D    = ((iw0 >> CC2stat_D_bits) & CC2stat_D_mask);
1216 
  int op   = ((iw0 >> CC2stat_op_bits) & CC2stat_op_mask);
1217 
  int cbit = ((iw0 >> CC2stat_cbit_bits) & CC2stat_cbit_mask);
1218 
 
1219 
  if (op == 0 && D == 0)
1220 
    {
1221 
      OUTS (outf, "CC = ");
1222 
      OUTS (outf, statbits (cbit));
1223 
    }
1224 
  else if (op == 1 && D == 0)
1225 
    {
1226 
      OUTS (outf, "CC |= ");
1227 
      OUTS (outf, statbits (cbit));
1228 
    }
1229 
  else if (op == 2 && D == 0)
1230 
    {
1231 
      OUTS (outf, "CC &= ");
1232 
      OUTS (outf, statbits (cbit));
1233 
    }
1234 
  else if (op == 3 && D == 0)
1235 
    {
1236 
      OUTS (outf, "CC ^= ");
1237 
      OUTS (outf, statbits (cbit));
1238 
    }
1239 
  else if (op == 0 && D == 1)
1240 
    {
1241 
      OUTS (outf, statbits (cbit));
1242 
      OUTS (outf, " = CC");
1243 
    }
1244 
  else if (op == 1 && D == 1)
1245 
    {
1246 
      OUTS (outf, statbits (cbit));
1247 
      OUTS (outf, " |= CC");
1248 
    }
1249 
  else if (op == 2 && D == 1)
1250 
    {
1251 
      OUTS (outf, statbits (cbit));
1252 
      OUTS (outf, " &= CC");
1253 
    }
1254 
  else if (op == 3 && D == 1)
1255 
    {
1256 
      OUTS (outf, statbits (cbit));
1257 
      OUTS (outf, " ^= CC");
1258 
    }
1259 
  else
1260 
    return 0;
1261 
 
1262 
  return 2;
1263 
}
1264 
 
1265 
static int
1266 
decode_BRCC_0 (TIword iw0, bfd_vma pc, disassemble_info *outf)
1267 
{
1268 
  /* BRCC
1269 
     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1270 
     | 0 | 0 | 0 | 1 |.T.|.B.|.offset................................|
1271 
     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+  */
1272 
  int B = ((iw0 >> BRCC_B_bits) & BRCC_B_mask);
1273 
  int T = ((iw0 >> BRCC_T_bits) & BRCC_T_mask);
1274 
  int offset = ((iw0 >> BRCC_offset_bits) & BRCC_offset_mask);
1275 
 
1276 
  if (T == 1 && B == 1)
1277 
    {
1278 
      OUTS (outf, "IF CC JUMP 0x");
1279 
      OUTS (outf, pcrel10 (offset));
1280 
      OUTS (outf, " (BP)");
1281 
    }
1282 
  else if (T == 0 && B == 1)
1283 
    {
1284 
      OUTS (outf, "IF !CC JUMP 0x");
1285 
      OUTS (outf, pcrel10 (offset));
1286 
      OUTS (outf, " (BP)");
1287 
    }
1288 
  else if (T == 1)
1289 
    {
1290 
      OUTS (outf, "IF CC JUMP 0x");
1291 
      OUTS (outf, pcrel10 (offset));
1292 
    }
1293 
  else if (T == 0)
1294 
    {
1295 
      OUTS (outf, "IF !CC JUMP 0x");
1296 
      OUTS (outf, pcrel10 (offset));
1297 
    }
1298 
  else
1299 
    return 0;
1300 
 
1301 
  return 2;
1302 
}
1303 
 
1304 
static int
1305 
decode_UJUMP_0 (TIword iw0, bfd_vma pc, disassemble_info *outf)
1306 
{
1307 
  /* UJUMP
1308 
     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1309 
     | 0 | 0 | 1 | 0 |.offset........................................|
1310 
     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+  */
1311 
  int offset = ((iw0 >> UJump_offset_bits) & UJump_offset_mask);
1312 
 
1313 
  OUTS (outf, "JUMP.S 0x");
1314 
  OUTS (outf, pcrel12 (offset));
1315 
  return 2;
1316 
}
1317 
 
1318 
static int
1319 
decode_REGMV_0 (TIword iw0, disassemble_info *outf)
1320 
{
1321 
  /* REGMV
1322 
     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1323 
     | 0 | 0 | 1 | 1 |.gd........|.gs........|.dst.......|.src.......|
1324 
     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+  */
1325 
  int gs  = ((iw0 >> RegMv_gs_bits) & RegMv_gs_mask);
1326 
  int gd  = ((iw0 >> RegMv_gd_bits) & RegMv_gd_mask);
1327 
  int src = ((iw0 >> RegMv_src_bits) & RegMv_src_mask);
1328 
  int dst = ((iw0 >> RegMv_dst_bits) & RegMv_dst_mask);
1329 
 
1330 
  if (!((IS_GENREG (gd, dst) && IS_GENREG (gs, src))
1331 
        || (IS_GENREG (gd, dst) && IS_DAGREG (gs, src))
1332 
        || (IS_DAGREG (gd, dst) && IS_GENREG (gs, src))
1333 
        || (IS_DAGREG (gd, dst) && IS_DAGREG (gs, src))
1334 
        || (IS_GENREG (gd, dst) && gs == 7 && src == 0)
1335 
        || (gd == 7 && dst == 0 && IS_GENREG (gs, src))
1336 
        || (IS_DREG (gd, dst) && IS_SYSREG (gs, src))
1337 
        || (IS_PREG (gd, dst) && IS_SYSREG (gs, src))
1338 
        || (IS_SYSREG (gd, dst) && IS_DREG (gs, src))
1339 
        || (IS_SYSREG (gd, dst) && IS_PREG (gs, src))
1340 
        || (IS_SYSREG (gd, dst) && gs == 7 && src == 0)))
1341 
    return 0;
1342 
 
1343 
  OUTS (outf, allregs (dst, gd));
1344 
  OUTS (outf, " = ");
1345 
  OUTS (outf, allregs (src, gs));
1346 
  return 2;
1347 
}
1348 
 
1349 
static int
1350 
decode_ALU2op_0 (TIword iw0, disassemble_info *outf)
1351 
{
1352 
  /* ALU2op
1353 
     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1354 
     | 0 | 1 | 0 | 0 | 0 | 0 |.opc...........|.src.......|.dst.......|
1355 
     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+  */
1356 
  int src = ((iw0 >> ALU2op_src_bits) & ALU2op_src_mask);
1357 
  int opc = ((iw0 >> ALU2op_opc_bits) & ALU2op_opc_mask);
1358 
  int dst = ((iw0 >> ALU2op_dst_bits) & ALU2op_dst_mask);
1359 
 
1360 
  if (opc == 0)
1361 
    {
1362 
      OUTS (outf, dregs (dst));
1363 
      OUTS (outf, " >>>= ");
1364 
      OUTS (outf, dregs (src));
1365 
    }
1366 
  else if (opc == 1)
1367 
    {
1368 
      OUTS (outf, dregs (dst));
1369 
      OUTS (outf, " >>= ");
1370 
      OUTS (outf, dregs (src));
1371 
    }
1372 
  else if (opc == 2)
1373 
    {
1374 
      OUTS (outf, dregs (dst));
1375 
      OUTS (outf, " <<= ");
1376 
      OUTS (outf, dregs (src));
1377 
    }
1378 
  else if (opc == 3)
1379 
    {
1380 
      OUTS (outf, dregs (dst));
1381 
      OUTS (outf, " *= ");
1382 
      OUTS (outf, dregs (src));
1383 
    }
1384 
  else if (opc == 4)
1385 
    {
1386 
      OUTS (outf, dregs (dst));
1387 
      OUTS (outf, " = (");
1388 
      OUTS (outf, dregs (dst));
1389 
      OUTS (outf, " + ");
1390 
      OUTS (outf, dregs (src));
1391 
      OUTS (outf, ") << 0x1");
1392 
    }
1393 
  else if (opc == 5)
1394 
    {
1395 
      OUTS (outf, dregs (dst));
1396 
      OUTS (outf, " = (");
1397 
      OUTS (outf, dregs (dst));
1398 
      OUTS (outf, " + ");
1399 
      OUTS (outf, dregs (src));
1400 
      OUTS (outf, ") << 0x2");
1401 
    }
1402 
  else if (opc == 8)
1403 
    {
1404 
      OUTS (outf, "DIVQ (");
1405 
      OUTS (outf, dregs (dst));
1406 
      OUTS (outf, ", ");
1407 
      OUTS (outf, dregs (src));
1408 
      OUTS (outf, ")");
1409 
    }
1410 
  else if (opc == 9)
1411 
    {
1412 
      OUTS (outf, "DIVS (");
1413 
      OUTS (outf, dregs (dst));
1414 
      OUTS (outf, ", ");
1415 
      OUTS (outf, dregs (src));
1416 
      OUTS (outf, ")");
1417 
    }
1418 
  else if (opc == 10)
1419 
    {
1420 
      OUTS (outf, dregs (dst));
1421 
      OUTS (outf, " = ");
1422 
      OUTS (outf, dregs_lo (src));
1423 
      OUTS (outf, " (X)");
1424 
    }
1425 
  else if (opc == 11)
1426 
    {
1427 
      OUTS (outf, dregs (dst));
1428 
      OUTS (outf, " = ");
1429 
      OUTS (outf, dregs_lo (src));
1430 
      OUTS (outf, " (Z)");
1431 
    }
1432 
  else if (opc == 12)
1433 
    {
1434 
      OUTS (outf, dregs (dst));
1435 
      OUTS (outf, " = ");
1436 
      OUTS (outf, dregs_byte (src));
1437 
      OUTS (outf, " (X)");
1438 
    }
1439 
  else if (opc == 13)
1440 
    {
1441 
      OUTS (outf, dregs (dst));
1442 
      OUTS (outf, " = ");
1443 
      OUTS (outf, dregs_byte (src));
1444 
      OUTS (outf, " (Z)");
1445 
    }
1446 
  else if (opc == 14)
1447 
    {
1448 
      OUTS (outf, dregs (dst));
1449 
      OUTS (outf, " = -");
1450 
      OUTS (outf, dregs (src));
1451 
    }
1452 
  else if (opc == 15)
1453 
    {
1454 
      OUTS (outf, dregs (dst));
1455 
      OUTS (outf, " =~ ");
1456 
      OUTS (outf, dregs (src));
1457 
    }
1458 
  else
1459 
    return 0;
1460 
 
1461 
  return 2;
1462 
}
1463 
 
1464 
static int
1465 
decode_PTR2op_0 (TIword iw0, disassemble_info *outf)
1466 
{
1467 
  /* PTR2op
1468 
     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1469 
     | 0 | 1 | 0 | 0 | 0 | 1 | 0 |.opc.......|.src.......|.dst.......|
1470 
     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+  */
1471 
  int src = ((iw0 >> PTR2op_src_bits) & PTR2op_dst_mask);
1472 
  int opc = ((iw0 >> PTR2op_opc_bits) & PTR2op_opc_mask);
1473 
  int dst = ((iw0 >> PTR2op_dst_bits) & PTR2op_dst_mask);
1474 
 
1475 
  if (opc == 0)
1476 
    {
1477 
      OUTS (outf, pregs (dst));
1478 
      OUTS (outf, " -= ");
1479 
      OUTS (outf, pregs (src));
1480 
    }
1481 
  else if (opc == 1)
1482 
    {
1483 
      OUTS (outf, pregs (dst));
1484 
      OUTS (outf, " = ");
1485 
      OUTS (outf, pregs (src));
1486 
      OUTS (outf, " << 0x2");
1487 
    }
1488 
  else if (opc == 3)
1489 
    {
1490 
      OUTS (outf, pregs (dst));
1491 
      OUTS (outf, " = ");
1492 
      OUTS (outf, pregs (src));
1493 
      OUTS (outf, " >> 0x2");
1494 
    }
1495 
  else if (opc == 4)
1496 
    {
1497 
      OUTS (outf, pregs (dst));
1498 
      OUTS (outf, " = ");
1499 
      OUTS (outf, pregs (src));
1500 
      OUTS (outf, " >> 0x1");
1501 
    }
1502 
  else if (opc == 5)
1503 
    {
1504 
      OUTS (outf, pregs (dst));
1505 
      OUTS (outf, " += ");
1506 
      OUTS (outf, pregs (src));
1507 
      OUTS (outf, " (BREV)");
1508 
    }
1509 
  else if (opc == 6)
1510 
    {
1511 
      OUTS (outf, pregs (dst));
1512 
      OUTS (outf, " = (");
1513 
      OUTS (outf, pregs (dst));
1514 
      OUTS (outf, " + ");
1515 
      OUTS (outf, pregs (src));
1516 
      OUTS (outf, ") << 0x1");
1517 
    }
1518 
  else if (opc == 7)
1519 
    {
1520 
      OUTS (outf, pregs (dst));
1521 
      OUTS (outf, " = (");
1522 
      OUTS (outf, pregs (dst));
1523 
      OUTS (outf, " + ");
1524 
      OUTS (outf, pregs (src));
1525 
      OUTS (outf, ") << 0x2");
1526 
    }
1527 
  else
1528 
    return 0;
1529 
 
1530 
  return 2;
1531 
}
1532 
 
1533 
static int
1534 
decode_LOGI2op_0 (TIword iw0, disassemble_info *outf)
1535 
{
1536 
  /* LOGI2op
1537 
     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1538 
     | 0 | 1 | 0 | 0 | 1 |.opc.......|.src...............|.dst.......|
1539 
     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+  */
1540 
  int src = ((iw0 >> LOGI2op_src_bits) & LOGI2op_src_mask);
1541 
  int opc = ((iw0 >> LOGI2op_opc_bits) & LOGI2op_opc_mask);
1542 
  int dst = ((iw0 >> LOGI2op_dst_bits) & LOGI2op_dst_mask);
1543 
 
1544 
  if (opc == 0)
1545 
    {
1546 
      OUTS (outf, "CC = !BITTST (");
1547 
      OUTS (outf, dregs (dst));
1548 
      OUTS (outf, ", ");
1549 
      OUTS (outf, uimm5 (src));
1550 
      OUTS (outf, ");\t\t/* bit");
1551 
      OUTS (outf, imm7d (src));
1552 
      OUTS (outf, " */");
1553 
      comment = 1;
1554 
    }
1555 
  else if (opc == 1)
1556 
    {
1557 
      OUTS (outf, "CC = BITTST (");
1558 
      OUTS (outf, dregs (dst));
1559 
      OUTS (outf, ", ");
1560 
      OUTS (outf, uimm5 (src));
1561 
      OUTS (outf, ");\t\t/* bit");
1562 
      OUTS (outf, imm7d (src));
1563 
      OUTS (outf, " */");
1564 
      comment = 1;
1565 
    }
1566 
  else if (opc == 2)
1567 
    {
1568 
      OUTS (outf, "BITSET (");
1569 
      OUTS (outf, dregs (dst));
1570 
      OUTS (outf, ", ");
1571 
      OUTS (outf, uimm5 (src));
1572 
      OUTS (outf, ");\t\t/* bit");
1573 
      OUTS (outf, imm7d (src));
1574 
      OUTS (outf, " */");
1575 
      comment = 1;
1576 
    }
1577 
  else if (opc == 3)
1578 
    {
1579 
      OUTS (outf, "BITTGL (");
1580 
      OUTS (outf, dregs (dst));
1581 
      OUTS (outf, ", ");
1582 
      OUTS (outf, uimm5 (src));
1583 
      OUTS (outf, ");\t\t/* bit");
1584 
      OUTS (outf, imm7d (src));
1585 
      OUTS (outf, " */");
1586 
      comment = 1;
1587 
    }
1588 
  else if (opc == 4)
1589 
    {
1590 
      OUTS (outf, "BITCLR (");
1591 
      OUTS (outf, dregs (dst));
1592 
      OUTS (outf, ", ");
1593 
      OUTS (outf, uimm5 (src));
1594 
      OUTS (outf, ");\t\t/* bit");
1595 
      OUTS (outf, imm7d (src));
1596 
      OUTS (outf, " */");
1597 
      comment = 1;
1598 
    }
1599 
  else if (opc == 5)
1600 
    {
1601 
      OUTS (outf, dregs (dst));
1602 
      OUTS (outf, " >>>= ");
1603 
      OUTS (outf, uimm5 (src));
1604 
    }
1605 
  else if (opc == 6)
1606 
    {
1607 
      OUTS (outf, dregs (dst));
1608 
      OUTS (outf, " >>= ");
1609 
      OUTS (outf, uimm5 (src));
1610 
    }
1611 
  else if (opc == 7)
1612 
    {
1613 
      OUTS (outf, dregs (dst));
1614 
      OUTS (outf, " <<= ");
1615 
      OUTS (outf, uimm5 (src));
1616 
    }
1617 
  else
1618 
    return 0;
1619 
 
1620 
  return 2;
1621 
}
1622 
 
1623 
static int
1624 
decode_COMP3op_0 (TIword iw0, disassemble_info *outf)
1625 
{
1626 
  /* COMP3op
1627 
     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1628 
     | 0 | 1 | 0 | 1 |.opc.......|.dst.......|.src1......|.src0......|
1629 
     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+  */
1630 
  int opc  = ((iw0 >> COMP3op_opc_bits) & COMP3op_opc_mask);
1631 
  int dst  = ((iw0 >> COMP3op_dst_bits) & COMP3op_dst_mask);
1632 
  int src0 = ((iw0 >> COMP3op_src0_bits) & COMP3op_src0_mask);
1633 
  int src1 = ((iw0 >> COMP3op_src1_bits) & COMP3op_src1_mask);
1634 
 
1635 
  if (opc == 5 && src1 == src0)
1636 
    {
1637 
      OUTS (outf, pregs (dst));
1638 
      OUTS (outf, " = ");
1639 
      OUTS (outf, pregs (src0));
1640 
      OUTS (outf, " << 0x1");
1641 
    }
1642 
  else if (opc == 1)
1643 
    {
1644 
      OUTS (outf, dregs (dst));
1645 
      OUTS (outf, " = ");
1646 
      OUTS (outf, dregs (src0));
1647 
      OUTS (outf, " - ");
1648 
      OUTS (outf, dregs (src1));
1649 
    }
1650 
  else if (opc == 2)
1651 
    {
1652 
      OUTS (outf, dregs (dst));
1653 
      OUTS (outf, " = ");
1654 
      OUTS (outf, dregs (src0));
1655 
      OUTS (outf, " & ");
1656 
      OUTS (outf, dregs (src1));
1657 
    }
1658 
  else if (opc == 3)
1659 
    {
1660 
      OUTS (outf, dregs (dst));
1661 
      OUTS (outf, " = ");
1662 
      OUTS (outf, dregs (src0));
1663 
      OUTS (outf, " | ");
1664 
      OUTS (outf, dregs (src1));
1665 
    }
1666 
  else if (opc == 4)
1667 
    {
1668 
      OUTS (outf, dregs (dst));
1669 
      OUTS (outf, " = ");
1670 
      OUTS (outf, dregs (src0));
1671 
      OUTS (outf, " ^ ");
1672 
      OUTS (outf, dregs (src1));
1673 
    }
1674 
  else if (opc == 5)
1675 
    {
1676 
      OUTS (outf, pregs (dst));
1677 
      OUTS (outf, " = ");
1678 
      OUTS (outf, pregs (src0));
1679 
      OUTS (outf, " + ");
1680 
      OUTS (outf, pregs (src1));
1681 
    }
1682 
  else if (opc == 6)
1683 
    {
1684 
      OUTS (outf, pregs (dst));
1685 
      OUTS (outf, " = ");
1686 
      OUTS (outf, pregs (src0));
1687 
      OUTS (outf, " + (");
1688 
      OUTS (outf, pregs (src1));
1689 
      OUTS (outf, " << 0x1)");
1690 
    }
1691 
  else if (opc == 7)
1692 
    {
1693 
      OUTS (outf, pregs (dst));
1694 
      OUTS (outf, " = ");
1695 
      OUTS (outf, pregs (src0));
1696 
      OUTS (outf, " + (");
1697 
      OUTS (outf, pregs (src1));
1698 
      OUTS (outf, " << 0x2)");
1699 
    }
1700 
  else if (opc == 0)
1701 
    {
1702 
      OUTS (outf, dregs (dst));
1703 
      OUTS (outf, " = ");
1704 
      OUTS (outf, dregs (src0));
1705 
      OUTS (outf, " + ");
1706 
      OUTS (outf, dregs (src1));
1707 
    }
1708 
  else
1709 
    return 0;
1710 
 
1711 
  return 2;
1712 
}
1713 
 
1714 
static int
1715 
decode_COMPI2opD_0 (TIword iw0, disassemble_info *outf)
1716 
{
1717 
  /* COMPI2opD
1718 
     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1719 
     | 0 | 1 | 1 | 0 | 0 |.op|..src......................|.dst.......|
1720 
     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+  */
1721 
  int op  = ((iw0 >> COMPI2opD_op_bits) & COMPI2opD_op_mask);
1722 
  int dst = ((iw0 >> COMPI2opD_dst_bits) & COMPI2opD_dst_mask);
1723 
  int src = ((iw0 >> COMPI2opD_src_bits) & COMPI2opD_src_mask);
1724 
 
1725 
  bu32 *pval = get_allreg (0, dst);
1726 
 
1727 
  /* Since we don't have 32-bit immediate loads, we allow the disassembler
1728 
     to combine them, so it prints out the right values.
1729 
     Here we keep track of the registers.  */
1730 
  if (op == 0)
1731 
    {
1732 
      *pval = imm7_val (src);
1733 
      if (src & 0x40)
1734 
        *pval |= 0xFFFFFF80;
1735 
      else
1736 
        *pval &= 0x7F;
1737 
    }
1738 
 
1739 
  if (op == 0)
1740 
    {
1741 
      OUTS (outf, dregs (dst));
1742 
      OUTS (outf, " = ");
1743 
      OUTS (outf, imm7 (src));
1744 
      OUTS (outf, " (X);\t\t/*\t\t");
1745 
      OUTS (outf, dregs (dst));
1746 
      OUTS (outf, "=");
1747 
      OUTS (outf, uimm32 (*pval));
1748 
      OUTS (outf, "(");
1749 
      OUTS (outf, imm32 (*pval));
1750 
      OUTS (outf, ") */");
1751 
      comment = 1;
1752 
    }
1753 
  else if (op == 1)
1754 
    {
1755 
      OUTS (outf, dregs (dst));
1756 
      OUTS (outf, " += ");
1757 
      OUTS (outf, imm7 (src));
1758 
      OUTS (outf, ";\t\t/* (");
1759 
      OUTS (outf, imm7d (src));
1760 
      OUTS (outf, ") */");
1761 
      comment = 1;
1762 
    }
1763 
  else
1764 
    return 0;
1765 
 
1766 
  return 2;
1767 
}
1768 
 
1769 
static int
1770 
decode_COMPI2opP_0 (TIword iw0, disassemble_info *outf)
1771 
{
1772 
  /* COMPI2opP
1773 
     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1774 
     | 0 | 1 | 1 | 0 | 1 |.op|.src.......................|.dst.......|
1775 
     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+  */
1776 
  int op  = ((iw0 >> COMPI2opP_op_bits) & COMPI2opP_op_mask);
1777 
  int src = ((iw0 >> COMPI2opP_src_bits) & COMPI2opP_src_mask);
1778 
  int dst = ((iw0 >> COMPI2opP_dst_bits) & COMPI2opP_dst_mask);
1779 
 
1780 
  bu32 *pval = get_allreg (1, dst);
1781 
 
1782 
  if (op == 0)
1783 
    {
1784 
      *pval = imm7_val (src);
1785 
      if (src & 0x40)
1786 
        *pval |= 0xFFFFFF80;
1787 
      else
1788 
        *pval &= 0x7F;
1789 
    }
1790 
 
1791 
  if (op == 0)
1792 
    {
1793 
      OUTS (outf, pregs (dst));
1794 
      OUTS (outf, " = ");
1795 
      OUTS (outf, imm7 (src));
1796 
      OUTS (outf, " (X);\t\t/*\t\t");
1797 
      OUTS (outf, pregs (dst));
1798 
      OUTS (outf, "=");
1799 
      OUTS (outf, uimm32 (*pval));
1800 
      OUTS (outf, "(");
1801 
      OUTS (outf, imm32 (*pval));
1802 
      OUTS (outf, ") */");
1803 
      comment = 1;
1804 
    }
1805 
  else if (op == 1)
1806 
    {
1807 
      OUTS (outf, pregs (dst));
1808 
      OUTS (outf, " += ");
1809 
      OUTS (outf, imm7 (src));
1810 
      OUTS (outf, ";\t\t/* (");
1811 
      OUTS (outf, imm7d (src));
1812 
      OUTS (outf, ") */");
1813 
      comment = 1;
1814 
    }
1815 
  else
1816 
    return 0;
1817 
 
1818 
  return 2;
1819 
}
1820 
 
1821 
static int
1822 
decode_LDSTpmod_0 (TIword iw0, disassemble_info *outf)
1823 
{
1824 
  /* LDSTpmod
1825 
     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1826 
     | 1 | 0 | 0 | 0 |.W.|.aop...|.reg.......|.idx.......|.ptr.......|
1827 
     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+  */
1828 
  int W   = ((iw0 >> LDSTpmod_W_bits) & LDSTpmod_W_mask);
1829 
  int aop = ((iw0 >> LDSTpmod_aop_bits) & LDSTpmod_aop_mask);
1830 
  int idx = ((iw0 >> LDSTpmod_idx_bits) & LDSTpmod_idx_mask);
1831 
  int ptr = ((iw0 >> LDSTpmod_ptr_bits) & LDSTpmod_ptr_mask);
1832 
  int reg = ((iw0 >> LDSTpmod_reg_bits) & LDSTpmod_reg_mask);
1833 
 
1834 
  if (aop == 1 && W == 0 && idx == ptr)
1835 
    {
1836 
      OUTS (outf, dregs_lo (reg));
1837 
      OUTS (outf, " = W[");
1838 
      OUTS (outf, pregs (ptr));
1839 
      OUTS (outf, "]");
1840 
    }
1841 
  else if (aop == 2 && W == 0 && idx == ptr)
1842 
    {
1843 
      OUTS (outf, dregs_hi (reg));
1844 
      OUTS (outf, " = W[");
1845 
      OUTS (outf, pregs (ptr));
1846 
      OUTS (outf, "]");
1847 
    }
1848 
  else if (aop == 1 && W == 1 && idx == ptr)
1849 
    {
1850 
      OUTS (outf, "W[");
1851 
      OUTS (outf, pregs (ptr));
1852 
      OUTS (outf, "] = ");
1853 
      OUTS (outf, dregs_lo (reg));
1854 
    }
1855 
  else if (aop == 2 && W == 1 && idx == ptr)
1856 
    {
1857 
      OUTS (outf, "W[");
1858 
      OUTS (outf, pregs (ptr));
1859 
      OUTS (outf, "] = ");
1860 
      OUTS (outf, dregs_hi (reg));
1861 
    }
1862 
  else if (aop == 0 && W == 0)
1863 
    {
1864 
      OUTS (outf, dregs (reg));
1865 
      OUTS (outf, " = [");
1866 
      OUTS (outf, pregs (ptr));
1867 
      OUTS (outf, " ++ ");
1868 
      OUTS (outf, pregs (idx));
1869 
      OUTS (outf, "]");
1870 
    }
1871 
  else if (aop == 1 && W == 0)
1872 
    {
1873 
      OUTS (outf, dregs_lo (reg));
1874 
      OUTS (outf, " = W[");
1875 
      OUTS (outf, pregs (ptr));
1876 
      OUTS (outf, " ++ ");
1877 
      OUTS (outf, pregs (idx));
1878 
      OUTS (outf, "]");
1879 
    }
1880 
  else if (aop == 2 && W == 0)
1881 
    {
1882 
      OUTS (outf, dregs_hi (reg));
1883 
      OUTS (outf, " = W[");
1884 
      OUTS (outf, pregs (ptr));
1885 
      OUTS (outf, " ++ ");
1886 
      OUTS (outf, pregs (idx));
1887 
      OUTS (outf, "]");
1888 
    }
1889 
  else if (aop == 3 && W == 0)
1890 
    {
1891 
      OUTS (outf, dregs (reg));
1892 
      OUTS (outf, " = W[");
1893 
      OUTS (outf, pregs (ptr));
1894 
      OUTS (outf, " ++ ");
1895 
      OUTS (outf, pregs (idx));
1896 
      OUTS (outf, "] (Z)");
1897 
    }
1898 
  else if (aop == 3 && W == 1)
1899 
    {
1900 
      OUTS (outf, dregs (reg));
1901 
      OUTS (outf, " = W[");
1902 
      OUTS (outf, pregs (ptr));
1903 
      OUTS (outf, " ++ ");
1904 
      OUTS (outf, pregs (idx));
1905 
      OUTS (outf, "] (X)");
1906 
    }
1907 
  else if (aop == 0 && W == 1)
1908 
    {
1909 
      OUTS (outf, "[");
1910 
      OUTS (outf, pregs (ptr));
1911 
      OUTS (outf, " ++ ");
1912 
      OUTS (outf, pregs (idx));
1913 
      OUTS (outf, "] = ");
1914 
      OUTS (outf, dregs (reg));
1915 
    }
1916 
  else if (aop == 1 && W == 1)
1917 
    {
1918 
      OUTS (outf, "W[");
1919 
      OUTS (outf, pregs (ptr));
1920 
      OUTS (outf, " ++ ");
1921 
      OUTS (outf, pregs (idx));
1922 
      OUTS (outf, "] = ");
1923 
      OUTS (outf, dregs_lo (reg));
1924 
    }
1925 
  else if (aop == 2 && W == 1)
1926 
    {
1927 
      OUTS (outf, "W[");
1928 
      OUTS (outf, pregs (ptr));
1929 
      OUTS (outf, " ++ ");
1930 
      OUTS (outf, pregs (idx));
1931 
      OUTS (outf, "] = ");
1932 
      OUTS (outf, dregs_hi (reg));
1933 
    }
1934 
  else
1935 
    return 0;
1936 
 
1937 
  return 2;
1938 
}
1939 
 
1940 
static int
1941 
decode_dagMODim_0 (TIword iw0, disassemble_info *outf)
1942 
{
1943 
  /* dagMODim
1944 
     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1945 
     | 1 | 0 | 0 | 1 | 1 | 1 | 1 | 0 |.br| 1 | 1 |.op|.m.....|.i.....|
1946 
     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+  */
1947 
  int i  = ((iw0 >> DagMODim_i_bits) & DagMODim_i_mask);
1948 
  int m  = ((iw0 >> DagMODim_m_bits) & DagMODim_m_mask);
1949 
  int br = ((iw0 >> DagMODim_br_bits) & DagMODim_br_mask);
1950 
  int op = ((iw0 >> DagMODim_op_bits) & DagMODim_op_mask);
1951 
 
1952 
  if (op == 0 && br == 1)
1953 
    {
1954 
      OUTS (outf, iregs (i));
1955 
      OUTS (outf, " += ");
1956 
      OUTS (outf, mregs (m));
1957 
      OUTS (outf, " (BREV)");
1958 
    }
1959 
  else if (op == 0)
1960 
    {
1961 
      OUTS (outf, iregs (i));
1962 
      OUTS (outf, " += ");
1963 
      OUTS (outf, mregs (m));
1964 
    }
1965 
  else if (op == 1)
1966 
    {
1967 
      OUTS (outf, iregs (i));
1968 
      OUTS (outf, " -= ");
1969 
      OUTS (outf, mregs (m));
1970 
    }
1971 
  else
1972 
    return 0;
1973 
 
1974 
  return 2;
1975 
}
1976 
 
1977 
static int
1978 
decode_dagMODik_0 (TIword iw0, disassemble_info *outf)
1979 
{
1980 
  /* dagMODik
1981 
     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1982 
     | 1 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | 1 | 0 |.op....|.i.....|
1983 
     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+  */
1984 
  int i  = ((iw0 >> DagMODik_i_bits) & DagMODik_i_mask);
1985 
  int op = ((iw0 >> DagMODik_op_bits) & DagMODik_op_mask);
1986 
 
1987 
  if (op == 0)
1988 
    {
1989 
      OUTS (outf, iregs (i));
1990 
      OUTS (outf, " += 0x2");
1991 
    }
1992 
  else if (op == 1)
1993 
    {
1994 
      OUTS (outf, iregs (i));
1995 
      OUTS (outf, " -= 0x2");
1996 
    }
1997 
  else if (op == 2)
1998 
    {
1999 
      OUTS (outf, iregs (i));
2000 
      OUTS (outf, " += 0x4");
2001 
    }
2002 
  else if (op == 3)
2003 
    {
2004 
      OUTS (outf, iregs (i));
2005 
      OUTS (outf, " -= 0x4");
2006 
    }
2007 
  else
2008 
    return 0;
2009 
 
2010 
 if (! parallel )
2011 
   {
2012 
     OUTS (outf, ";\t\t/* (  ");
2013 
     if (op == 0 || op == 1)
2014 
       OUTS (outf, "2");
2015 
     else if (op == 2 || op == 3)
2016 
        OUTS (outf, "4");
2017 
     OUTS (outf, ") */");
2018 
    comment = 1;
2019 
  }
2020 
 
2021 
  return 2;
2022 
}
2023 
 
2024 
static int
2025 
decode_dspLDST_0 (TIword iw0, disassemble_info *outf)
2026 
{
2027 
  /* dspLDST
2028 
     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
2029 
     | 1 | 0 | 0 | 1 | 1 | 1 |.W.|.aop...|.m.....|.i.....|.reg.......|
2030 
     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+  */
2031 
  int i   = ((iw0 >> DspLDST_i_bits) & DspLDST_i_mask);
2032 
  int m   = ((iw0 >> DspLDST_m_bits) & DspLDST_m_mask);
2033 
  int W   = ((iw0 >> DspLDST_W_bits) & DspLDST_W_mask);
2034 
  int aop = ((iw0 >> DspLDST_aop_bits) & DspLDST_aop_mask);
2035 
  int reg = ((iw0 >> DspLDST_reg_bits) & DspLDST_reg_mask);
2036 
 
2037 
  if (aop == 0 && W == 0 && m == 0)
2038 
    {
2039 
      OUTS (outf, dregs (reg));
2040 
      OUTS (outf, " = [");
2041 
      OUTS (outf, iregs (i));
2042 
      OUTS (outf, "++]");
2043 
    }
2044 
  else if (aop == 0 && W == 0 && m == 1)
2045 
    {
2046 
      OUTS (outf, dregs_lo (reg));
2047 
      OUTS (outf, " = W[");
2048 
      OUTS (outf, iregs (i));
2049 
      OUTS (outf, "++]");
2050 
    }
2051 
  else if (aop == 0 && W == 0 && m == 2)
2052 
    {
2053 
      OUTS (outf, dregs_hi (reg));
2054 
      OUTS (outf, " = W[");
2055 
      OUTS (outf, iregs (i));
2056 
      OUTS (outf, "++]");
2057 
    }
2058 
  else if (aop == 1 && W == 0 && m == 0)
2059 
    {
2060 
      OUTS (outf, dregs (reg));
2061 
      OUTS (outf, " = [");
2062 
      OUTS (outf, iregs (i));
2063 
      OUTS (outf, "--]");
2064 
    }
2065 
  else if (aop == 1 && W == 0 && m == 1)
2066 
    {
2067 
      OUTS (outf, dregs_lo (reg));
2068 
      OUTS (outf, " = W[");
2069 
      OUTS (outf, iregs (i));
2070 
      OUTS (outf, "--]");
2071 
    }
2072 
  else if (aop == 1 && W == 0 && m == 2)
2073 
    {
2074 
      OUTS (outf, dregs_hi (reg));
2075 
      OUTS (outf, " = W[");
2076 
      OUTS (outf, iregs (i));
2077 
      OUTS (outf, "--]");
2078 
    }
2079 
  else if (aop == 2 && W == 0 && m == 0)
2080 
    {
2081 
      OUTS (outf, dregs (reg));
2082 
      OUTS (outf, " = [");
2083 
      OUTS (outf, iregs (i));
2084 
      OUTS (outf, "]");
2085 
    }
2086 
  else if (aop == 2 && W == 0 && m == 1)
2087 
    {
2088 
      OUTS (outf, dregs_lo (reg));
2089 
      OUTS (outf, " = W[");
2090 
      OUTS (outf, iregs (i));
2091 
      OUTS (outf, "]");
2092 
    }
2093 
  else if (aop == 2 && W == 0 && m == 2)
2094 
    {
2095 
      OUTS (outf, dregs_hi (reg));
2096 
      OUTS (outf, " = W[");
2097 
      OUTS (outf, iregs (i));
2098 
      OUTS (outf, "]");
2099 
    }
2100 
  else if (aop == 0 && W == 1 && m == 0)
2101 
    {
2102 
      OUTS (outf, "[");
2103 
      OUTS (outf, iregs (i));
2104 
      OUTS (outf, "++] = ");
2105 
      OUTS (outf, dregs (reg));
2106 
    }
2107 
  else if (aop == 0 && W == 1 && m == 1)
2108 
    {
2109 
      OUTS (outf, "W[");
2110 
      OUTS (outf, iregs (i));
2111 
      OUTS (outf, "++] = ");
2112 
      OUTS (outf, dregs_lo (reg));
2113 
    }
2114 
  else if (aop == 0 && W == 1 && m == 2)
2115 
    {
2116 
      OUTS (outf, "W[");
2117 
      OUTS (outf, iregs (i));
2118 
      OUTS (outf, "++] = ");
2119 
      OUTS (outf, dregs_hi (reg));
2120 
    }
2121 
  else if (aop == 1 && W == 1 && m == 0)
2122 
    {
2123 
      OUTS (outf, "[");
2124 
      OUTS (outf, iregs (i));
2125 
      OUTS (outf, "--] = ");
2126 
      OUTS (outf, dregs (reg));
2127 
    }
2128 
  else if (aop == 1 && W == 1 && m == 1)
2129 
    {
2130 
      OUTS (outf, "W[");
2131 
      OUTS (outf, iregs (i));
2132 
      OUTS (outf, "--] = ");
2133 
      OUTS (outf, dregs_lo (reg));
2134 
    }
2135 
  else if (aop == 1 && W == 1 && m == 2)
2136 
    {
2137 
      OUTS (outf, "W[");
2138 
      OUTS (outf, iregs (i));
2139 
      OUTS (outf, "--] = ");
2140 
      OUTS (outf, dregs_hi (reg));
2141 
    }
2142 
  else if (aop == 2 && W == 1 && m == 0)
2143 
    {
2144 
      OUTS (outf, "[");
2145 
      OUTS (outf, iregs (i));
2146 
      OUTS (outf, "] = ");
2147 
      OUTS (outf, dregs (reg));
2148 
    }
2149 
  else if (aop == 2 && W == 1 && m == 1)
2150 
    {
2151 
      OUTS (outf, "W[");
2152 
      OUTS (outf, iregs (i));
2153 
      OUTS (outf, "] = ");
2154 
      OUTS (outf, dregs_lo (reg));
2155 
    }
2156 
  else if (aop == 2 && W == 1 && m == 2)
2157 
    {
2158 
      OUTS (outf, "W[");
2159 
      OUTS (outf, iregs (i));
2160 
      OUTS (outf, "] = ");
2161 
      OUTS (outf, dregs_hi (reg));
2162 
    }
2163 
  else if (aop == 3 && W == 0)
2164 
    {
2165 
      OUTS (outf, dregs (reg));
2166 
      OUTS (outf, " = [");
2167 
      OUTS (outf, iregs (i));
2168 
      OUTS (outf, " ++ ");
2169 
      OUTS (outf, mregs (m));
2170 
      OUTS (outf, "]");
2171 
    }
2172 
  else if (aop == 3 && W == 1)
2173 
    {
2174 
      OUTS (outf, "[");
2175 
      OUTS (outf, iregs (i));
2176 
      OUTS (outf, " ++ ");
2177 
      OUTS (outf, mregs (m));
2178 
      OUTS (outf, "] = ");
2179 
      OUTS (outf, dregs (reg));
2180 
    }
2181 
  else
2182 
    return 0;
2183 
 
2184 
  return 2;
2185 
}
2186 
 
2187 
static int
2188 
decode_LDST_0 (TIword iw0, disassemble_info *outf)
2189 
{
2190 
  /* LDST
2191 
     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
2192 
     | 1 | 0 | 0 | 1 |.sz....|.W.|.aop...|.Z.|.ptr.......|.reg.......|
2193 
     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+  */
2194 
  int Z   = ((iw0 >> LDST_Z_bits) & LDST_Z_mask);
2195 
  int W   = ((iw0 >> LDST_W_bits) & LDST_W_mask);
2196 
  int sz  = ((iw0 >> LDST_sz_bits) & LDST_sz_mask);
2197 
  int aop = ((iw0 >> LDST_aop_bits) & LDST_aop_mask);
2198 
  int reg = ((iw0 >> LDST_reg_bits) & LDST_reg_mask);
2199 
  int ptr = ((iw0 >> LDST_ptr_bits) & LDST_ptr_mask);
2200 
 
2201 
  if (aop == 0 && sz == 0 && Z == 0 && W == 0)
2202 
    {
2203 
      OUTS (outf, dregs (reg));
2204 
      OUTS (outf, " = [");
2205 
      OUTS (outf, pregs (ptr));
2206 
      OUTS (outf, "++]");
2207 
    }
2208 
  else if (aop == 0 && sz == 0 && Z == 1 && W == 0)
2209 
    {
2210 
      OUTS (outf, pregs (reg));
2211 
      OUTS (outf, " = [");
2212 
      OUTS (outf, pregs (ptr));
2213 
      OUTS (outf, "++]");
2214 
    }
2215 
  else if (aop == 0 && sz == 1 && Z == 0 && W == 0)
2216 
    {
2217 
      OUTS (outf, dregs (reg));
2218 
      OUTS (outf, " = W[");
2219 
      OUTS (outf, pregs (ptr));
2220 
      OUTS (outf, "++] (Z)");
2221 
    }
2222 
  else if (aop == 0 && sz == 1 && Z == 1 && W == 0)
2223 
    {
2224 
      OUTS (outf, dregs (reg));
2225 
      OUTS (outf, " = W[");
2226 
      OUTS (outf, pregs (ptr));
2227 
      OUTS (outf, "++] (X)");
2228 
    }
2229 
  else if (aop == 0 && sz == 2 && Z == 0 && W == 0)
2230 
    {
2231 
      OUTS (outf, dregs (reg));
2232 
      OUTS (outf, " = B[");
2233 
      OUTS (outf, pregs (ptr));
2234 
      OUTS (outf, "++] (Z)");
2235 
    }
2236 
  else if (aop == 0 && sz == 2 && Z == 1 && W == 0)
2237 
    {
2238 
      OUTS (outf, dregs (reg));
2239 
      OUTS (outf, " = B[");
2240 
      OUTS (outf, pregs (ptr));
2241 
      OUTS (outf, "++] (X)");
2242 
    }
2243 
  else if (aop == 1 && sz == 0 && Z == 0 && W == 0)
2244 
    {
2245 
      OUTS (outf, dregs (reg));
2246 
      OUTS (outf, " = [");
2247 
      OUTS (outf, pregs (ptr));
2248 
      OUTS (outf, "--]");
2249 
    }
2250 
  else if (aop == 1 && sz == 0 && Z == 1 && W == 0)
2251 
    {
2252 
      OUTS (outf, pregs (reg));
2253 
      OUTS (outf, " = [");
2254 
      OUTS (outf, pregs (ptr));
2255 
      OUTS (outf, "--]");
2256 
    }
2257 
  else if (aop == 1 && sz == 1 && Z == 0 && W == 0)
2258 
    {
2259 
      OUTS (outf, dregs (reg));
2260 
      OUTS (outf, " = W[");
2261 
      OUTS (outf, pregs (ptr));
2262 
      OUTS (outf, "--] (Z)");
2263 
    }
2264 
  else if (aop == 1 && sz == 1 && Z == 1 && W == 0)
2265 
    {
2266 
      OUTS (outf, dregs (reg));
2267 
      OUTS (outf, " = W[");
2268 
      OUTS (outf, pregs (ptr));
2269 
      OUTS (outf, "--] (X)");
2270 
    }
2271 
  else if (aop == 1 && sz == 2 && Z == 0 && W == 0)
2272 
    {
2273 
      OUTS (outf, dregs (reg));
2274 
      OUTS (outf, " = B[");
2275 
      OUTS (outf, pregs (ptr));
2276 
      OUTS (outf, "--] (Z)");
2277 
    }
2278 
  else if (aop == 1 && sz == 2 && Z == 1 && W == 0)
2279 
    {
2280 
      OUTS (outf, dregs (reg));
2281 
      OUTS (outf, " = B[");
2282 
      OUTS (outf, pregs (ptr));
2283 
      OUTS (outf, "--] (X)");
2284 
    }
2285 
  else if (aop == 2 && sz == 0 && Z == 0 && W == 0)
2286 
    {
2287 
      OUTS (outf, dregs (reg));
2288 
      OUTS (outf, " = [");
2289 
      OUTS (outf, pregs (ptr));
2290 
      OUTS (outf, "]");
2291 
    }
2292 
  else if (aop == 2 && sz == 0 && Z == 1 && W == 0)
2293 
    {
2294 
      OUTS (outf, pregs (reg));
2295 
      OUTS (outf, " = [");
2296 
      OUTS (outf, pregs (ptr));
2297 
      OUTS (outf, "]");
2298 
    }
2299 
  else if (aop == 2 && sz == 1 && Z == 0 && W == 0)
2300 
    {
2301 
      OUTS (outf, dregs (reg));
2302 
      OUTS (outf, " = W[");
2303 
      OUTS (outf, pregs (ptr));
2304 
      OUTS (outf, "] (Z)");
2305 
    }
2306 
  else if (aop == 2 && sz == 1 && Z == 1 && W == 0)
2307 
    {
2308 
      OUTS (outf, dregs (reg));
2309 
      OUTS (outf, " = W[");
2310 
      OUTS (outf, pregs (ptr));
2311 
      OUTS (outf, "] (X)");
2312 
    }
2313 
  else if (aop == 2 && sz == 2 && Z == 0 && W == 0)
2314 
    {
2315 
      OUTS (outf, dregs (reg));
2316 
      OUTS (outf, " = B[");
2317 
      OUTS (outf, pregs (ptr));
2318 
      OUTS (outf, "] (Z)");
2319 
    }
2320 
  else if (aop == 2 && sz == 2 && Z == 1 && W == 0)
2321 
    {
2322 
      OUTS (outf, dregs (reg));
2323 
      OUTS (outf, " = B[");
2324 
      OUTS (outf, pregs (ptr));
2325 
      OUTS (outf, "] (X)");
2326 
    }
2327 
  else if (aop == 0 && sz == 0 && Z == 0 && W == 1)
2328 
    {
2329 
      OUTS (outf, "[");
2330 
      OUTS (outf, pregs (ptr));
2331 
      OUTS (outf, "++] = ");
2332 
      OUTS (outf, dregs (reg));
2333 
    }
2334 
  else if (aop == 0 && sz == 0 && Z == 1 && W == 1)
2335 
    {
2336 
      OUTS (outf, "[");
2337 
      OUTS (outf, pregs (ptr));
2338 
      OUTS (outf, "++] = ");
2339 
      OUTS (outf, pregs (reg));
2340 
    }
2341 
  else if (aop == 0 && sz == 1 && Z == 0 && W == 1)
2342 
    {
2343 
      OUTS (outf, "W[");
2344 
      OUTS (outf, pregs (ptr));
2345 
      OUTS (outf, "++] = ");
2346 
      OUTS (outf, dregs (reg));
2347 
    }
2348 
  else if (aop == 0 && sz == 2 && Z == 0 && W == 1)
2349 
    {
2350 
      OUTS (outf, "B[");
2351 
      OUTS (outf, pregs (ptr));
2352 
      OUTS (outf, "++] = ");
2353 
      OUTS (outf, dregs (reg));
2354 
    }
2355 
  else if (aop == 1 && sz == 0 && Z == 0 && W == 1)
2356 
    {
2357 
      OUTS (outf, "[");
2358 
      OUTS (outf, pregs (ptr));
2359 
      OUTS (outf, "--] = ");
2360 
      OUTS (outf, dregs (reg));
2361 
    }
2362 
  else if (aop == 1 && sz == 0 && Z == 1 && W == 1)
2363 
    {
2364 
      OUTS (outf, "[");
2365 
      OUTS (outf, pregs (ptr));
2366 
      OUTS (outf, "--] = ");
2367 
      OUTS (outf, pregs (reg));
2368 
    }
2369 
  else if (aop == 1 && sz == 1 && Z == 0 && W == 1)
2370 
    {
2371 
      OUTS (outf, "W[");
2372 
      OUTS (outf, pregs (ptr));
2373 
      OUTS (outf, "--] = ");
2374 
      OUTS (outf, dregs (reg));
2375 
    }
2376 
  else if (aop == 1 && sz == 2 && Z == 0 && W == 1)
2377 
    {
2378 
      OUTS (outf, "B[");
2379 
      OUTS (outf, pregs (ptr));
2380 
      OUTS (outf, "--] = ");
2381 
      OUTS (outf, dregs (reg));
2382 
    }
2383 
  else if (aop == 2 && sz == 0 && Z == 0 && W == 1)
2384 
    {
2385 
      OUTS (outf, "[");
2386 
      OUTS (outf, pregs (ptr));
2387 
      OUTS (outf, "] = ");
2388 
      OUTS (outf, dregs (reg));
2389 
    }
2390 
  else if (aop == 2 && sz == 0 && Z == 1 && W == 1)
2391 
    {
2392 
      OUTS (outf, "[");
2393 
      OUTS (outf, pregs (ptr));
2394 
      OUTS (outf, "] = ");
2395 
      OUTS (outf, pregs (reg));
2396 
    }
2397 
  else if (aop == 2 && sz == 1 && Z == 0 && W == 1)
2398 
    {
2399 
      OUTS (outf, "W[");
2400 
      OUTS (outf, pregs (ptr));
2401 
      OUTS (outf, "] = ");
2402 
      OUTS (outf, dregs (reg));
2403 
    }
2404 
  else if (aop == 2 && sz == 2 && Z == 0 && W == 1)
2405 
    {
2406 
      OUTS (outf, "B[");
2407 
      OUTS (outf, pregs (ptr));
2408 
      OUTS (outf, "] = ");
2409 
      OUTS (outf, dregs (reg));
2410 
    }
2411 
  else
2412 
    return 0;
2413 
 
2414 
  return 2;
2415 
}
2416 
 
2417 
static int
2418 
decode_LDSTiiFP_0 (TIword iw0, disassemble_info *outf)
2419 
{
2420 
  /* LDSTiiFP
2421 
     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
2422 
     | 1 | 0 | 1 | 1 | 1 | 0 |.W.|.offset............|.reg...........|
2423 
     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+  */
2424 
  int reg = ((iw0 >> LDSTiiFP_reg_bits) & LDSTiiFP_reg_mask);
2425 
  int offset = ((iw0 >> LDSTiiFP_offset_bits) & LDSTiiFP_offset_mask);
2426 
  int W = ((iw0 >> LDSTiiFP_W_bits) & LDSTiiFP_W_mask);
2427 
 
2428 
  if (W == 0)
2429 
    {
2430 
      OUTS (outf, dpregs (reg));
2431 
      OUTS (outf, " = [FP ");
2432 
      OUTS (outf, negimm5s4 (offset));
2433 
      OUTS (outf, "]");
2434 
    }
2435 
  else if (W == 1)
2436 
    {
2437 
      OUTS (outf, "[FP ");
2438 
      OUTS (outf, negimm5s4 (offset));
2439 
      OUTS (outf, "] = ");
2440 
      OUTS (outf, dpregs (reg));
2441 
    }
2442 
  else
2443 
    return 0;
2444 
 
2445 
  return 2;
2446 
}
2447 
 
2448 
static int
2449 
decode_LDSTii_0 (TIword iw0, disassemble_info *outf)
2450 
{
2451 
  /* LDSTii
2452 
     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
2453 
     | 1 | 0 | 1 |.W.|.op....|.offset........|.ptr.......|.reg.......|
2454 
     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+  */
2455 
  int reg = ((iw0 >> LDSTii_reg_bit) & LDSTii_reg_mask);
2456 
  int ptr = ((iw0 >> LDSTii_ptr_bit) & LDSTii_ptr_mask);
2457 
  int offset = ((iw0 >> LDSTii_offset_bit) & LDSTii_offset_mask);
2458 
  int op = ((iw0 >> LDSTii_op_bit) & LDSTii_op_mask);
2459 
  int W = ((iw0 >> LDSTii_W_bit) & LDSTii_W_mask);
2460 
 
2461 
  if (W == 0 && op == 0)
2462 
    {
2463 
      OUTS (outf, dregs (reg));
2464 
      OUTS (outf, " = [");
2465 
      OUTS (outf, pregs (ptr));
2466 
      OUTS (outf, " + ");
2467 
      OUTS (outf, uimm4s4 (offset));
2468 
      OUTS (outf, "]");
2469 
    }
2470 
  else if (W == 0 && op == 1)
2471 
    {
2472 
      OUTS (outf, dregs (reg));
2473 
      OUTS (outf, " = W[");
2474 
      OUTS (outf, pregs (ptr));
2475 
      OUTS (outf, " + ");
2476 
      OUTS (outf, uimm4s2 (offset));
2477 
      OUTS (outf, "] (Z)");
2478 
    }
2479 
  else if (W == 0 && op == 2)
2480 
    {
2481 
      OUTS (outf, dregs (reg));
2482 
      OUTS (outf, " = W[");
2483 
      OUTS (outf, pregs (ptr));
2484 
      OUTS (outf, " + ");
2485 
      OUTS (outf, uimm4s2 (offset));
2486 
      OUTS (outf, "] (X)");
2487 
    }
2488 
  else if (W == 0 && op == 3)
2489 
    {
2490 
      OUTS (outf, pregs (reg));
2491 
      OUTS (outf, " = [");
2492 
      OUTS (outf, pregs (ptr));
2493 
      OUTS (outf, " + ");
2494 
      OUTS (outf, uimm4s4 (offset));
2495 
      OUTS (outf, "]");
2496 
    }
2497 
  else if (W == 1 && op == 0)
2498 
    {
2499 
      OUTS (outf, "[");
2500 
      OUTS (outf, pregs (ptr));
2501 
      OUTS (outf, " + ");
2502 
      OUTS (outf, uimm4s4 (offset));
2503 
      OUTS (outf, "] = ");
2504 
      OUTS (outf, dregs (reg));
2505 
    }
2506 
  else if (W == 1 && op == 1)
2507 
    {
2508 
      OUTS (outf, "W[");
2509 
      OUTS (outf, pregs (ptr));
2510 
      OUTS (outf, " + ");
2511 
      OUTS (outf, uimm4s2 (offset));
2512 
      OUTS (outf, "] = ");
2513 
      OUTS (outf, dregs (reg));
2514 
    }
2515 
  else if (W == 1 && op == 3)
2516 
    {
2517 
      OUTS (outf, "[");
2518 
      OUTS (outf, pregs (ptr));
2519 
      OUTS (outf, " + ");
2520 
      OUTS (outf, uimm4s4 (offset));
2521 
      OUTS (outf, "] = ");
2522 
      OUTS (outf, pregs (reg));
2523 
    }
2524 
  else
2525 
    return 0;
2526 
 
2527 
  return 2;
2528 
}
2529 
 
2530 
static int
2531 
decode_LoopSetup_0 (TIword iw0, TIword iw1, bfd_vma pc, disassemble_info *outf)
2532 
{
2533 
  /* LoopSetup
2534 
     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
2535 
     | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 1 |.rop...|.c.|.soffset.......|
2536 
     |.reg...........| - | - |.eoffset...............................|
2537 
     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+  */
2538 
  int c   = ((iw0 >> (LoopSetup_c_bits - 16)) & LoopSetup_c_mask);
2539 
  int reg = ((iw1 >> LoopSetup_reg_bits) & LoopSetup_reg_mask);
2540 
  int rop = ((iw0 >> (LoopSetup_rop_bits - 16)) & LoopSetup_rop_mask);
2541 
  int soffset = ((iw0 >> (LoopSetup_soffset_bits - 16)) & LoopSetup_soffset_mask);
2542 
  int eoffset = ((iw1 >> LoopSetup_eoffset_bits) & LoopSetup_eoffset_mask);
2543 
 
2544 
  if (rop == 0)
2545 
    {
2546 
      OUTS (outf, "LSETUP");
2547 
      OUTS (outf, "(0x");
2548 
      OUTS (outf, pcrel4 (soffset));
2549 
      OUTS (outf, ", 0x");
2550 
      OUTS (outf, lppcrel10 (eoffset));
2551 
      OUTS (outf, ") ");
2552 
      OUTS (outf, counters (c));
2553 
    }
2554 
  else if (rop == 1)
2555 
    {
2556 
      OUTS (outf, "LSETUP");
2557 
      OUTS (outf, "(0x");
2558 
      OUTS (outf, pcrel4 (soffset));
2559 
      OUTS (outf, ", 0x");
2560 
      OUTS (outf, lppcrel10 (eoffset));
2561 
      OUTS (outf, ") ");
2562 
      OUTS (outf, counters (c));
2563 
      OUTS (outf, " = ");
2564 
      OUTS (outf, pregs (reg));
2565 
    }
2566 
  else if (rop == 3)
2567 
    {
2568 
      OUTS (outf, "LSETUP");
2569 
      OUTS (outf, "(0x");
2570 
      OUTS (outf, pcrel4 (soffset));
2571 
      OUTS (outf, ", 0x");
2572 
      OUTS (outf, lppcrel10 (eoffset));
2573 
      OUTS (outf, ") ");
2574 
      OUTS (outf, counters (c));
2575 
      OUTS (outf, " = ");
2576 
      OUTS (outf, pregs (reg));
2577 
      OUTS (outf, " >> 0x1");
2578 
    }
2579 
  else
2580 
    return 0;
2581 
 
2582 
  return 4;
2583 
}
2584 
 
2585 
static int
2586 
decode_LDIMMhalf_0 (TIword iw0, TIword iw1, disassemble_info *outf)
2587 
{
2588 
  /* LDIMMhalf
2589 
     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
2590 
     | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 1 |.Z.|.H.|.S.|.grp...|.reg.......|
2591 
     |.hword.........................................................|
2592 
     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+  */
2593 
  int H = ((iw0 >> (LDIMMhalf_H_bits - 16)) & LDIMMhalf_H_mask);
2594 
  int Z = ((iw0 >> (LDIMMhalf_Z_bits - 16)) & LDIMMhalf_Z_mask);
2595 
  int S = ((iw0 >> (LDIMMhalf_S_bits - 16)) & LDIMMhalf_S_mask);
2596 
  int reg = ((iw0 >> (LDIMMhalf_reg_bits - 16)) & LDIMMhalf_reg_mask);
2597 
  int grp = ((iw0 >> (LDIMMhalf_grp_bits - 16)) & LDIMMhalf_grp_mask);
2598 
  int hword = ((iw1 >> LDIMMhalf_hword_bits) & LDIMMhalf_hword_mask);
2599 
 
2600 
  bu32 *pval = get_allreg (grp, reg);
2601 
 
2602 
  /* Since we don't have 32-bit immediate loads, we allow the disassembler
2603 
     to combine them, so it prints out the right values.
2604 
     Here we keep track of the registers.  */
2605 
  if (H == 0 && S == 1 && Z == 0)
2606 
    {
2607 
      /* regs = imm16 (x) */
2608 
      *pval = imm16_val (hword);
2609 
      if (hword & 0x8000)
2610 
        *pval |= 0xFFFF0000;
2611 
      else
2612 
        *pval &= 0xFFFF;
2613 
    }
2614 
  else if (H == 0 && S == 0 && Z == 1)
2615 
    {
2616 
      /* regs = luimm16 (Z) */
2617 
      *pval = luimm16_val (hword);
2618 
      *pval &= 0xFFFF;
2619 
    }
2620 
  else if (H == 0 && S == 0 && Z == 0)
2621 
    {
2622 
      /* regs_lo = luimm16 */
2623 
      *pval &= 0xFFFF0000;
2624 
      *pval |= luimm16_val (hword);
2625 
    }
2626 
  else if (H == 1 && S == 0 && Z == 0)
2627 
    {
2628 
      /* regs_hi = huimm16 */
2629 
      *pval &= 0xFFFF;
2630 
      *pval |= luimm16_val (hword) << 16;
2631 
    }
2632 
 
2633 
  /* Here we do the disassembly */
2634 
  if (grp == 0 && H == 0 && S == 0 && Z == 0)
2635 
    {
2636 
      OUTS (outf, dregs_lo (reg));
2637 
      OUTS (outf, " = ");
2638 
      OUTS (outf, uimm16 (hword));
2639 
    }
2640 
  else if (grp == 0 && H == 1 && S == 0 && Z == 0)
2641 
    {
2642 
      OUTS (outf, dregs_hi (reg));
2643 
      OUTS (outf, " = ");
2644 
      OUTS (outf, uimm16 (hword));
2645 
    }
2646 
  else if (grp == 0 && H == 0 && S == 1 && Z == 0)
2647 
    {
2648 
      OUTS (outf, dregs (reg));
2649 
      OUTS (outf, " = ");
2650 
      OUTS (outf, imm16 (hword));
2651 
      OUTS (outf, " (X)");
2652 
    }
2653 
  else if (H == 0 && S == 1 && Z == 0)
2654 
   {
2655 
      OUTS (outf, regs (reg, grp));
2656 
      OUTS (outf, " = ");
2657 
      OUTS (outf, imm16 (hword));
2658 
      OUTS (outf, " (X)");
2659 
    }
2660 
  else if (H == 0 && S == 0 && Z == 1)
2661 
    {
2662 
      OUTS (outf, regs (reg, grp));
2663 
      OUTS (outf, " = ");
2664 
      OUTS (outf, uimm16 (hword));
2665 
      OUTS (outf, " (Z)");
2666 
    }
2667 
  else if (H == 0 && S == 0 && Z == 0)
2668 
    {
2669 
      OUTS (outf, regs_lo (reg, grp));
2670 
      OUTS (outf, " = ");
2671 
      OUTS (outf, uimm16 (hword));
2672 
    }
2673 
  else if (H == 1 && S == 0 && Z == 0)
2674 
    {
2675 
      OUTS (outf, regs_hi (reg, grp));
2676 
      OUTS (outf, " = ");
2677 
      OUTS (outf, uimm16 (hword));
2678 
    }
2679 
  else
2680 
    return 0;
2681 
 
2682 
  /* And we print out the 32-bit value if it is a pointer.  */
2683 
  if (S == 0 && Z == 0)
2684 
    {
2685 
      OUTS (outf, ";\t\t/* (");
2686 
      OUTS (outf, imm16d (hword));
2687 
      OUTS (outf, ")\t");
2688 
 
2689 
      /* If it is an MMR, don't print the symbol.  */
2690 
      if (*pval < 0xFFC00000 && grp == 1)
2691 
        {
2692 
          OUTS (outf, regs (reg, grp));
2693 
          OUTS (outf, "=0x");
2694 
          OUTS (outf, huimm32e (*pval));
2695 
        }
2696 
      else
2697 
        {
2698 
          OUTS (outf, regs (reg, grp));
2699 
          OUTS (outf, "=0x");
2700 
          OUTS (outf, huimm32e (*pval));
2701 
          OUTS (outf, "(");
2702 
          OUTS (outf, imm32 (*pval));
2703 
          OUTS (outf, ")");
2704 
        }
2705 
 
2706 
      OUTS (outf, " */");
2707 
      comment = 1;
2708 
    }
2709 
  if (S == 1 || Z == 1)
2710 
    {
2711 
       OUTS (outf, ";\t\t/*\t\t");
2712 
       OUTS (outf, regs (reg, grp));
2713 
       OUTS (outf, "=0x");
2714 
       OUTS (outf, huimm32e (*pval));
2715 
       OUTS (outf, "(");
2716 
       OUTS (outf, imm32 (*pval));
2717 
       OUTS (outf, ") */");
2718 
       comment = 1;
2719 
    }
2720 
  return 4;
2721 
}
2722 
 
2723 
static int
2724 
decode_CALLa_0 (TIword iw0, TIword iw1, bfd_vma pc, disassemble_info *outf)
2725 
{
2726 
  /* CALLa
2727 
     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
2728 
     | 1 | 1 | 1 | 0 | 0 | 0 | 1 |.S.|.msw...........................|
2729 
     |.lsw...........................................................|
2730 
     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+  */
2731 
  int S   = ((iw0 >> (CALLa_S_bits - 16)) & CALLa_S_mask);
2732 
  int lsw = ((iw1 >> 0) & 0xffff);
2733 
  int msw = ((iw0 >> 0) & 0xff);
2734 
 
2735 
  if (S == 1)
2736 
    OUTS (outf, "CALL 0x");
2737 
  else if (S == 0)
2738 
    OUTS (outf, "JUMP.L 0x");
2739 
  else
2740 
    return 0;
2741 
 
2742 
  OUTS (outf, pcrel24 (((msw) << 16) | (lsw)));
2743 
  return 4;
2744 
}
2745 
 
2746 
static int
2747 
decode_LDSTidxI_0 (TIword iw0, TIword iw1, disassemble_info *outf)
2748 
{
2749 
  /* LDSTidxI
2750 
     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
2751 
     | 1 | 1 | 1 | 0 | 0 | 1 |.W.|.Z.|.sz....|.ptr.......|.reg.......|
2752 
     |.offset........................................................|
2753 
     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+  */
2754 
  int Z = ((iw0 >> (LDSTidxI_Z_bits - 16)) & LDSTidxI_Z_mask);
2755 
  int W = ((iw0 >> (LDSTidxI_W_bits - 16)) & LDSTidxI_W_mask);
2756 
  int sz = ((iw0 >> (LDSTidxI_sz_bits - 16)) & LDSTidxI_sz_mask);
2757 
  int reg = ((iw0 >> (LDSTidxI_reg_bits - 16)) & LDSTidxI_reg_mask);
2758 
  int ptr = ((iw0 >> (LDSTidxI_ptr_bits - 16)) & LDSTidxI_ptr_mask);
2759 
  int offset = ((iw1 >> LDSTidxI_offset_bits) & LDSTidxI_offset_mask);
2760 
 
2761 
  if (W == 0 && sz == 0 && Z == 0)
2762 
    {
2763 
      OUTS (outf, dregs (reg));
2764 
      OUTS (outf, " = [");
2765 
      OUTS (outf, pregs (ptr));
2766 
      OUTS (outf, " + ");
2767 
      OUTS (outf, imm16s4 (offset));
2768 
      OUTS (outf, "]");
2769 
    }
2770 
  else if (W == 0 && sz == 0 && Z == 1)
2771 
    {
2772 
      OUTS (outf, pregs (reg));
2773 
      OUTS (outf, " = [");
2774 
      OUTS (outf, pregs (ptr));
2775 
      OUTS (outf, " + ");
2776 
      OUTS (outf, imm16s4 (offset));
2777 
      OUTS (outf, "]");
2778 
    }
2779 
  else if (W == 0 && sz == 1 && Z == 0)
2780 
    {
2781 
      OUTS (outf, dregs (reg));
2782 
      OUTS (outf, " = W[");
2783 
      OUTS (outf, pregs (ptr));
2784 
      OUTS (outf, " + ");
2785 
      OUTS (outf, imm16s2 (offset));
2786 
      OUTS (outf, "] (Z)");
2787 
    }
2788 
  else if (W == 0 && sz == 1 && Z == 1)
2789 
    {
2790 
      OUTS (outf, dregs (reg));
2791 
      OUTS (outf, " = W[");
2792 
      OUTS (outf, pregs (ptr));
2793 
      OUTS (outf, " + ");
2794 
      OUTS (outf, imm16s2 (offset));
2795 
      OUTS (outf, "] (X)");
2796 
    }
2797 
  else if (W == 0 && sz == 2 && Z == 0)
2798 
    {
2799 
      OUTS (outf, dregs (reg));
2800 
      OUTS (outf, " = B[");
2801 
      OUTS (outf, pregs (ptr));
2802 
      OUTS (outf, " + ");
2803 
      OUTS (outf, imm16 (offset));
2804 
      OUTS (outf, "] (Z)");
2805 
    }
2806 
  else if (W == 0 && sz == 2 && Z == 1)
2807 
    {
2808 
      OUTS (outf, dregs (reg));
2809 
      OUTS (outf, " = B[");
2810 
      OUTS (outf, pregs (ptr));
2811 
      OUTS (outf, " + ");
2812 
      OUTS (outf, imm16 (offset));
2813 
      OUTS (outf, "] (X)");
2814 
    }
2815 
  else if (W == 1 && sz == 0 && Z == 0)
2816 
    {
2817 
      OUTS (outf, "[");
2818 
      OUTS (outf, pregs (ptr));
2819 
      OUTS (outf, " + ");
2820 
      OUTS (outf, imm16s4 (offset));
2821 
      OUTS (outf, "] = ");
2822 
      OUTS (outf, dregs (reg));
2823 
    }
2824 
  else if (W == 1 && sz == 0 && Z == 1)
2825 
    {
2826 
      OUTS (outf, "[");
2827 
      OUTS (outf, pregs (ptr));
2828 
      OUTS (outf, " + ");
2829 
      OUTS (outf, imm16s4 (offset));
2830 
      OUTS (outf, "] = ");
2831 
      OUTS (outf, pregs (reg));
2832 
    }
2833 
  else if (W == 1 && sz == 1 && Z == 0)
2834 
    {
2835 
      OUTS (outf, "W[");
2836 
      OUTS (outf, pregs (ptr));
2837 
      OUTS (outf, " + ");
2838 
      OUTS (outf, imm16s2 (offset));
2839 
      OUTS (outf, "] = ");
2840 
      OUTS (outf, dregs (reg));
2841 
    }
2842 
  else if (W == 1 && sz == 2 && Z == 0)
2843 
    {
2844 
      OUTS (outf, "B[");
2845 
      OUTS (outf, pregs (ptr));
2846 
      OUTS (outf, " + ");
2847 
      OUTS (outf, imm16 (offset));
2848 
      OUTS (outf, "] = ");
2849 
      OUTS (outf, dregs (reg));
2850 
    }
2851 
  else
2852 
    return 0;
2853 
 
2854 
  return 4;
2855 
}
2856 
 
2857 
static int
2858 
decode_linkage_0 (TIword iw0, TIword iw1, disassemble_info *outf)
2859 
{
2860 
  /* linkage
2861 
     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
2862 
     | 1 | 1 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |.R.|
2863 
     |.framesize.....................................................|
2864 
     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+  */
2865 
  int R = ((iw0 >> (Linkage_R_bits - 16)) & Linkage_R_mask);
2866 
  int framesize = ((iw1 >> Linkage_framesize_bits) & Linkage_framesize_mask);
2867 
 
2868 
  if (R == 0)
2869 
    {
2870 
      OUTS (outf, "LINK ");
2871 
      OUTS (outf, uimm16s4 (framesize));
2872 
      OUTS (outf, ";\t\t/* (");
2873 
      OUTS (outf, uimm16s4d (framesize));
2874 
      OUTS (outf, ") */");
2875 
      comment = 1;
2876 
    }
2877 
  else if (R == 1)
2878 
    OUTS (outf, "UNLINK");
2879 
  else
2880 
    return 0;
2881 
 
2882 
  return 4;
2883 
}
2884 
 
2885 
static int
2886 
decode_dsp32mac_0 (TIword iw0, TIword iw1, disassemble_info *outf)
2887 
{
2888 
  /* dsp32mac
2889 
     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
2890 
     | 1 | 1 | 0 | 0 |.M.| 0 | 0 |.mmod..........|.MM|.P.|.w1|.op1...|
2891 
     |.h01|.h11|.w0|.op0...|.h00|.h10|.dst.......|.src0......|.src1..|
2892 
     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+  */
2893 
  int op1  = ((iw0 >> (DSP32Mac_op1_bits - 16)) & DSP32Mac_op1_mask);
2894 
  int w1   = ((iw0 >> (DSP32Mac_w1_bits - 16)) & DSP32Mac_w1_mask);
2895 
  int P    = ((iw0 >> (DSP32Mac_p_bits - 16)) & DSP32Mac_p_mask);
2896 
  int MM   = ((iw0 >> (DSP32Mac_MM_bits - 16)) & DSP32Mac_MM_mask);
2897 
  int mmod = ((iw0 >> (DSP32Mac_mmod_bits - 16)) & DSP32Mac_mmod_mask);
2898 
  int w0   = ((iw1 >> DSP32Mac_w0_bits) & DSP32Mac_w0_mask);
2899 
  int src0 = ((iw1 >> DSP32Mac_src0_bits) & DSP32Mac_src0_mask);
2900 
  int src1 = ((iw1 >> DSP32Mac_src1_bits) & DSP32Mac_src1_mask);
2901 
  int dst  = ((iw1 >> DSP32Mac_dst_bits) & DSP32Mac_dst_mask);
2902 
  int h10  = ((iw1 >> DSP32Mac_h10_bits) & DSP32Mac_h10_mask);
2903 
  int h00  = ((iw1 >> DSP32Mac_h00_bits) & DSP32Mac_h00_mask);
2904 
  int op0  = ((iw1 >> DSP32Mac_op0_bits) & DSP32Mac_op0_mask);
2905 
  int h11  = ((iw1 >> DSP32Mac_h11_bits) & DSP32Mac_h11_mask);
2906 
  int h01  = ((iw1 >> DSP32Mac_h01_bits) & DSP32Mac_h01_mask);
2907 
 
2908 
  if (w0 == 0 && w1 == 0 && op1 == 3 && op0 == 3)
2909 
    return 0;
2910 
 
2911 
  if (op1 == 3 && MM)
2912 
    return 0;
2913 
 
2914 
  if ((w1 || w0) && mmod == M_W32)
2915 
    return 0;
2916 
 
2917 
  if (((1 << mmod) & (P ? 0x131b : 0x1b5f)) == 0)
2918 
    return 0;
2919 
 
2920 
  if (w1 == 1 || op1 != 3)
2921 
    {
2922 
      if (w1)
2923 
        OUTS (outf, P ? dregs (dst + 1) : dregs_hi (dst));
2924 
 
2925 
      if (op1 == 3)
2926 
        OUTS (outf, " = A1");
2927 
      else
2928 
        {
2929 
          if (w1)
2930 
            OUTS (outf, " = (");
2931 
          decode_macfunc (1, op1, h01, h11, src0, src1, outf);
2932 
          if (w1)
2933 
            OUTS (outf, ")");
2934 
        }
2935 
 
2936 
      if (w0 == 1 || op0 != 3)
2937 
        {
2938 
          if (MM)
2939 
            OUTS (outf, " (M)");
2940 
          MM = 0;
2941 
          OUTS (outf, ", ");
2942 
        }
2943 
    }
2944 
 
2945 
  if (w0 == 1 || op0 != 3)
2946 
    {
2947 
      if (w0)
2948 
        OUTS (outf, P ? dregs (dst) : dregs_lo (dst));
2949 
 
2950 
      if (op0 == 3)
2951 
        OUTS (outf, " = A0");
2952 
      else
2953 
        {
2954 
          if (w0)
2955 
            OUTS (outf, " = (");
2956 
          decode_macfunc (0, op0, h00, h10, src0, src1, outf);
2957 
          if (w0)
2958 
            OUTS (outf, ")");
2959 
        }
2960 
    }
2961 
 
2962 
  decode_optmode (mmod, MM, outf);
2963 
 
2964 
  return 4;
2965 
}
2966 
 
2967 
static int
2968 
decode_dsp32mult_0 (TIword iw0, TIword iw1, disassemble_info *outf)
2969 
{
2970 
  /* dsp32mult
2971 
     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
2972 
     | 1 | 1 | 0 | 0 |.M.| 0 | 1 |.mmod..........|.MM|.P.|.w1|.op1...|
2973 
     |.h01|.h11|.w0|.op0...|.h00|.h10|.dst.......|.src0......|.src1..|
2974 
     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+  */
2975 
  int w1   = ((iw0 >> (DSP32Mac_w1_bits - 16)) & DSP32Mac_w1_mask);
2976 
  int P    = ((iw0 >> (DSP32Mac_p_bits - 16)) & DSP32Mac_p_mask);
2977 
  int MM   = ((iw0 >> (DSP32Mac_MM_bits - 16)) & DSP32Mac_MM_mask);
2978 
  int mmod = ((iw0 >> (DSP32Mac_mmod_bits - 16)) & DSP32Mac_mmod_mask);
2979 
  int w0   = ((iw1 >> DSP32Mac_w0_bits) & DSP32Mac_w0_mask);
2980 
  int src0 = ((iw1 >> DSP32Mac_src0_bits) & DSP32Mac_src0_mask);
2981 
  int src1 = ((iw1 >> DSP32Mac_src1_bits) & DSP32Mac_src1_mask);
2982 
  int dst  = ((iw1 >> DSP32Mac_dst_bits) & DSP32Mac_dst_mask);
2983 
  int h10  = ((iw1 >> DSP32Mac_h10_bits) & DSP32Mac_h10_mask);
2984 
  int h00  = ((iw1 >> DSP32Mac_h00_bits) & DSP32Mac_h00_mask);
2985 
  int h11  = ((iw1 >> DSP32Mac_h11_bits) & DSP32Mac_h11_mask);
2986 
  int h01  = ((iw1 >> DSP32Mac_h01_bits) & DSP32Mac_h01_mask);
2987 
 
2988 
  if (w1 == 0 && w0 == 0)
2989 
    return 0;
2990 
 
2991 
  if (((1 << mmod) & (P ? 0x313 : 0x1b57)) == 0)
2992 
    return 0;
2993 
 
2994 
  if (w1)
2995 
    {
2996 
      OUTS (outf, P ? dregs (dst | 1) : dregs_hi (dst));
2997 
      OUTS (outf, " = ");
2998 
      decode_multfunc (h01, h11, src0, src1, outf);
2999 
 
3000 
      if (w0)
3001 
        {
3002 
          if (MM)
3003 
            OUTS (outf, " (M)");
3004 
          MM = 0;
3005 
          OUTS (outf, ", ");
3006 
        }
3007 
    }
3008 
 
3009 
  if (w0)
3010 
    {
3011 
      OUTS (outf, dregs (dst));
3012 
      OUTS (outf, " = ");
3013 
      decode_multfunc (h00, h10, src0, src1, outf);
3014 
    }
3015 
 
3016 
  decode_optmode (mmod, MM, outf);
3017 
  return 4;
3018 
}
3019 
 
3020 
static int
3021 
decode_dsp32alu_0 (TIword iw0, TIword iw1, disassemble_info *outf)
3022 
{
3023 
  /* dsp32alu
3024 
     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
3025 
     | 1 | 1 | 0 | 0 |.M.| 1 | 0 | - | - | - |.HL|.aopcde............|
3026 
     |.aop...|.s.|.x.|.dst0......|.dst1......|.src0......|.src1......|
3027 
     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+  */
3028 
  int s    = ((iw1 >> DSP32Alu_s_bits) & DSP32Alu_s_mask);
3029 
  int x    = ((iw1 >> DSP32Alu_x_bits) & DSP32Alu_x_mask);
3030 
  int aop  = ((iw1 >> DSP32Alu_aop_bits) & DSP32Alu_aop_mask);
3031 
  int src0 = ((iw1 >> DSP32Alu_src0_bits) & DSP32Alu_src0_mask);
3032 
  int src1 = ((iw1 >> DSP32Alu_src1_bits) & DSP32Alu_src1_mask);
3033 
  int dst0 = ((iw1 >> DSP32Alu_dst0_bits) & DSP32Alu_dst0_mask);
3034 
  int dst1 = ((iw1 >> DSP32Alu_dst1_bits) & DSP32Alu_dst1_mask);
3035 
  int HL   = ((iw0 >> (DSP32Alu_HL_bits - 16)) & DSP32Alu_HL_mask);
3036 
  int aopcde = ((iw0 >> (DSP32Alu_aopcde_bits - 16)) & DSP32Alu_aopcde_mask);
3037 
 
3038 
  if (aop == 0 && aopcde == 9 && HL == 0 && s == 0)
3039 
    {
3040 
      OUTS (outf, "A0.L = ");
3041 
      OUTS (outf, dregs_lo (src0));
3042 
    }
3043 
  else if (aop == 2 && aopcde == 9 && HL == 1 && s == 0)
3044 
    {
3045 
      OUTS (outf, "A1.H = ");
3046 
      OUTS (outf, dregs_hi (src0));
3047 
    }
3048 
  else if (aop == 2 && aopcde == 9 && HL == 0 && s == 0)
3049 
    {
3050 
      OUTS (outf, "A1.L = ");
3051 
      OUTS (outf, dregs_lo (src0));
3052 
    }
3053 
  else if (aop == 0 && aopcde == 9 && HL == 1 && s == 0)
3054 
    {
3055 
      OUTS (outf, "A0.H = ");
3056 
      OUTS (outf, dregs_hi (src0));
3057 
    }
3058 
  else if (x == 1 && HL == 1 && aop == 3 && aopcde == 5)
3059 
    {
3060 
      OUTS (outf, dregs_hi (dst0));
3061 
      OUTS (outf, " = ");
3062 
      OUTS (outf, dregs (src0));
3063 
      OUTS (outf, " - ");
3064 
      OUTS (outf, dregs (src1));
3065 
      OUTS (outf, " (RND20)");
3066 
    }
3067 
  else if (x == 1 && HL == 1 && aop == 2 && aopcde == 5)
3068 
    {
3069 
      OUTS (outf, dregs_hi (dst0));
3070 
      OUTS (outf, " = ");
3071 
      OUTS (outf, dregs (src0));
3072 
      OUTS (outf, " + ");
3073 
      OUTS (outf, dregs (src1));
3074 
      OUTS (outf, " (RND20)");
3075 
    }
3076 
  else if (x == 0 && HL == 0 && aop == 1 && aopcde == 5)
3077 
    {
3078 
      OUTS (outf, dregs_lo (dst0));
3079 
      OUTS (outf, " = ");
3080 
      OUTS (outf, dregs (src0));
3081 
      OUTS (outf, " - ");
3082 
      OUTS (outf, dregs (src1));
3083 
      OUTS (outf, " (RND12)");
3084 
    }
3085 
  else if (x == 0 && HL == 0 && aop == 0 && aopcde == 5)
3086 
    {
3087 
      OUTS (outf, dregs_lo (dst0));
3088 
      OUTS (outf, " = ");
3089 
      OUTS (outf, dregs (src0));
3090 
      OUTS (outf, " + ");
3091 
      OUTS (outf, dregs (src1));
3092 
      OUTS (outf, " (RND12)");
3093 
    }
3094 
  else if (x == 1 && HL == 0 && aop == 3 && aopcde == 5)
3095 
    {
3096 
      OUTS (outf, dregs_lo (dst0));
3097 
      OUTS (outf, " = ");
3098 
      OUTS (outf, dregs (src0));
3099 
      OUTS (outf, " - ");
3100 
      OUTS (outf, dregs (src1));
3101 
      OUTS (outf, " (RND20)");
3102 
    }
3103 
  else if (x == 0 && HL == 1 && aop == 0 && aopcde == 5)
3104 
    {
3105 
      OUTS (outf, dregs_hi (dst0));
3106 
      OUTS (outf, " = ");
3107 
      OUTS (outf, dregs (src0));
3108 
      OUTS (outf, " + ");
3109 
      OUTS (outf, dregs (src1));
3110 
      OUTS (outf, " (RND12)");
3111 
    }
3112 
  else if (x == 1 && HL == 0 && aop == 2 && aopcde == 5)
3113 
    {
3114 
      OUTS (outf, dregs_lo (dst0));
3115 
      OUTS (outf, " = ");
3116 
      OUTS (outf, dregs (src0));
3117 
      OUTS (outf, " + ");
3118 
      OUTS (outf, dregs (src1));
3119 
      OUTS (outf, " (RND20)");
3120 
    }
3121 
  else if (x == 0 && HL == 1 && aop == 1 && aopcde == 5)
3122 
    {
3123 
      OUTS (outf, dregs_hi (dst0));
3124 
      OUTS (outf, " = ");
3125 
      OUTS (outf, dregs (src0));
3126 
      OUTS (outf, " - ");
3127 
      OUTS (outf, dregs (src1));
3128 
      OUTS (outf, " (RND12)");
3129 
    }
3130 
  else if (HL == 1 && aop == 0 && aopcde == 2)
3131 
    {
3132 
      OUTS (outf, dregs_hi (dst0));
3133 
      OUTS (outf, " = ");
3134 
      OUTS (outf, dregs_lo (src0));
3135 
      OUTS (outf, " + ");
3136 
      OUTS (outf, dregs_lo (src1));
3137 
      amod1 (s, x, outf);
3138 
    }
3139 
  else if (HL == 1 && aop == 1 && aopcde == 2)
3140 
    {
3141 
      OUTS (outf, dregs_hi (dst0));
3142 
      OUTS (outf, " = ");
3143 
      OUTS (outf, dregs_lo (src0));
3144 
      OUTS (outf, " + ");
3145 
      OUTS (outf, dregs_hi (src1));
3146 
      amod1 (s, x, outf);
3147 
    }
3148 
  else if (HL == 1 && aop == 2 && aopcde == 2)
3149 
    {
3150 
      OUTS (outf, dregs_hi (dst0));
3151 
      OUTS (outf, " = ");
3152 
      OUTS (outf, dregs_hi (src0));
3153 
      OUTS (outf, " + ");
3154 
      OUTS (outf, dregs_lo (src1));
3155 
      amod1 (s, x, outf);
3156 
    }
3157 
  else if (HL == 1 && aop == 3 && aopcde == 2)
3158 
    {
3159 
      OUTS (outf, dregs_hi (dst0));
3160 
      OUTS (outf, " = ");
3161 
      OUTS (outf, dregs_hi (src0));
3162 
      OUTS (outf, " + ");
3163 
      OUTS (outf, dregs_hi (src1));
3164 
      amod1 (s, x, outf);
3165 
    }
3166 
  else if (HL == 0 && aop == 0 && aopcde == 3)
3167 
    {
3168 
      OUTS (outf, dregs_lo (dst0));
3169 
      OUTS (outf, " = ");
3170 
      OUTS (outf, dregs_lo (src0));
3171 
      OUTS (outf, " - ");
3172 
      OUTS (outf, dregs_lo (src1));
3173 
      amod1 (s, x, outf);
3174 
    }
3175 
  else if (HL == 0 && aop == 1 && aopcde == 3)
3176 
    {
3177 
      OUTS (outf, dregs_lo (dst0));
3178 
      OUTS (outf, " = ");
3179 
      OUTS (outf, dregs_lo (src0));
3180 
      OUTS (outf, " - ");
3181 
      OUTS (outf, dregs_hi (src1));
3182 
      amod1 (s, x, outf);
3183 
    }
3184 
  else if (HL == 0 && aop == 3 && aopcde == 2)
3185 
    {
3186 
      OUTS (outf, dregs_lo (dst0));
3187 
      OUTS (outf, " = ");
3188 
      OUTS (outf, dregs_hi (src0));
3189 
      OUTS (outf, " + ");
3190 
      OUTS (outf, dregs_hi (src1));
3191 
      amod1 (s, x, outf);
3192 
    }
3193 
  else if (HL == 1 && aop == 0 && aopcde == 3)
3194 
    {
3195 
      OUTS (outf, dregs_hi (dst0));
3196 
      OUTS (outf, " = ");
3197 
      OUTS (outf, dregs_lo (src0));
3198 
      OUTS (outf, " - ");
3199 
      OUTS (outf, dregs_lo (src1));
3200 
      amod1 (s, x, outf);
3201 
    }
3202 
  else if (HL == 1 && aop == 1 && aopcde == 3)
3203 
    {
3204 
      OUTS (outf, dregs_hi (dst0));
3205 
      OUTS (outf, " = ");
3206 
      OUTS (outf, dregs_lo (src0));
3207 
      OUTS (outf, " - ");
3208 
      OUTS (outf, dregs_hi (src1));
3209 
      amod1 (s, x, outf);
3210 
    }
3211 
  else if (HL == 1 && aop == 2 && aopcde == 3)
3212 
    {
3213 
      OUTS (outf, dregs_hi (dst0));
3214 
      OUTS (outf, " = ");
3215 
      OUTS (outf, dregs_hi (src0));
3216 
      OUTS (outf, " - ");
3217 
      OUTS (outf, dregs_lo (src1));
3218 
      amod1 (s, x, outf);
3219 
    }
3220 
  else if (HL == 1 && aop == 3 && aopcde == 3)
3221 
    {
3222 
      OUTS (outf, dregs_hi (dst0));
3223 
      OUTS (outf, " = ");
3224 
      OUTS (outf, dregs_hi (src0));
3225 
      OUTS (outf, " - ");
3226 
      OUTS (outf, dregs_hi (src1));
3227 
      amod1 (s, x, outf);
3228 
    }
3229 
  else if (HL == 0 && aop == 2 && aopcde == 2)
3230 
    {
3231 
      OUTS (outf, dregs_lo (dst0));
3232 
      OUTS (outf, " = ");
3233 
      OUTS (outf, dregs_hi (src0));
3234 
      OUTS (outf, " + ");
3235 
      OUTS (outf, dregs_lo (src1));
3236 
      amod1 (s, x, outf);
3237 
    }
3238 
  else if (HL == 0 && aop == 1 && aopcde == 2)
3239 
    {
3240 
      OUTS (outf, dregs_lo (dst0));
3241 
      OUTS (outf, " = ");
3242 
      OUTS (outf, dregs_lo (src0));
3243 
      OUTS (outf, " + ");
3244 
      OUTS (outf, dregs_hi (src1));
3245 
      amod1 (s, x, outf);
3246 
    }
3247 
  else if (HL == 0 && aop == 2 && aopcde == 3)
3248 
    {
3249 
      OUTS (outf, dregs_lo (dst0));
3250 
      OUTS (outf, " = ");
3251 
      OUTS (outf, dregs_hi (src0));
3252 
      OUTS (outf, " - ");
3253 
      OUTS (outf, dregs_lo (src1));
3254 
      amod1 (s, x, outf);
3255 
    }
3256 
  else if (HL == 0 && aop == 3 && aopcde == 3)
3257 
    {
3258 
      OUTS (outf, dregs_lo (dst0));
3259 
      OUTS (outf, " = ");
3260 
      OUTS (outf, dregs_hi (src0));
3261 
      OUTS (outf, " - ");
3262 
      OUTS (outf, dregs_hi (src1));
3263 
      amod1 (s, x, outf);
3264 
    }
3265 
  else if (HL == 0 && aop == 0 && aopcde == 2)
3266 
    {
3267 
      OUTS (outf, dregs_lo (dst0));
3268 
      OUTS (outf, " = ");
3269 
      OUTS (outf, dregs_lo (src0));
3270 
      OUTS (outf, " + ");
3271 
      OUTS (outf, dregs_lo (src1));
3272 
      amod1 (s, x, outf);
3273 
    }
3274 
  else if (aop == 0 && aopcde == 9 && s == 1)
3275 
    {
3276 
      OUTS (outf, "A0 = ");
3277 
      OUTS (outf, dregs (src0));
3278 
    }
3279 
  else if (aop == 3 && aopcde == 11 && s == 0)
3280 
    OUTS (outf, "A0 -= A1");
3281 
 
3282 
  else if (aop == 3 && aopcde == 11 && s == 1)
3283 
    OUTS (outf, "A0 -= A1 (W32)");
3284 
 
3285 
  else if (aop == 3 && aopcde == 22 && HL == 1)
3286 
    {
3287 
      OUTS (outf, dregs (dst0));
3288 
      OUTS (outf, " = BYTEOP2M (");
3289 
      OUTS (outf, dregs (src0 + 1));
3290 
      OUTS (outf, ":");
3291 
      OUTS (outf, imm5 (src0));
3292 
      OUTS (outf, ", ");
3293 
      OUTS (outf, dregs (src1 + 1));
3294 
      OUTS (outf, ":");
3295 
      OUTS (outf, imm5 (src1));
3296 
      OUTS (outf, ") (TH");
3297 
      if (s == 1)
3298 
        OUTS (outf, ", R)");
3299 
      else
3300 
        OUTS (outf, ")");
3301 
    }
3302 
  else if (aop == 3 && aopcde == 22 && HL == 0)
3303 
    {
3304 
      OUTS (outf, dregs (dst0));
3305 
      OUTS (outf, " = BYTEOP2M (");
3306 
      OUTS (outf, dregs (src0 + 1));
3307 
      OUTS (outf, ":");
3308 
      OUTS (outf, imm5 (src0));
3309 
      OUTS (outf, ", ");
3310 
      OUTS (outf, dregs (src1 + 1));
3311 
      OUTS (outf, ":");
3312 
      OUTS (outf, imm5 (src1));
3313 
      OUTS (outf, ") (TL");
3314 
      if (s == 1)
3315 
        OUTS (outf, ", R)");
3316 
      else
3317 
        OUTS (outf, ")");
3318 
    }
3319 
  else if (aop == 2 && aopcde == 22 && HL == 1)
3320 
    {
3321 
      OUTS (outf, dregs (dst0));
3322 
      OUTS (outf, " = BYTEOP2M (");
3323 
      OUTS (outf, dregs (src0 + 1));
3324 
      OUTS (outf, ":");
3325 
      OUTS (outf, imm5 (src0));
3326 
      OUTS (outf, ", ");
3327 
      OUTS (outf, dregs (src1 + 1));
3328 
      OUTS (outf, ":");
3329 
      OUTS (outf, imm5 (src1));
3330 
      OUTS (outf, ") (RNDH");
3331 
      if (s == 1)
3332 
        OUTS (outf, ", R)");
3333 
      else
3334 
        OUTS (outf, ")");
3335 
    }
3336 
  else if (aop == 2 && aopcde == 22 && HL == 0)
3337 
    {
3338 
      OUTS (outf, dregs (dst0));
3339 
      OUTS (outf, " = BYTEOP2M (");
3340 
      OUTS (outf, dregs (src0 + 1));
3341 
      OUTS (outf, ":");
3342 
      OUTS (outf, imm5 (src0));
3343 
      OUTS (outf, ", ");
3344 
      OUTS (outf, dregs (src1 + 1));
3345 
      OUTS (outf, ":");
3346 
      OUTS (outf, imm5 (src1));
3347 
      OUTS (outf, ") (RNDL");
3348 
      if (s == 1)
3349 
        OUTS (outf, ", R)");
3350 
      else
3351 
        OUTS (outf, ")");
3352 
    }
3353 
  else if (aop == 1 && aopcde == 22 && HL == 1)
3354 
    {
3355 
      OUTS (outf, dregs (dst0));
3356 
      OUTS (outf, " = BYTEOP2P (");
3357 
      OUTS (outf, dregs (src0 + 1));
3358 
      OUTS (outf, ":");
3359 
      OUTS (outf, imm5d (src0));
3360 
      OUTS (outf, ", ");
3361 
      OUTS (outf, dregs (src1 + 1));
3362 
      OUTS (outf, ":");
3363 
      OUTS (outf, imm5d (src1));
3364 
      OUTS (outf, ") (TH");
3365 
      if (s == 1)
3366 
        OUTS (outf, ", R)");
3367 
      else
3368 
        OUTS (outf, ")");
3369 
    }
3370 
  else if (aop == 1 && aopcde == 22 && HL == 0)
3371 
    {
3372 
      OUTS (outf, dregs (dst0));
3373 
      OUTS (outf, " = BYTEOP2P (");
3374 
      OUTS (outf, dregs (src0 + 1));
3375 
      OUTS (outf, ":");
3376 
      OUTS (outf, imm5d (src0));
3377 
      OUTS (outf, ", ");
3378 
      OUTS (outf, dregs (src1 + 1));
3379 
      OUTS (outf, ":");
3380 
      OUTS (outf, imm5d (src1));
3381 
      OUTS (outf, ") (TL");
3382 
      if (s == 1)
3383 
        OUTS (outf, ", R)");
3384 
      else
3385 
        OUTS (outf, ")");
3386 
    }
3387 
  else if (aop == 0 && aopcde == 22 && HL == 1)
3388 
    {
3389 
      OUTS (outf, dregs (dst0));
3390 
      OUTS (outf, " = BYTEOP2P (");
3391 
      OUTS (outf, dregs (src0 + 1));
3392 
      OUTS (outf, ":");
3393 
      OUTS (outf, imm5d (src0));
3394 
      OUTS (outf, ", ");
3395 
      OUTS (outf, dregs (src1 + 1));
3396 
      OUTS (outf, ":");
3397 
      OUTS (outf, imm5d (src1));
3398 
      OUTS (outf, ") (RNDH");
3399 
      if (s == 1)
3400 
        OUTS (outf, ", R)");
3401 
      else
3402 
        OUTS (outf, ")");
3403 
    }
3404 
  else if (aop == 0 && aopcde == 22 && HL == 0)
3405 
    {
3406 
      OUTS (outf, dregs (dst0));
3407 
      OUTS (outf, " = BYTEOP2P (");
3408 
      OUTS (outf, dregs (src0 + 1));
3409 
      OUTS (outf, ":");
3410 
      OUTS (outf, imm5d (src0));
3411 
      OUTS (outf, ", ");
3412 
      OUTS (outf, dregs (src1 + 1));
3413 
      OUTS (outf, ":");
3414 
      OUTS (outf, imm5d (src1));
3415 
      OUTS (outf, ") (RNDL");
3416 
      if (s == 1)
3417 
        OUTS (outf, ", R)");
3418 
      else
3419 
        OUTS (outf, ")");
3420 
    }
3421 
  else if (aop == 0 && s == 0 && aopcde == 8)
3422 
    OUTS (outf, "A0 = 0");
3423 
 
3424 
  else if (aop == 0 && s == 1 && aopcde == 8)
3425 
    OUTS (outf, "A0 = A0 (S)");
3426 
 
3427 
  else if (aop == 1 && s == 0 && aopcde == 8)
3428 
    OUTS (outf, "A1 = 0");
3429 
 
3430 
  else if (aop == 1 && s == 1 && aopcde == 8)
3431 
    OUTS (outf, "A1 = A1 (S)");
3432 
 
3433 
  else if (aop == 2 && s == 0 && aopcde == 8)
3434 
    OUTS (outf, "A1 = A0 = 0");
3435 
 
3436 
  else if (aop == 2 && s == 1 && aopcde == 8)
3437 
    OUTS (outf, "A1 = A1 (S), A0 = A0 (S)");
3438 
 
3439 
  else if (aop == 3 && s == 0 && aopcde == 8)
3440 
    OUTS (outf, "A0 = A1");
3441 
 
3442 
  else if (aop == 3 && s == 1 && aopcde == 8)
3443 
    OUTS (outf, "A1 = A0");
3444 
 
3445 
  else if (aop == 1 && aopcde == 9 && s == 0)
3446 
    {
3447 
      OUTS (outf, "A0.X = ");
3448 
      OUTS (outf, dregs_lo (src0));
3449 
    }
3450 
  else if (aop == 1 && HL == 0 && aopcde == 11)
3451 
    {
3452 
      OUTS (outf, dregs_lo (dst0));
3453 
      OUTS (outf, " = (A0 += A1)");
3454 
    }
3455 
  else if (aop == 3 && HL == 0 && aopcde == 16)
3456 
    OUTS (outf, "A1 = ABS A0, A0 = ABS A0");
3457 
 
3458 
  else if (aop == 0 && aopcde == 23 && HL == 1)
3459 
    {
3460 
      OUTS (outf, dregs (dst0));
3461 
      OUTS (outf, " = BYTEOP3P (");
3462 
      OUTS (outf, dregs (src0 + 1));
3463 
      OUTS (outf, ":");
3464 
      OUTS (outf, imm5d (src0));
3465 
      OUTS (outf, ", ");
3466 
      OUTS (outf, dregs (src1 + 1));
3467 
      OUTS (outf, ":");
3468 
      OUTS (outf, imm5d (src1));
3469 
      OUTS (outf, ") (HI");
3470 
      if (s == 1)
3471 
        OUTS (outf, ", R)");
3472 
      else
3473 
        OUTS (outf, ")");
3474 
    }
3475 
  else if (aop == 3 && aopcde == 9 && s == 0)
3476 
    {
3477 
      OUTS (outf, "A1.X = ");
3478 
      OUTS (outf, dregs_lo (src0));
3479 
    }
3480 
  else if (aop == 1 && HL == 1 && aopcde == 16)
3481 
    OUTS (outf, "A1 = ABS A1");
3482 
 
3483 
  else if (aop == 0 && HL == 1 && aopcde == 16)
3484 
    OUTS (outf, "A1 = ABS A0");
3485 
 
3486 
  else if (aop == 2 && aopcde == 9 && s == 1)
3487 
    {
3488 
      OUTS (outf, "A1 = ");
3489 
      OUTS (outf, dregs (src0));
3490 
    }
3491 
  else if (HL == 0 && aop == 3 && aopcde == 12)
3492 
    {
3493 
      OUTS (outf, dregs_lo (dst0));
3494 
      OUTS (outf, " = ");
3495 
      OUTS (outf, dregs (src0));
3496 
      OUTS (outf, " (RND)");
3497 
    }
3498 
  else if (aop == 1 && HL == 0 && aopcde == 16)
3499 
    OUTS (outf, "A0 = ABS A1");
3500 
 
3501 
  else if (aop == 0 && HL == 0 && aopcde == 16)
3502 
    OUTS (outf, "A0 = ABS A0");
3503 
 
3504 
  else if (aop == 3 && HL == 0 && aopcde == 15)
3505 
    {
3506 
      OUTS (outf, dregs (dst0));
3507 
      OUTS (outf, " = -");
3508 
      OUTS (outf, dregs (src0));
3509 
      OUTS (outf, " (V)");
3510 
    }
3511 
  else if (aop == 3 && s == 1 && HL == 0 && aopcde == 7)
3512 
    {
3513 
      OUTS (outf, dregs (dst0));
3514 
      OUTS (outf, " = -");
3515 
      OUTS (outf, dregs (src0));
3516 
      OUTS (outf, " (S)");
3517 
    }
3518 
  else if (aop == 3 && s == 0 && HL == 0 && aopcde == 7)
3519 
    {
3520 
      OUTS (outf, dregs (dst0));
3521 
      OUTS (outf, " = -");
3522 
      OUTS (outf, dregs (src0));
3523 
      OUTS (outf, " (NS)");
3524 
    }
3525 
  else if (aop == 1 && HL == 1 && aopcde == 11)
3526 
    {
3527 
      OUTS (outf, dregs_hi (dst0));
3528 
      OUTS (outf, " = (A0 += A1)");
3529 
    }
3530 
  else if (aop == 2 && aopcde == 11 && s == 0)
3531 
    OUTS (outf, "A0 += A1");
3532 
 
3533 
  else if (aop == 2 && aopcde == 11 && s == 1)
3534 
    OUTS (outf, "A0 += A1 (W32)");
3535 
 
3536 
  else if (aop == 3 && HL == 0 && aopcde == 14)
3537 
    OUTS (outf, "A1 = -A1, A0 = -A0");
3538 
 
3539 
  else if (HL == 1 && aop == 3 && aopcde == 12)
3540 
    {
3541 
      OUTS (outf, dregs_hi (dst0));
3542 
      OUTS (outf, " = ");
3543 
      OUTS (outf, dregs (src0));
3544 
      OUTS (outf, " (RND)");
3545 
    }
3546 
  else if (aop == 0 && aopcde == 23 && HL == 0)
3547 
    {
3548 
      OUTS (outf, dregs (dst0));
3549 
      OUTS (outf, " = BYTEOP3P (");
3550 
      OUTS (outf, dregs (src0 + 1));
3551 
      OUTS (outf, ":");
3552 
      OUTS (outf, imm5d (src0));
3553 
      OUTS (outf, ", ");
3554 
      OUTS (outf, dregs (src1 + 1));
3555 
      OUTS (outf, ":");
3556 
      OUTS (outf, imm5d (src1));
3557 
      OUTS (outf, ") (LO");
3558 
      if (s == 1)
3559 
        OUTS (outf, ", R)");
3560 
      else
3561 
        OUTS (outf, ")");
3562 
    }
3563 
  else if (aop == 0 && HL == 0 && aopcde == 14)
3564 
    OUTS (outf, "A0 = -A0");
3565 
 
3566 
  else if (aop == 1 && HL == 0 && aopcde == 14)
3567 
    OUTS (outf, "A0 = -A1");
3568 
 
3569 
  else if (aop == 0 && HL == 1 && aopcde == 14)
3570 
    OUTS (outf, "A1 = -A0");
3571 
 
3572 
  else if (aop == 1 && HL == 1 && aopcde == 14)
3573 
    OUTS (outf, "A1 = -A1");
3574 
 
3575 
  else if (aop == 0 && aopcde == 12)
3576 
    {
3577 
      OUTS (outf, dregs_hi (dst0));
3578 
      OUTS (outf, " = ");
3579 
      OUTS (outf, dregs_lo (dst0));
3580 
      OUTS (outf, " = SIGN (");
3581 
      OUTS (outf, dregs_hi (src0));
3582 
      OUTS (outf, ") * ");
3583 
      OUTS (outf, dregs_hi (src1));
3584 
      OUTS (outf, " + SIGN (");
3585 
      OUTS (outf, dregs_lo (src0));
3586 
      OUTS (outf, ") * ");
3587 
      OUTS (outf, dregs_lo (src1));
3588 
    }
3589 
  else if (aop == 2 && aopcde == 0)
3590 
    {
3591 
      OUTS (outf, dregs (dst0));
3592 
      OUTS (outf, " = ");
3593 
      OUTS (outf, dregs (src0));
3594 
      OUTS (outf, " -|+ ");
3595 
      OUTS (outf, dregs (src1));
3596 
      amod0 (s, x, outf);
3597 
    }
3598 
  else if (aop == 1 && aopcde == 12)
3599 
    {
3600 
      OUTS (outf, dregs (dst1));
3601 
      OUTS (outf, " = A1.L + A1.H, ");
3602 
      OUTS (outf, dregs (dst0));
3603 
      OUTS (outf, " = A0.L + A0.H");
3604 
    }
3605 
  else if (aop == 2 && aopcde == 4)
3606 
    {
3607 
      OUTS (outf, dregs (dst1));
3608 
      OUTS (outf, " = ");
3609 
      OUTS (outf, dregs (src0));
3610 
      OUTS (outf, " + ");
3611 
      OUTS (outf, dregs (src1));
3612 
      OUTS (outf, ", ");
3613 
      OUTS (outf, dregs (dst0));
3614 
      OUTS (outf, " = ");
3615 
      OUTS (outf, dregs (src0));
3616 
      OUTS (outf, " - ");
3617 
      OUTS (outf, dregs (src1));
3618 
      amod1 (s, x, outf);
3619 
    }
3620 
  else if (HL == 0 && aopcde == 1)
3621 
    {
3622 
      OUTS (outf, dregs (dst1));
3623 
      OUTS (outf, " = ");
3624 
      OUTS (outf, dregs (src0));
3625 
      OUTS (outf, " +|+ ");
3626 
      OUTS (outf, dregs (src1));
3627 
      OUTS (outf, ", ");
3628 
      OUTS (outf, dregs (dst0));
3629 
      OUTS (outf, " = ");
3630 
      OUTS (outf, dregs (src0));
3631 
      OUTS (outf, " -|- ");
3632 
      OUTS (outf, dregs (src1));
3633 
      amod0amod2 (s, x, aop, outf);
3634 
    }
3635 
  else if (aop == 0 && aopcde == 11)
3636 
    {
3637 
      OUTS (outf, dregs (dst0));
3638 
      OUTS (outf, " = (A0 += A1)");
3639 
    }
3640 
  else if (aop == 0 && aopcde == 10)
3641 
    {
3642 
      OUTS (outf, dregs_lo (dst0));
3643 
      OUTS (outf, " = A0.X");
3644 
    }
3645 
  else if (aop == 1 && aopcde == 10)
3646 
    {
3647 
      OUTS (outf, dregs_lo (dst0));
3648 
      OUTS (outf, " = A1.X");
3649 
    }
3650 
  else if (aop == 1 && aopcde == 0)
3651 
    {
3652 
      OUTS (outf, dregs (dst0));
3653 
      OUTS (outf, " = ");
3654 
      OUTS (outf, dregs (src0));
3655 
      OUTS (outf, " +|- ");
3656 
      OUTS (outf, dregs (src1));
3657 
      amod0 (s, x, outf);
3658 
    }
3659 
  else if (aop == 3 && aopcde == 0)
3660 
    {
3661 
      OUTS (outf, dregs (dst0));
3662 
      OUTS (outf, " = ");
3663 
      OUTS (outf, dregs (src0));
3664 
      OUTS (outf, " -|- ");
3665 
      OUTS (outf, dregs (src1));
3666 
      amod0 (s, x, outf);
3667 
    }
3668 
  else if (aop == 1 && aopcde == 4)
3669 
    {
3670 
      OUTS (outf, dregs (dst0));
3671 
      OUTS (outf, " = ");
3672 
      OUTS (outf, dregs (src0));
3673 
      OUTS (outf, " - ");
3674 
      OUTS (outf, dregs (src1));
3675 
      amod1 (s, x, outf);
3676 
    }
3677 
  else if (aop == 0 && aopcde == 17)
3678 
    {
3679 
      OUTS (outf, dregs (dst1));
3680 
      OUTS (outf, " = A1 + A0, ");
3681 
      OUTS (outf, dregs (dst0));
3682 
      OUTS (outf, " = A1 - A0");
3683 
      amod1 (s, x, outf);
3684 
    }
3685 
  else if (aop == 1 && aopcde == 17)
3686 
    {
3687 
      OUTS (outf, dregs (dst1));
3688 
      OUTS (outf, " = A0 + A1, ");
3689 
      OUTS (outf, dregs (dst0));
3690 
      OUTS (outf, " = A0 - A1");
3691 
      amod1 (s, x, outf);
3692 
    }
3693 
  else if (aop == 0 && aopcde == 18)
3694 
    {
3695 
      OUTS (outf, "SAA (");
3696 
      OUTS (outf, dregs (src0 + 1));
3697 
      OUTS (outf, ":");
3698 
      OUTS (outf, imm5d (src0));
3699 
      OUTS (outf, ", ");
3700 
      OUTS (outf, dregs (src1 + 1));
3701 
      OUTS (outf, ":");
3702 
      OUTS (outf, imm5d (src1));
3703 
      OUTS (outf, ")");
3704 
      aligndir (s, outf);
3705 
    }
3706 
  else if (aop == 3 && aopcde == 18)
3707 
    OUTS (outf, "DISALGNEXCPT");
3708 
 
3709 
  else if (aop == 0 && aopcde == 20)
3710 
    {
3711 
      OUTS (outf, dregs (dst0));
3712 
      OUTS (outf, " = BYTEOP1P (");
3713 
      OUTS (outf, dregs (src0 + 1));
3714 
      OUTS (outf, ":");
3715 
      OUTS (outf, imm5d (src0));
3716 
      OUTS (outf, ", ");
3717 
      OUTS (outf, dregs (src1 + 1));
3718 
      OUTS (outf, ":");
3719 
      OUTS (outf, imm5d (src1));
3720 
      OUTS (outf, ")");
3721 
      aligndir (s, outf);
3722 
    }
3723 
  else if (aop == 1 && aopcde == 20)
3724 
    {
3725 
      OUTS (outf, dregs (dst0));
3726 
      OUTS (outf, " = BYTEOP1P (");
3727 
      OUTS (outf, dregs (src0 + 1));
3728 
      OUTS (outf, ":");
3729 
      OUTS (outf, imm5d (src0));
3730 
      OUTS (outf, ", ");
3731 
      OUTS (outf, dregs (src1 + 1));
3732 
      OUTS (outf, ":");
3733 
      OUTS (outf, imm5d (src1));
3734 
      OUTS (outf, ") (T");
3735 
      if (s == 1)
3736 
        OUTS (outf, ", R)");
3737 
      else
3738 
        OUTS (outf, ")");
3739 
    }
3740 
  else if (aop == 0 && aopcde == 21)
3741 
    {
3742 
      OUTS (outf, "(");
3743 
      OUTS (outf, dregs (dst1));
3744 
      OUTS (outf, ", ");
3745 
      OUTS (outf, dregs (dst0));
3746 
      OUTS (outf, ") = BYTEOP16P (");
3747 
      OUTS (outf, dregs (src0 + 1));
3748 
      OUTS (outf, ":");
3749 
      OUTS (outf, imm5d (src0));
3750 
      OUTS (outf, ", ");
3751 
      OUTS (outf, dregs (src1 + 1));
3752 
      OUTS (outf, ":");
3753 
      OUTS (outf, imm5d (src1));
3754 
      OUTS (outf, ")");
3755 
      aligndir (s, outf);
3756 
    }
3757 
  else if (aop == 1 && aopcde == 21)
3758 
    {
3759 
      OUTS (outf, "(");
3760 
      OUTS (outf, dregs (dst1));
3761 
      OUTS (outf, ", ");
3762 
      OUTS (outf, dregs (dst0));
3763 
      OUTS (outf, ") = BYTEOP16M (");
3764 
      OUTS (outf, dregs (src0 + 1));
3765 
      OUTS (outf, ":");
3766 
      OUTS (outf, imm5d (src0));
3767 
      OUTS (outf, ", ");
3768 
      OUTS (outf, dregs (src1 + 1));
3769 
      OUTS (outf, ":");
3770 
      OUTS (outf, imm5d (src1));
3771 
      OUTS (outf, ")");
3772 
      aligndir (s, outf);
3773 
    }
3774 
  else if (aop == 2 && aopcde == 7)
3775 
    {
3776 
      OUTS (outf, dregs (dst0));
3777 
      OUTS (outf, " = ABS ");
3778 
      OUTS (outf, dregs (src0));
3779 
    }
3780 
  else if (aop == 1 && aopcde == 7)
3781 
    {
3782 
      OUTS (outf, dregs (dst0));
3783 
      OUTS (outf, " = MIN (");
3784 
      OUTS (outf, dregs (src0));
3785 
      OUTS (outf, ", ");
3786 
      OUTS (outf, dregs (src1));
3787 
      OUTS (outf, ")");
3788 
    }
3789 
  else if (aop == 0 && aopcde == 7)
3790 
    {
3791 
      OUTS (outf, dregs (dst0));
3792 
      OUTS (outf, " = MAX (");
3793 
      OUTS (outf, dregs (src0));
3794 
      OUTS (outf, ", ");
3795 
      OUTS (outf, dregs (src1));
3796 
      OUTS (outf, ")");
3797 
    }
3798 
  else if (aop == 2 && aopcde == 6)
3799 
    {
3800 
      OUTS (outf, dregs (dst0));
3801 
      OUTS (outf, " = ABS ");
3802 
      OUTS (outf, dregs (src0));
3803 
      OUTS (outf, " (V)");
3804 
    }
3805 
  else if (aop == 1 && aopcde == 6)
3806 
    {
3807 
      OUTS (outf, dregs (dst0));
3808 
      OUTS (outf, " = MIN (");
3809 
      OUTS (outf, dregs (src0));
3810 
      OUTS (outf, ", ");
3811 
      OUTS (outf, dregs (src1));
3812 
      OUTS (outf, ") (V)");
3813 
    }
3814 
  else if (aop == 0 && aopcde == 6)
3815 
    {
3816 
      OUTS (outf, dregs (dst0));
3817 
      OUTS (outf, " = MAX (");
3818 
      OUTS (outf, dregs (src0));
3819 
      OUTS (outf, ", ");
3820 
      OUTS (outf, dregs (src1));
3821 
      OUTS (outf, ") (V)");
3822 
    }
3823 
  else if (HL == 1 && aopcde == 1)
3824 
    {
3825 
      OUTS (outf, dregs (dst1));
3826 
      OUTS (outf, " = ");
3827 
      OUTS (outf, dregs (src0));
3828 
      OUTS (outf, " +|- ");
3829 
      OUTS (outf, dregs (src1));
3830 
      OUTS (outf, ", ");
3831 
      OUTS (outf, dregs (dst0));
3832 
      OUTS (outf, " = ");
3833 
      OUTS (outf, dregs (src0));
3834 
      OUTS (outf, " -|+ ");
3835 
      OUTS (outf, dregs (src1));
3836 
      amod0amod2 (s, x, aop, outf);
3837 
    }
3838 
  else if (aop == 0 && aopcde == 4)
3839 
    {
3840 
      OUTS (outf, dregs (dst0));
3841 
      OUTS (outf, " = ");
3842 
      OUTS (outf, dregs (src0));
3843 
      OUTS (outf, " + ");
3844 
      OUTS (outf, dregs (src1));
3845 
      amod1 (s, x, outf);
3846 
    }
3847 
  else if (aop == 0 && aopcde == 0)
3848 
    {
3849 
      OUTS (outf, dregs (dst0));
3850 
      OUTS (outf, " = ");
3851 
      OUTS (outf, dregs (src0));
3852 
      OUTS (outf, " +|+ ");
3853 
      OUTS (outf, dregs (src1));
3854 
      amod0 (s, x, outf);
3855 
    }
3856 
  else if (aop == 0 && aopcde == 24)
3857 
    {
3858 
      OUTS (outf, dregs (dst0));
3859 
      OUTS (outf, " = BYTEPACK (");
3860 
      OUTS (outf, dregs (src0));
3861 
      OUTS (outf, ", ");
3862 
      OUTS (outf, dregs (src1));
3863 
      OUTS (outf, ")");
3864 
    }
3865 
  else if (aop == 1 && aopcde == 24)
3866 
    {
3867 
      OUTS (outf, "(");
3868 
      OUTS (outf, dregs (dst1));
3869 
      OUTS (outf, ", ");
3870 
      OUTS (outf, dregs (dst0));
3871 
      OUTS (outf, ") = BYTEUNPACK ");
3872 
      OUTS (outf, dregs (src0 + 1));
3873 
      OUTS (outf, ":");
3874 
      OUTS (outf, imm5d (src0));
3875 
      aligndir (s, outf);
3876 
    }
3877 
  else if (aopcde == 13)
3878 
    {
3879 
      OUTS (outf, "(");
3880 
      OUTS (outf, dregs (dst1));
3881 
      OUTS (outf, ", ");
3882 
      OUTS (outf, dregs (dst0));
3883 
      OUTS (outf, ") = SEARCH ");
3884 
      OUTS (outf, dregs (src0));
3885 
      OUTS (outf, " (");
3886 
      searchmod (aop, outf);
3887 
      OUTS (outf, ")");
3888 
    }
3889 
  else
3890 
    return 0;
3891 
 
3892 
  return 4;
3893 
}
3894 
 
3895 
static int
3896 
decode_dsp32shift_0 (TIword iw0, TIword iw1, disassemble_info *outf)
3897 
{
3898 
  /* dsp32shift
3899 
     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
3900 
     | 1 | 1 | 0 | 0 |.M.| 1 | 1 | 0 | 0 | - | - |.sopcde............|
3901 
     |.sop...|.HLs...|.dst0......| - | - | - |.src0......|.src1......|
3902 
     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+  */
3903 
  int HLs  = ((iw1 >> DSP32Shift_HLs_bits) & DSP32Shift_HLs_mask);
3904 
  int sop  = ((iw1 >> DSP32Shift_sop_bits) & DSP32Shift_sop_mask);
3905 
  int src0 = ((iw1 >> DSP32Shift_src0_bits) & DSP32Shift_src0_mask);
3906 
  int src1 = ((iw1 >> DSP32Shift_src1_bits) & DSP32Shift_src1_mask);
3907 
  int dst0 = ((iw1 >> DSP32Shift_dst0_bits) & DSP32Shift_dst0_mask);
3908 
  int sopcde = ((iw0 >> (DSP32Shift_sopcde_bits - 16)) & DSP32Shift_sopcde_mask);
3909 
  const char *acc01 = (HLs & 1) == 0 ? "A0" : "A1";
3910 
 
3911 
  if (HLs == 0 && sop == 0 && sopcde == 0)
3912 
    {
3913 
      OUTS (outf, dregs_lo (dst0));
3914 
      OUTS (outf, " = ASHIFT ");
3915 
      OUTS (outf, dregs_lo (src1));
3916 
      OUTS (outf, " BY ");
3917 
      OUTS (outf, dregs_lo (src0));
3918 
    }
3919 
  else if (HLs == 1 && sop == 0 && sopcde == 0)
3920 
    {
3921 
      OUTS (outf, dregs_lo (dst0));
3922 
      OUTS (outf, " = ASHIFT ");
3923 
      OUTS (outf, dregs_hi (src1));
3924 
      OUTS (outf, " BY ");
3925 
      OUTS (outf, dregs_lo (src0));
3926 
    }
3927 
  else if (HLs == 2 && sop == 0 && sopcde == 0)
3928 
    {
3929 
      OUTS (outf, dregs_hi (dst0));
3930 
      OUTS (outf, " = ASHIFT ");
3931 
      OUTS (outf, dregs_lo (src1));
3932 
      OUTS (outf, " BY ");
3933 
      OUTS (outf, dregs_lo (src0));
3934 
    }
3935 
  else if (HLs == 3 && sop == 0 && sopcde == 0)
3936 
    {
3937 
      OUTS (outf, dregs_hi (dst0));
3938 
      OUTS (outf, " = ASHIFT ");
3939 
      OUTS (outf, dregs_hi (src1));
3940 
      OUTS (outf, " BY ");
3941 
      OUTS (outf, dregs_lo (src0));
3942 
    }
3943 
  else if (HLs == 0 && sop == 1 && sopcde == 0)
3944 
    {
3945 
      OUTS (outf, dregs_lo (dst0));
3946 
      OUTS (outf, " = ASHIFT ");
3947 
      OUTS (outf, dregs_lo (src1));
3948 
      OUTS (outf, " BY ");
3949 
      OUTS (outf, dregs_lo (src0));
3950 
      OUTS (outf, " (S)");
3951 
    }
3952 
  else if (HLs == 1 && sop == 1 && sopcde == 0)
3953 
    {
3954 
      OUTS (outf, dregs_lo (dst0));
3955 
      OUTS (outf, " = ASHIFT ");
3956 
      OUTS (outf, dregs_hi (src1));
3957 
      OUTS (outf, " BY ");
3958 
      OUTS (outf, dregs_lo (src0));
3959 
      OUTS (outf, " (S)");
3960 
    }
3961 
  else if (HLs == 2 && sop == 1 && sopcde == 0)
3962 
    {
3963 
      OUTS (outf, dregs_hi (dst0));
3964 
      OUTS (outf, " = ASHIFT ");
3965 
      OUTS (outf, dregs_lo (src1));
3966 
      OUTS (outf, " BY ");
3967 
      OUTS (outf, dregs_lo (src0));
3968 
      OUTS (outf, " (S)");
3969 
    }
3970 
  else if (HLs == 3 && sop == 1 && sopcde == 0)
3971 
    {
3972 
      OUTS (outf, dregs_hi (dst0));
3973 
      OUTS (outf, " = ASHIFT ");
3974 
      OUTS (outf, dregs_hi (src1));
3975 
      OUTS (outf, " BY ");
3976 
      OUTS (outf, dregs_lo (src0));
3977 
      OUTS (outf, " (S)");
3978 
    }
3979 
  else if (sop == 2 && sopcde == 0)
3980 
    {
3981 
      OUTS (outf, (HLs & 2) == 0 ? dregs_lo (dst0) : dregs_hi (dst0));
3982 
      OUTS (outf, " = LSHIFT ");
3983 
      OUTS (outf, (HLs & 1) == 0 ? dregs_lo (src1) : dregs_hi (src1));
3984 
      OUTS (outf, " BY ");
3985 
      OUTS (outf, dregs_lo (src0));
3986 
    }
3987 
  else if (sop == 0 && sopcde == 3)
3988 
    {
3989 
      OUTS (outf, acc01);
3990 
      OUTS (outf, " = ASHIFT ");
3991 
      OUTS (outf, acc01);
3992 
      OUTS (outf, " BY ");
3993 
      OUTS (outf, dregs_lo (src0));
3994 
    }
3995 
  else if (sop == 1 && sopcde == 3)
3996 
    {
3997 
      OUTS (outf, acc01);
3998 
      OUTS (outf, " = LSHIFT ");
3999 
      OUTS (outf, acc01);
4000 
      OUTS (outf, " BY ");
4001 
      OUTS (outf, dregs_lo (src0));
4002 
    }
4003 
  else if (sop == 2 && sopcde == 3)
4004 
    {
4005 
      OUTS (outf, acc01);
4006 
      OUTS (outf, " = ROT ");
4007 
      OUTS (outf, acc01);
4008 
      OUTS (outf, " BY ");
4009 
      OUTS (outf, dregs_lo (src0));
4010 
    }
4011 
  else if (sop == 3 && sopcde == 3)
4012 
    {
4013 
      OUTS (outf, dregs (dst0));
4014 
      OUTS (outf, " = ROT ");
4015 
      OUTS (outf, dregs (src1));
4016 
      OUTS (outf, " BY ");
4017 
      OUTS (outf, dregs_lo (src0));
4018 
    }
4019 
  else if (sop == 1 && sopcde == 1)
4020 
    {
4021 
      OUTS (outf, dregs (dst0));
4022 
      OUTS (outf, " = ASHIFT ");
4023 
      OUTS (outf, dregs (src1));
4024 
      OUTS (outf, " BY ");
4025 
      OUTS (outf, dregs_lo (src0));
4026 
      OUTS (outf, " (V, S)");
4027 
    }
4028 
  else if (sop == 0 && sopcde == 1)
4029 
    {
4030 
      OUTS (outf, dregs (dst0));
4031 
      OUTS (outf, " = ASHIFT ");
4032 
      OUTS (outf, dregs (src1));
4033 
      OUTS (outf, " BY ");
4034 
      OUTS (outf, dregs_lo (src0));
4035 
      OUTS (outf, " (V)");
4036 
    }
4037 
  else if (sop == 0 && sopcde == 2)
4038 
    {
4039 
      OUTS (outf, dregs (dst0));
4040 
      OUTS (outf, " = ASHIFT ");
4041 
      OUTS (outf, dregs (src1));
4042 
      OUTS (outf, " BY ");
4043 
      OUTS (outf, dregs_lo (src0));
4044 
    }
4045 
  else if (sop == 1 && sopcde == 2)
4046 
    {
4047 
      OUTS (outf, dregs (dst0));
4048 
      OUTS (outf, " = ASHIFT ");
4049 
      OUTS (outf, dregs (src1));
4050 
      OUTS (outf, " BY ");
4051 
      OUTS (outf, dregs_lo (src0));
4052 
      OUTS (outf, " (S)");
4053 
    }
4054 
  else if (sop == 2 && sopcde == 2)
4055 
    {
4056 
      OUTS (outf, dregs (dst0));
4057 
      OUTS (outf, " = SHIFT ");
4058 
      OUTS (outf, dregs (src1));
4059 
      OUTS (outf, " BY ");
4060 
      OUTS (outf, dregs_lo (src0));
4061 
    }
4062 
  else if (sop == 3 && sopcde == 2)
4063 
    {
4064 
      OUTS (outf, dregs (dst0));
4065 
      OUTS (outf, " = ROT ");
4066 
      OUTS (outf, dregs (src1));
4067 
      OUTS (outf, " BY ");
4068 
      OUTS (outf, dregs_lo (src0));
4069 
    }
4070 
  else if (sop == 2 && sopcde == 1)
4071 
    {
4072 
      OUTS (outf, dregs (dst0));
4073 
      OUTS (outf, " = SHIFT ");
4074 
      OUTS (outf, dregs (src1));
4075 
      OUTS (outf, " BY ");
4076 
      OUTS (outf, dregs_lo (src0));
4077 
      OUTS (outf, " (V)");
4078 
    }
4079 
  else if (sop == 0 && sopcde == 4)
4080 
    {
4081 
      OUTS (outf, dregs (dst0));
4082 
      OUTS (outf, " = PACK (");
4083 
      OUTS (outf, dregs_lo (src1));
4084 
      OUTS (outf, ", ");
4085 
      OUTS (outf, dregs_lo (src0));
4086 
      OUTS (outf, ")");
4087 
    }
4088 
  else if (sop == 1 && sopcde == 4)
4089 
    {
4090 
      OUTS (outf, dregs (dst0));
4091 
      OUTS (outf, " = PACK (");
4092 
      OUTS (outf, dregs_lo (src1));
4093 
      OUTS (outf, ", ");
4094 
      OUTS (outf, dregs_hi (src0));
4095 
      OUTS (outf, ")");
4096 
    }
4097 
  else if (sop == 2 && sopcde == 4)
4098 
    {
4099 
      OUTS (outf, dregs (dst0));
4100 
      OUTS (outf, " = PACK (");
4101 
      OUTS (outf, dregs_hi (src1));
4102 
      OUTS (outf, ", ");
4103 
      OUTS (outf, dregs_lo (src0));
4104 
      OUTS (outf, ")");
4105 
    }
4106 
  else if (sop == 3 && sopcde == 4)
4107 
    {
4108 
      OUTS (outf, dregs (dst0));
4109 
      OUTS (outf, " = PACK (");
4110 
      OUTS (outf, dregs_hi (src1));
4111 
      OUTS (outf, ", ");
4112 
      OUTS (outf, dregs_hi (src0));
4113 
      OUTS (outf, ")");
4114 
    }
4115 
  else if (sop == 0 && sopcde == 5)
4116 
    {
4117 
      OUTS (outf, dregs_lo (dst0));
4118 
      OUTS (outf, " = SIGNBITS ");
4119 
      OUTS (outf, dregs (src1));
4120 
    }
4121 
  else if (sop == 1 && sopcde == 5)
4122 
    {
4123 
      OUTS (outf, dregs_lo (dst0));
4124 
      OUTS (outf, " = SIGNBITS ");
4125 
      OUTS (outf, dregs_lo (src1));
4126 
    }
4127 
  else if (sop == 2 && sopcde == 5)
4128 
    {
4129 
      OUTS (outf, dregs_lo (dst0));
4130 
      OUTS (outf, " = SIGNBITS ");
4131 
      OUTS (outf, dregs_hi (src1));
4132 
    }
4133 
  else if (sop == 0 && sopcde == 6)
4134 
    {
4135 
      OUTS (outf, dregs_lo (dst0));
4136 
      OUTS (outf, " = SIGNBITS A0");
4137 
    }
4138 
  else if (sop == 1 && sopcde == 6)
4139 
    {
4140 
      OUTS (outf, dregs_lo (dst0));
4141 
      OUTS (outf, " = SIGNBITS A1");
4142 
    }
4143 
  else if (sop == 3 && sopcde == 6)
4144 
    {
4145 
      OUTS (outf, dregs_lo (dst0));
4146 
      OUTS (outf, " = ONES ");
4147 
      OUTS (outf, dregs (src1));
4148 
    }
4149 
  else if (sop == 0 && sopcde == 7)
4150 
    {
4151 
      OUTS (outf, dregs_lo (dst0));
4152 
      OUTS (outf, " = EXPADJ (");
4153 
      OUTS (outf, dregs (src1));
4154 
      OUTS (outf, ", ");
4155 
      OUTS (outf, dregs_lo (src0));
4156 
      OUTS (outf, ")");
4157 
    }
4158 
  else if (sop == 1 && sopcde == 7)
4159 
    {
4160 
      OUTS (outf, dregs_lo (dst0));
4161 
      OUTS (outf, " = EXPADJ (");
4162 
      OUTS (outf, dregs (src1));
4163 
      OUTS (outf, ", ");
4164 
      OUTS (outf, dregs_lo (src0));
4165 
      OUTS (outf, ") (V)");
4166 
    }
4167 
  else if (sop == 2 && sopcde == 7)
4168 
    {
4169 
      OUTS (outf, dregs_lo (dst0));
4170 
      OUTS (outf, " = EXPADJ (");
4171 
      OUTS (outf, dregs_lo (src1));
4172 
      OUTS (outf, ", ");
4173 
      OUTS (outf, dregs_lo (src0));
4174 
      OUTS (outf, ")");
4175 
    }
4176 
  else if (sop == 3 && sopcde == 7)
4177 
    {
4178 
      OUTS (outf, dregs_lo (dst0));
4179 
      OUTS (outf, " = EXPADJ (");
4180 
      OUTS (outf, dregs_hi (src1));
4181 
      OUTS (outf, ", ");
4182 
      OUTS (outf, dregs_lo (src0));
4183 
      OUTS (outf, ")");
4184 
    }
4185 
  else if (sop == 0 && sopcde == 8)
4186 
    {
4187 
      OUTS (outf, "BITMUX (");
4188 
      OUTS (outf, dregs (src0));
4189 
      OUTS (outf, ", ");
4190 
      OUTS (outf, dregs (src1));
4191 
      OUTS (outf, ", A0) (ASR)");
4192 
    }
4193 
  else if (sop == 1 && sopcde == 8)
4194 
    {
4195 
      OUTS (outf, "BITMUX (");
4196 
      OUTS (outf, dregs (src0));
4197 
      OUTS (outf, ", ");
4198 
      OUTS (outf, dregs (src1));
4199 
      OUTS (outf, ", A0) (ASL)");
4200 
    }
4201 
  else if (sop == 0 && sopcde == 9)
4202 
    {
4203 
      OUTS (outf, dregs_lo (dst0));
4204 
      OUTS (outf, " = VIT_MAX (");
4205 
      OUTS (outf, dregs (src1));
4206 
      OUTS (outf, ") (ASL)");
4207 
    }
4208 
  else if (sop == 1 && sopcde == 9)
4209 
    {
4210 
      OUTS (outf, dregs_lo (dst0));
4211 
      OUTS (outf, " = VIT_MAX (");
4212 
      OUTS (outf, dregs (src1));
4213 
      OUTS (outf, ") (ASR)");
4214 
    }
4215 
  else if (sop == 2 && sopcde == 9)
4216 
    {
4217 
      OUTS (outf, dregs (dst0));
4218 
      OUTS (outf, " = VIT_MAX (");
4219 
      OUTS (outf, dregs (src1));
4220 
      OUTS (outf, ", ");
4221 
      OUTS (outf, dregs (src0));
4222 
      OUTS (outf, ") (ASL)");
4223 
    }
4224 
  else if (sop == 3 && sopcde == 9)
4225 
    {
4226 
      OUTS (outf, dregs (dst0));
4227 
      OUTS (outf, " = VIT_MAX (");
4228 
      OUTS (outf, dregs (src1));
4229 
      OUTS (outf, ", ");
4230 
      OUTS (outf, dregs (src0));
4231 
      OUTS (outf, ") (ASR)");
4232 
    }
4233 
  else if (sop == 0 && sopcde == 10)
4234 
    {
4235 
      OUTS (outf, dregs (dst0));
4236 
      OUTS (outf, " = EXTRACT (");
4237 
      OUTS (outf, dregs (src1));
4238 
      OUTS (outf, ", ");
4239 
      OUTS (outf, dregs_lo (src0));
4240 
      OUTS (outf, ") (Z)");
4241 
    }
4242 
  else if (sop == 1 && sopcde == 10)
4243 
    {
4244 
      OUTS (outf, dregs (dst0));
4245 
      OUTS (outf, " = EXTRACT (");
4246 
      OUTS (outf, dregs (src1));
4247 
      OUTS (outf, ", ");
4248 
      OUTS (outf, dregs_lo (src0));
4249 
      OUTS (outf, ") (X)");
4250 
    }
4251 
  else if (sop == 2 && sopcde == 10)
4252 
    {
4253 
      OUTS (outf, dregs (dst0));
4254 
      OUTS (outf, " = DEPOSIT (");
4255 
      OUTS (outf, dregs (src1));
4256 
      OUTS (outf, ", ");
4257 
      OUTS (outf, dregs (src0));
4258 
      OUTS (outf, ")");
4259 
    }
4260 
  else if (sop == 3 && sopcde == 10)
4261 
    {
4262 
      OUTS (outf, dregs (dst0));
4263 
      OUTS (outf, " = DEPOSIT (");
4264 
      OUTS (outf, dregs (src1));
4265 
      OUTS (outf, ", ");
4266 
      OUTS (outf, dregs (src0));
4267 
      OUTS (outf, ") (X)");
4268 
    }
4269 
  else if (sop == 0 && sopcde == 11)
4270 
    {
4271 
      OUTS (outf, dregs_lo (dst0));
4272 
      OUTS (outf, " = CC = BXORSHIFT (A0, ");
4273 
      OUTS (outf, dregs (src0));
4274 
      OUTS (outf, ")");
4275 
    }
4276 
  else if (sop == 1 && sopcde == 11)
4277 
    {
4278 
      OUTS (outf, dregs_lo (dst0));
4279 
      OUTS (outf, " = CC = BXOR (A0, ");
4280 
      OUTS (outf, dregs (src0));
4281 
      OUTS (outf, ")");
4282 
    }
4283 
  else if (sop == 0 && sopcde == 12)
4284 
    OUTS (outf, "A0 = BXORSHIFT (A0, A1, CC)");
4285 
 
4286 
  else if (sop == 1 && sopcde == 12)
4287 
    {
4288 
      OUTS (outf, dregs_lo (dst0));
4289 
      OUTS (outf, " = CC = BXOR (A0, A1, CC)");
4290 
    }
4291 
  else if (sop == 0 && sopcde == 13)
4292 
    {
4293 
      OUTS (outf, dregs (dst0));
4294 
      OUTS (outf, " = ALIGN8 (");
4295 
      OUTS (outf, dregs (src1));
4296 
      OUTS (outf, ", ");
4297 
      OUTS (outf, dregs (src0));
4298 
      OUTS (outf, ")");
4299 
    }
4300 
  else if (sop == 1 && sopcde == 13)
4301 
    {
4302 
      OUTS (outf, dregs (dst0));
4303 
      OUTS (outf, " = ALIGN16 (");
4304 
      OUTS (outf, dregs (src1));
4305 
      OUTS (outf, ", ");
4306 
      OUTS (outf, dregs (src0));
4307 
      OUTS (outf, ")");
4308 
    }
4309 
  else if (sop == 2 && sopcde == 13)
4310 
    {
4311 
      OUTS (outf, dregs (dst0));
4312 
      OUTS (outf, " = ALIGN24 (");
4313 
      OUTS (outf, dregs (src1));
4314 
      OUTS (outf, ", ");
4315 
      OUTS (outf, dregs (src0));
4316 
      OUTS (outf, ")");
4317 
    }
4318 
  else
4319 
    return 0;
4320 
 
4321 
  return 4;
4322 
}
4323 
 
4324 
static int
4325 
decode_dsp32shiftimm_0 (TIword iw0, TIword iw1, disassemble_info *outf)
4326 
{
4327 
  /* dsp32shiftimm
4328 
     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
4329 
     | 1 | 1 | 0 | 0 |.M.| 1 | 1 | 0 | 1 | - | - |.sopcde............|
4330 
     |.sop...|.HLs...|.dst0......|.immag.................|.src1......|
4331 
     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+  */
4332 
  int src1     = ((iw1 >> DSP32ShiftImm_src1_bits) & DSP32ShiftImm_src1_mask);
4333 
  int sop      = ((iw1 >> DSP32ShiftImm_sop_bits) & DSP32ShiftImm_sop_mask);
4334 
  int bit8     = ((iw1 >> 8) & 0x1);
4335 
  int immag    = ((iw1 >> DSP32ShiftImm_immag_bits) & DSP32ShiftImm_immag_mask);
4336 
  int newimmag = (-(iw1 >> DSP32ShiftImm_immag_bits) & DSP32ShiftImm_immag_mask);
4337 
  int dst0     = ((iw1 >> DSP32ShiftImm_dst0_bits) & DSP32ShiftImm_dst0_mask);
4338 
  int sopcde   = ((iw0 >> (DSP32ShiftImm_sopcde_bits - 16)) & DSP32ShiftImm_sopcde_mask);
4339 
  int HLs      = ((iw1 >> DSP32ShiftImm_HLs_bits) & DSP32ShiftImm_HLs_mask);
4340 
 
4341 
 
4342 
  if (sop == 0 && sopcde == 0)
4343 
    {
4344 
      OUTS (outf, (HLs & 2) ? dregs_hi (dst0) : dregs_lo (dst0));
4345 
      OUTS (outf, " = ");
4346 
      OUTS (outf, (HLs & 1) ? dregs_hi (src1) : dregs_lo (src1));
4347 
      OUTS (outf, " >>> ");
4348 
      OUTS (outf, uimm4 (newimmag));
4349 
    }
4350 
  else if (sop == 1 && sopcde == 0 && bit8 == 0)
4351 
    {
4352 
      OUTS (outf, (HLs & 2) ? dregs_hi (dst0) : dregs_lo (dst0));
4353 
      OUTS (outf, " = ");
4354 
      OUTS (outf, (HLs & 1) ? dregs_hi (src1) : dregs_lo (src1));
4355 
      OUTS (outf, " << ");
4356 
      OUTS (outf, uimm4 (immag));
4357 
      OUTS (outf, " (S)");
4358 
    }
4359 
  else if (sop == 1 && sopcde == 0 && bit8 == 1)
4360 
    {
4361 
      OUTS (outf, (HLs & 2) ? dregs_hi (dst0) : dregs_lo (dst0));
4362 
      OUTS (outf, " = ");
4363 
      OUTS (outf, (HLs & 1) ? dregs_hi (src1) : dregs_lo (src1));
4364 
      OUTS (outf, " >>> ");
4365 
      OUTS (outf, uimm4 (newimmag));
4366 
      OUTS (outf, " (S)");
4367 
    }
4368 
  else if (sop == 2 && sopcde == 0 && bit8 == 0)
4369 
    {
4370 
      OUTS (outf, (HLs & 2) ? dregs_hi (dst0) : dregs_lo (dst0));
4371 
      OUTS (outf, " = ");
4372 
      OUTS (outf, (HLs & 1) ? dregs_hi (src1) : dregs_lo (src1));
4373 
      OUTS (outf, " << ");
4374 
      OUTS (outf, uimm4 (immag));
4375 
    }
4376 
  else if (sop == 2 && sopcde == 0 && bit8 == 1)
4377 
    {
4378 
      OUTS (outf, (HLs & 2) ? dregs_hi (dst0) : dregs_lo (dst0));
4379 
      OUTS (outf, " = ");
4380 
      OUTS (outf, (HLs & 1) ? dregs_hi (src1) : dregs_lo (src1));
4381 
      OUTS (outf, " >> ");
4382 
      OUTS (outf, uimm4 (newimmag));
4383 
    }
4384 
  else if (sop == 2 && sopcde == 3 && HLs == 1)
4385 
    {
4386 
      OUTS (outf, "A1 = ROT A1 BY ");
4387 
      OUTS (outf, imm6 (immag));
4388 
    }
4389 
  else if (sop == 0 && sopcde == 3 && HLs == 0 && bit8 == 0)
4390 
    {
4391 
      OUTS (outf, "A0 = A0 << ");
4392 
      OUTS (outf, uimm5 (immag));
4393 
    }
4394 
  else if (sop == 0 && sopcde == 3 && HLs == 0 && bit8 == 1)
4395 
    {
4396 
      OUTS (outf, "A0 = A0 >>> ");
4397 
      OUTS (outf, uimm5 (newimmag));
4398 
    }
4399 
  else if (sop == 0 && sopcde == 3 && HLs == 1 && bit8 == 0)
4400 
    {
4401 
      OUTS (outf, "A1 = A1 << ");
4402 
      OUTS (outf, uimm5 (immag));
4403 
    }
4404 
  else if (sop == 0 && sopcde == 3 && HLs == 1 && bit8 == 1)
4405 
    {
4406 
      OUTS (outf, "A1 = A1 >>> ");
4407 
      OUTS (outf, uimm5 (newimmag));
4408 
    }
4409 
  else if (sop == 1 && sopcde == 3 && HLs == 0)
4410 
    {
4411 
      OUTS (outf, "A0 = A0 >> ");
4412 
      OUTS (outf, uimm5 (newimmag));
4413 
    }
4414 
  else if (sop == 1 && sopcde == 3 && HLs == 1)
4415 
    {
4416 
      OUTS (outf, "A1 = A1 >> ");
4417 
      OUTS (outf, uimm5 (newimmag));
4418 
    }
4419 
  else if (sop == 2 && sopcde == 3 && HLs == 0)
4420 
    {
4421 
      OUTS (outf, "A0 = ROT A0 BY ");
4422 
      OUTS (outf, imm6 (immag));
4423 
    }
4424 
  else if (sop == 1 && sopcde == 1 && bit8 == 0)
4425 
    {
4426 
      OUTS (outf, dregs (dst0));
4427 
      OUTS (outf, " = ");
4428 
      OUTS (outf, dregs (src1));
4429 
      OUTS (outf, " << ");
4430 
      OUTS (outf, uimm5 (immag));
4431 
      OUTS (outf, " (V, S)");
4432 
    }
4433 
  else if (sop == 1 && sopcde == 1 && bit8 == 1)
4434 
    {
4435 
      OUTS (outf, dregs (dst0));
4436 
      OUTS (outf, " = ");
4437 
      OUTS (outf, dregs (src1));
4438 
      OUTS (outf, " >>> ");
4439 
      OUTS (outf, imm5 (-immag));
4440 
      OUTS (outf, " (V)");
4441 
    }
4442 
  else if (sop == 2 && sopcde == 1 && bit8 == 1)
4443 
    {
4444 
      OUTS (outf, dregs (dst0));
4445 
      OUTS (outf, " = ");
4446 
      OUTS (outf, dregs (src1));
4447 
      OUTS (outf, " >> ");
4448 
      OUTS (outf, uimm5 (newimmag));
4449 
      OUTS (outf, " (V)");
4450 
    }
4451 
  else if (sop == 2 && sopcde == 1 && bit8 == 0)
4452 
    {
4453 
      OUTS (outf, dregs (dst0));
4454 
      OUTS (outf, " = ");
4455 
      OUTS (outf, dregs (src1));
4456 
      OUTS (outf, " << ");
4457 
      OUTS (outf, imm5 (immag));
4458 
      OUTS (outf, " (V)");
4459 
    }
4460 
  else if (sop == 0 && sopcde == 1)
4461 
    {
4462 
      OUTS (outf, dregs (dst0));
4463 
      OUTS (outf, " = ");
4464 
      OUTS (outf, dregs (src1));
4465 
      OUTS (outf, " >>> ");
4466 
      OUTS (outf, uimm5 (newimmag));
4467 
      OUTS (outf, " (V)");
4468 
    }
4469 
  else if (sop == 1 && sopcde == 2)
4470 
    {
4471 
      OUTS (outf, dregs (dst0));
4472 
      OUTS (outf, " = ");
4473 
      OUTS (outf, dregs (src1));
4474 
      OUTS (outf, " << ");
4475 
      OUTS (outf, uimm5 (immag));
4476 
      OUTS (outf, " (S)");
4477 
    }
4478 
  else if (sop == 2 && sopcde == 2 && bit8 == 1)
4479 
    {
4480 
      OUTS (outf, dregs (dst0));
4481 
      OUTS (outf, " = ");
4482 
      OUTS (outf, dregs (src1));
4483 
      OUTS (outf, " >> ");
4484 
      OUTS (outf, uimm5 (newimmag));
4485 
    }
4486 
  else if (sop == 2 && sopcde == 2 && bit8 == 0)
4487 
    {
4488 
      OUTS (outf, dregs (dst0));
4489 
      OUTS (outf, " = ");
4490 
      OUTS (outf, dregs (src1));
4491 
      OUTS (outf, " << ");
4492 
      OUTS (outf, uimm5 (immag));
4493 
    }
4494 
  else if (sop == 3 && sopcde == 2)
4495 
    {
4496 
      OUTS (outf, dregs (dst0));
4497 
      OUTS (outf, " = ROT ");
4498 
      OUTS (outf, dregs (src1));
4499 
      OUTS (outf, " BY ");
4500 
      OUTS (outf, imm6 (immag));
4501 
    }
4502 
  else if (sop == 0 && sopcde == 2)
4503 
    {
4504 
      OUTS (outf, dregs (dst0));
4505 
      OUTS (outf, " = ");
4506 
      OUTS (outf, dregs (src1));
4507 
      OUTS (outf, " >>> ");
4508 
      OUTS (outf, uimm5 (newimmag));
4509 
    }
4510 
  else
4511 
    return 0;
4512 
 
4513 
  return 4;
4514 
}
4515 
 
4516 
static int
4517 
decode_pseudoDEBUG_0 (TIword iw0, disassemble_info *outf)
4518 
{
4519 
  /* pseudoDEBUG
4520 
     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
4521 
     | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 0 |.fn....|.grp.......|.reg.......|
4522 
     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+  */
4523 
  int fn  = ((iw0 >> PseudoDbg_fn_bits) & PseudoDbg_fn_mask);
4524 
  int grp = ((iw0 >> PseudoDbg_grp_bits) & PseudoDbg_grp_mask);
4525 
  int reg = ((iw0 >> PseudoDbg_reg_bits) & PseudoDbg_reg_mask);
4526 
 
4527 
  if (reg == 0 && fn == 3)
4528 
    OUTS (outf, "DBG A0");
4529 
 
4530 
  else if (reg == 1 && fn == 3)
4531 
    OUTS (outf, "DBG A1");
4532 
 
4533 
  else if (reg == 3 && fn == 3)
4534 
    OUTS (outf, "ABORT");
4535 
 
4536 
  else if (reg == 4 && fn == 3)
4537 
    OUTS (outf, "HLT");
4538 
 
4539 
  else if (reg == 5 && fn == 3)
4540 
    OUTS (outf, "DBGHALT");
4541 
 
4542 
  else if (reg == 6 && fn == 3)
4543 
    {
4544 
      OUTS (outf, "DBGCMPLX (");
4545 
      OUTS (outf, dregs (grp));
4546 
      OUTS (outf, ")");
4547 
    }
4548 
  else if (reg == 7 && fn == 3)
4549 
    OUTS (outf, "DBG");
4550 
 
4551 
  else if (grp == 0 && fn == 2)
4552 
    {
4553 
      OUTS (outf, "OUTC");
4554 
      OUTS (outf, dregs (reg));
4555 
    }
4556 
  else if (fn == 0)
4557 
    {
4558 
      OUTS (outf, "DBG");
4559 
      OUTS (outf, allregs (reg, grp));
4560 
    }
4561 
  else if (fn == 1)
4562 
    {
4563 
      OUTS (outf, "PRNT");
4564 
      OUTS (outf, allregs (reg, grp));
4565 
    }
4566 
  else
4567 
    return 0;
4568 
 
4569 
  return 2;
4570 
}
4571 
 
4572 
static int
4573 
decode_pseudodbg_assert_0 (TIword iw0, TIword iw1, disassemble_info *outf)
4574 
{
4575 
  /* pseudodbg_assert
4576 
     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
4577 
     | 1 | 1 | 1 | 1 | 0 | - | - | - | dbgop |.grp.......|.regtest...|
4578 
     |.expected......................................................|
4579 
     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+  */
4580 
  int expected = ((iw1 >> PseudoDbg_Assert_expected_bits) & PseudoDbg_Assert_expected_mask);
4581 
  int dbgop    = ((iw0 >> (PseudoDbg_Assert_dbgop_bits - 16)) & PseudoDbg_Assert_dbgop_mask);
4582 
  int grp      = ((iw0 >> (PseudoDbg_Assert_grp_bits - 16)) & PseudoDbg_Assert_grp_mask);
4583 
  int regtest  = ((iw0 >> (PseudoDbg_Assert_regtest_bits - 16)) & PseudoDbg_Assert_regtest_mask);
4584 
 
4585 
  if (dbgop == 0)
4586 
    {
4587 
      OUTS (outf, "DBGA (");
4588 
      OUTS (outf, regs_lo (regtest, grp));
4589 
      OUTS (outf, ", ");
4590 
      OUTS (outf, uimm16 (expected));
4591 
      OUTS (outf, ")");
4592 
    }
4593 
  else if (dbgop == 1)
4594 
    {
4595 
      OUTS (outf, "DBGA (");
4596 
      OUTS (outf, regs_hi (regtest, grp));
4597 
      OUTS (outf, ", ");
4598 
      OUTS (outf, uimm16 (expected));
4599 
      OUTS (outf, ")");
4600 
    }
4601 
  else if (dbgop == 2)
4602 
    {
4603 
      OUTS (outf, "DBGAL (");
4604 
      OUTS (outf, allregs (regtest, grp));
4605 
      OUTS (outf, ", ");
4606 
      OUTS (outf, uimm16 (expected));
4607 
      OUTS (outf, ")");
4608 
    }
4609 
  else if (dbgop == 3)
4610 
    {
4611 
      OUTS (outf, "DBGAH (");
4612 
      OUTS (outf, allregs (regtest, grp));
4613 
      OUTS (outf, ", ");
4614 
      OUTS (outf, uimm16 (expected));
4615 
      OUTS (outf, ")");
4616 
    }
4617 
  else
4618 
    return 0;
4619 
  return 4;
4620 
}
4621 
 
4622 
static int
4623 
_print_insn_bfin (bfd_vma pc, disassemble_info *outf)
4624 
{
4625 
  bfd_byte buf[4];
4626 
  TIword iw0;
4627 
  TIword iw1;
4628 
  int status;
4629 
  int rv = 0;
4630 
 
4631 
  status = (*outf->read_memory_func) (pc & ~0x1, buf, 2, outf);
4632 
  /* FIXME */
4633 
  (void) status;
4634 
  status = (*outf->read_memory_func) ((pc + 2) & ~0x1, buf + 2, 2, outf);
4635 
  /* FIXME */
4636 
  (void) status;
4637 
 
4638 
  iw0 = bfd_getl16 (buf);
4639 
  iw1 = bfd_getl16 (buf + 2);
4640 
 
4641 
  if ((iw0 & 0xf7ff) == 0xc003 && iw1 == 0x1800)
4642 
    {
4643 
      OUTS (outf, "MNOP");
4644 
      return 4;
4645 
    }
4646 
  else if ((iw0 & 0xff00) == 0x0000)
4647 
    rv = decode_ProgCtrl_0 (iw0, outf);
4648 
  else if ((iw0 & 0xffc0) == 0x0240)
4649 
    rv = decode_CaCTRL_0 (iw0, outf);
4650 
  else if ((iw0 & 0xff80) == 0x0100)
4651 
    rv = decode_PushPopReg_0 (iw0, outf);
4652 
  else if ((iw0 & 0xfe00) == 0x0400)
4653 
    rv = decode_PushPopMultiple_0 (iw0, outf);
4654 
  else if ((iw0 & 0xfe00) == 0x0600)
4655 
    rv = decode_ccMV_0 (iw0, outf);
4656 
  else if ((iw0 & 0xf800) == 0x0800)
4657 
    rv = decode_CCflag_0 (iw0, outf);
4658 
  else if ((iw0 & 0xffe0) == 0x0200)
4659 
    rv = decode_CC2dreg_0 (iw0, outf);
4660 
  else if ((iw0 & 0xff00) == 0x0300)
4661 
    rv = decode_CC2stat_0 (iw0, outf);
4662 
  else if ((iw0 & 0xf000) == 0x1000)
4663 
    rv = decode_BRCC_0 (iw0, pc, outf);
4664 
  else if ((iw0 & 0xf000) == 0x2000)
4665 
    rv = decode_UJUMP_0 (iw0, pc, outf);
4666 
  else if ((iw0 & 0xf000) == 0x3000)
4667 
    rv = decode_REGMV_0 (iw0, outf);
4668 
  else if ((iw0 & 0xfc00) == 0x4000)
4669 
    rv = decode_ALU2op_0 (iw0, outf);
4670 
  else if ((iw0 & 0xfe00) == 0x4400)
4671 
    rv = decode_PTR2op_0 (iw0, outf);
4672 
  else if ((iw0 & 0xf800) == 0x4800)
4673 
    rv = decode_LOGI2op_0 (iw0, outf);
4674 
  else if ((iw0 & 0xf000) == 0x5000)
4675 
    rv = decode_COMP3op_0 (iw0, outf);
4676 
  else if ((iw0 & 0xf800) == 0x6000)
4677 
    rv = decode_COMPI2opD_0 (iw0, outf);
4678 
  else if ((iw0 & 0xf800) == 0x6800)
4679 
    rv = decode_COMPI2opP_0 (iw0, outf);
4680 
  else if ((iw0 & 0xf000) == 0x8000)
4681 
    rv = decode_LDSTpmod_0 (iw0, outf);
4682 
  else if ((iw0 & 0xff60) == 0x9e60)
4683 
    rv = decode_dagMODim_0 (iw0, outf);
4684 
  else if ((iw0 & 0xfff0) == 0x9f60)
4685 
    rv = decode_dagMODik_0 (iw0, outf);
4686 
  else if ((iw0 & 0xfc00) == 0x9c00)
4687 
    rv = decode_dspLDST_0 (iw0, outf);
4688 
  else if ((iw0 & 0xf000) == 0x9000)
4689 
    rv = decode_LDST_0 (iw0, outf);
4690 
  else if ((iw0 & 0xfc00) == 0xb800)
4691 
    rv = decode_LDSTiiFP_0 (iw0, outf);
4692 
  else if ((iw0 & 0xe000) == 0xA000)
4693 
    rv = decode_LDSTii_0 (iw0, outf);
4694 
  else if ((iw0 & 0xff80) == 0xe080 && (iw1 & 0x0C00) == 0x0000)
4695 
    rv = decode_LoopSetup_0 (iw0, iw1, pc, outf);
4696 
  else if ((iw0 & 0xff00) == 0xe100 && (iw1 & 0x0000) == 0x0000)
4697 
    rv = decode_LDIMMhalf_0 (iw0, iw1, outf);
4698 
  else if ((iw0 & 0xfe00) == 0xe200 && (iw1 & 0x0000) == 0x0000)
4699 
    rv = decode_CALLa_0 (iw0, iw1, pc, outf);
4700 
  else if ((iw0 & 0xfc00) == 0xe400 && (iw1 & 0x0000) == 0x0000)
4701 
    rv = decode_LDSTidxI_0 (iw0, iw1, outf);
4702 
  else if ((iw0 & 0xfffe) == 0xe800 && (iw1 & 0x0000) == 0x0000)
4703 
    rv = decode_linkage_0 (iw0, iw1, outf);
4704 
  else if ((iw0 & 0xf600) == 0xc000 && (iw1 & 0x0000) == 0x0000)
4705 
    rv = decode_dsp32mac_0 (iw0, iw1, outf);
4706 
  else if ((iw0 & 0xf600) == 0xc200 && (iw1 & 0x0000) == 0x0000)
4707 
    rv = decode_dsp32mult_0 (iw0, iw1, outf);
4708 
  else if ((iw0 & 0xf7c0) == 0xc400 && (iw1 & 0x0000) == 0x0000)
4709 
    rv = decode_dsp32alu_0 (iw0, iw1, outf);
4710 
  else if ((iw0 & 0xf780) == 0xc600 && (iw1 & 0x01c0) == 0x0000)
4711 
    rv = decode_dsp32shift_0 (iw0, iw1, outf);
4712 
  else if ((iw0 & 0xf780) == 0xc680 && (iw1 & 0x0000) == 0x0000)
4713 
    rv = decode_dsp32shiftimm_0 (iw0, iw1, outf);
4714 
  else if ((iw0 & 0xff00) == 0xf800)
4715 
    rv = decode_pseudoDEBUG_0 (iw0, outf);
4716 
#if 0
4717 
  else if ((iw0 & 0xFF00) == 0xF900)
4718 
    rv = decode_pseudoOChar_0 (iw0, iw1, pc, outf);
4719 
#endif
4720 
  else if ((iw0 & 0xFF00) == 0xf000 && (iw1 & 0x0000) == 0x0000)
4721 
    rv = decode_pseudodbg_assert_0 (iw0, iw1, outf);
4722 
 
4723 
  return rv;
4724 
}
4725 
 
4726 
 
4727 
int
4728 
print_insn_bfin (bfd_vma pc, disassemble_info *outf)
4729 
{
4730 
  bfd_byte buf[2];
4731 
  unsigned short iw0;
4732 
  int status;
4733 
  int count = 0;
4734 
 
4735 
  status = (*outf->read_memory_func) (pc & ~0x01, buf, 2, outf);
4736 
  /* FIXME */
4737 
  (void) status;
4738 
  iw0 = bfd_getl16 (buf);
4739 
 
4740 
  count += _print_insn_bfin (pc, outf);
4741 
 
4742 
  /* Proper display of multiple issue instructions.  */
4743 
 
4744 
  if ((iw0 & 0xc000) == 0xc000 && (iw0 & BIT_MULTI_INS)
4745 
      && ((iw0 & 0xe800) != 0xe800 /* Not Linkage.  */ ))
4746 
    {
4747 
      parallel = 1;
4748 
      outf->fprintf_func (outf->stream, " || ");
4749 
      count += _print_insn_bfin (pc + 4, outf);
4750 
      outf->fprintf_func (outf->stream, " || ");
4751 
      count += _print_insn_bfin (pc + 6, outf);
4752 
      parallel = 0;
4753 
    }
4754 
  if (count == 0)
4755 
    {
4756 
      outf->fprintf_func (outf->stream, "ILLEGAL");
4757 
      return 2;
4758 
    }
4759 
  if (!comment)
4760 
    outf->fprintf_func (outf->stream, ";");
4761 
 
4762 
  comment = 0;
4763 
 
4764 
  return count;
4765 
}

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