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[/] [openrisc/] [trunk/] [gnu-stable/] [gdb-7.2/] [opcodes/] [iq2000-desc.h] - Blame information for rev 841

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1 330 jeremybenn
/* CPU data header for iq2000.
2
 
3
THIS FILE IS MACHINE GENERATED WITH CGEN.
4
 
5
Copyright 1996-2010 Free Software Foundation, Inc.
6
 
7
This file is part of the GNU Binutils and/or GDB, the GNU debugger.
8
 
9
   This file is free software; you can redistribute it and/or modify
10
   it under the terms of the GNU General Public License as published by
11
   the Free Software Foundation; either version 3, or (at your option)
12
   any later version.
13
 
14
   It is distributed in the hope that it will be useful, but WITHOUT
15
   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
16
   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
17
   License for more details.
18
 
19
   You should have received a copy of the GNU General Public License along
20
   with this program; if not, write to the Free Software Foundation, Inc.,
21
   51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
22
 
23
*/
24
 
25
#ifndef IQ2000_CPU_H
26
#define IQ2000_CPU_H
27
 
28
#define CGEN_ARCH iq2000
29
 
30
/* Given symbol S, return iq2000_cgen_<S>.  */
31
#define CGEN_SYM(s) iq2000##_cgen_##s
32
 
33
 
34
/* Selected cpu families.  */
35
#define HAVE_CPU_IQ2000BF
36
#define HAVE_CPU_IQ10BF
37
 
38
#define CGEN_INSN_LSB0_P 1
39
 
40
/* Minimum size of any insn (in bytes).  */
41
#define CGEN_MIN_INSN_SIZE 4
42
 
43
/* Maximum size of any insn (in bytes).  */
44
#define CGEN_MAX_INSN_SIZE 4
45
 
46
#define CGEN_INT_INSN_P 1
47
 
48
/* Maximum number of syntax elements in an instruction.  */
49
#define CGEN_ACTUAL_MAX_SYNTAX_ELEMENTS 19
50
 
51
/* CGEN_MNEMONIC_OPERANDS is defined if mnemonics have operands.
52
   e.g. In "b,a foo" the ",a" is an operand.  If mnemonics have operands
53
   we can't hash on everything up to the space.  */
54
#define CGEN_MNEMONIC_OPERANDS
55
 
56
/* Maximum number of fields in an instruction.  */
57
#define CGEN_ACTUAL_MAX_IFMT_OPERANDS 8
58
 
59
/* Enums.  */
60
 
61
/* Enum declaration for .  */
62
typedef enum gr_names {
63
  H_GR_R0 = 0, H_GR__0 = 0, H_GR_R1 = 1, H_GR__1 = 1
64
 , H_GR_R2 = 2, H_GR__2 = 2, H_GR_R3 = 3, H_GR__3 = 3
65
 , H_GR_R4 = 4, H_GR__4 = 4, H_GR_R5 = 5, H_GR__5 = 5
66
 , H_GR_R6 = 6, H_GR__6 = 6, H_GR_R7 = 7, H_GR__7 = 7
67
 , H_GR_R8 = 8, H_GR__8 = 8, H_GR_R9 = 9, H_GR__9 = 9
68
 , H_GR_R10 = 10, H_GR__10 = 10, H_GR_R11 = 11, H_GR__11 = 11
69
 , H_GR_R12 = 12, H_GR__12 = 12, H_GR_R13 = 13, H_GR__13 = 13
70
 , H_GR_R14 = 14, H_GR__14 = 14, H_GR_R15 = 15, H_GR__15 = 15
71
 , H_GR_R16 = 16, H_GR__16 = 16, H_GR_R17 = 17, H_GR__17 = 17
72
 , H_GR_R18 = 18, H_GR__18 = 18, H_GR_R19 = 19, H_GR__19 = 19
73
 , H_GR_R20 = 20, H_GR__20 = 20, H_GR_R21 = 21, H_GR__21 = 21
74
 , H_GR_R22 = 22, H_GR__22 = 22, H_GR_R23 = 23, H_GR__23 = 23
75
 , H_GR_R24 = 24, H_GR__24 = 24, H_GR_R25 = 25, H_GR__25 = 25
76
 , H_GR_R26 = 26, H_GR__26 = 26, H_GR_R27 = 27, H_GR__27 = 27
77
 , H_GR_R28 = 28, H_GR__28 = 28, H_GR_R29 = 29, H_GR__29 = 29
78
 , H_GR_R30 = 30, H_GR__30 = 30, H_GR_R31 = 31, H_GR__31 = 31
79
} GR_NAMES;
80
 
81
/* Enum declaration for primary opcodes.  */
82
typedef enum opcodes {
83
  OP_SPECIAL = 0, OP_REGIMM = 1, OP_J = 2, OP_JAL = 3
84
 , OP_BEQ = 4, OP_BNE = 5, OP_BLEZ = 6, OP_BGTZ = 7
85
 , OP_ADDI = 8, OP_ADDIU = 9, OP_SLTI = 10, OP_SLTIU = 11
86
 , OP_ANDI = 12, OP_ORI = 13, OP_XORI = 14, OP_LUI = 15
87
 , OP_COP0 = 16, OP_COP1 = 17, OP_COP2 = 18, OP_COP3 = 19
88
 , OP_BEQL = 20, OP_BNEL = 21, OP_BLEZL = 22, OP_BGTZL = 23
89
 , OP_BMB0 = 24, OP_BMB1 = 25, OP_BMB2 = 26, OP_BMB3 = 27
90
 , OP_BBI = 28, OP_BBV = 29, OP_BBIN = 30, OP_BBVN = 31
91
 , OP_LB = 32, OP_LH = 33, OP_LW = 35, OP_LBU = 36
92
 , OP_LHU = 37, OP_RAM = 39, OP_SB = 40, OP_SH = 41
93
 , OP_SW = 43, OP_ANDOI = 44, OP_BMB = 45, OP_ORUI = 47
94
 , OP_LDW = 48, OP_SDW = 56, OP_ANDOUI = 63
95
} OPCODES;
96
 
97
/* Enum declaration for iq10-only primary opcodes.  */
98
typedef enum q10_opcodes {
99
  OP10_BMB = 6, OP10_ORUI = 15, OP10_BMBL = 22, OP10_ANDOUI = 47
100
 , OP10_BBIL = 60, OP10_BBVL = 61, OP10_BBINL = 62, OP10_BBVNL = 63
101
} Q10_OPCODES;
102
 
103
/* Enum declaration for branch sub-opcodes.  */
104
typedef enum regimm_functions {
105
  FUNC_BLTZ = 0, FUNC_BGEZ = 1, FUNC_BLTZL = 2, FUNC_BGEZL = 3
106
 , FUNC_BLEZ = 4, FUNC_BGTZ = 5, FUNC_BLEZL = 6, FUNC_BGTZL = 7
107
 , FUNC_BRI = 8, FUNC_BRV = 9, FUNC_BCTX = 12, FUNC_BLTZAL = 16
108
 , FUNC_BGEZAL = 17, FUNC_BLTZALL = 18, FUNC_BGEZALL = 19, FUNC_BLEZAL = 20
109
 , FUNC_BGTZAL = 21, FUNC_BLEZALL = 22, FUNC_BGTZALL = 23
110
} REGIMM_FUNCTIONS;
111
 
112
/* Enum declaration for function sub-opcodes.  */
113
typedef enum functions {
114
  FUNC_SLL = 0, FUNC_SLMV = 1, FUNC_SRL = 2, FUNC_SRA = 3
115
 , FUNC_SLLV = 4, FUNC_SRMV = 5, FUNC_SRLV = 6, FUNC_SRAV = 7
116
 , FUNC_JR = 8, FUNC_JALR = 9, FUNC_JCR = 10, FUNC_SYSCALL = 12
117
 , FUNC_BREAK = 13, FUNC_SLEEP = 14, FUNC_ADD = 32, FUNC_ADDU = 33
118
 , FUNC_SUB = 34, FUNC_SUBU = 35, FUNC_AND = 36, FUNC_OR = 37
119
 , FUNC_XOR = 38, FUNC_NOR = 39, FUNC_ADO16 = 41, FUNC_SLT = 42
120
 , FUNC_SLTU = 43, FUNC_MRGB = 45
121
} FUNCTIONS;
122
 
123
/* Enum declaration for iq10-only special function sub-opcodes.  */
124
typedef enum q10s_functions {
125
  FUNC10_YIELD = 14, FUNC10_CNT1S = 46
126
} Q10S_FUNCTIONS;
127
 
128
/* Enum declaration for iq10 function sub-opcodes.  */
129
typedef enum cop_functions {
130
  FUNC10_CFC = 0, FUNC10_LOCK = 1, FUNC10_CTC = 2, FUNC10_UNLK = 3
131
 , FUNC10_SWRD = 4, FUNC10_SWRDL = 5, FUNC10_SWWR = 6, FUNC10_SWWRU = 7
132
 , FUNC10_RBA = 8, FUNC10_RBAL = 9, FUNC10_RBAR = 10, FUNC10_DWRD = 12
133
 , FUNC10_DWRDL = 13, FUNC10_WBA = 16, FUNC10_WBAU = 17, FUNC10_WBAC = 18
134
 , FUNC10_CRC32 = 20, FUNC10_CRC32B = 21, FUNC10_MCID = 32, FUNC10_DBD = 33
135
 , FUNC10_DBA = 34, FUNC10_DPWT = 35, FUNC10_AVAIL = 36, FUNC10_FREE = 37
136
 , FUNC10_CHKHDR = 38, FUNC10_TSTOD = 39, FUNC10_PKRLA = 40, FUNC10_PKRLAU = 41
137
 , FUNC10_PKRLAH = 42, FUNC10_PKRLAC = 43, FUNC10_CMPHDR = 44, FUNC10_CM64RS = 0
138
 , FUNC10_CM64RD = 1, FUNC10_CM64RI = 4, FUNC10_CM64CLR = 5, FUNC10_CM64SS = 8
139
 , FUNC10_CM64SD = 9, FUNC10_CM64SI = 12, FUNC10_CM64RA = 16, FUNC10_CM64RIA2 = 20
140
 , FUNC10_CM128RIA2 = 21, FUNC10_CM64SA = 24, FUNC10_CM64SIA2 = 28, FUNC10_CM128SIA2 = 29
141
 , FUNC10_CM32RS = 32, FUNC10_CM32RD = 33, FUNC10_CM32XOR = 34, FUNC10_CM32ANDN = 35
142
 , FUNC10_CM32RI = 36, FUNC10_CM128VSA = 38, FUNC10_CM32SS = 40, FUNC10_CM32SD = 41
143
 , FUNC10_CM32OR = 42, FUNC10_CM32AND = 43, FUNC10_CM32SI = 44, FUNC10_CM32RA = 48
144
 , FUNC10_CM32SA = 56
145
} COP_FUNCTIONS;
146
 
147
/* Enum declaration for iq10 function sub-opcodes.  */
148
typedef enum cop_cm128_4functions {
149
  FUNC10_CM128RIA3 = 4, FUNC10_CM128SIA3 = 6
150
} COP_CM128_4FUNCTIONS;
151
 
152
/* Enum declaration for iq10 function sub-opcodes.  */
153
typedef enum cop_cm128_3functions {
154
  FUNC10_CM128RIA4 = 6, FUNC10_CM128SIA4 = 7
155
} COP_CM128_3FUNCTIONS;
156
 
157
/* Enum declaration for iq10 coprocessor sub-opcodes.  */
158
typedef enum cop2_functions {
159
  FUNC10_PKRLI = 0, FUNC10_PKRLIU = 1, FUNC10_PKRLIH = 2, FUNC10_PKRLIC = 3
160
 , FUNC10_RBIR = 1, FUNC10_RBI = 2, FUNC10_RBIL = 3, FUNC10_WBIC = 5
161
 , FUNC10_WBI = 6, FUNC10_WBIU = 7
162
} COP2_FUNCTIONS;
163
 
164
/* Enum declaration for iq10 coprocessor cam sub-opcodes.  */
165
typedef enum cop3_cam_functions {
166
  FUNC10_CAM36 = 16, FUNC10_CAM72 = 17, FUNC10_CAM144 = 18, FUNC10_CAM288 = 19
167
} COP3_CAM_FUNCTIONS;
168
 
169
/* Attributes.  */
170
 
171
/* Enum declaration for machine type selection.  */
172
typedef enum mach_attr {
173
  MACH_BASE, MACH_IQ2000, MACH_IQ10, MACH_MAX
174
} MACH_ATTR;
175
 
176
/* Enum declaration for instruction set selection.  */
177
typedef enum isa_attr {
178
  ISA_IQ2000, ISA_MAX
179
} ISA_ATTR;
180
 
181
/* Number of architecture variants.  */
182
#define MAX_ISAS  1
183
#define MAX_MACHS ((int) MACH_MAX)
184
 
185
/* Ifield support.  */
186
 
187
/* Ifield attribute indices.  */
188
 
189
/* Enum declaration for cgen_ifld attrs.  */
190
typedef enum cgen_ifld_attr {
191
  CGEN_IFLD_VIRTUAL, CGEN_IFLD_PCREL_ADDR, CGEN_IFLD_ABS_ADDR, CGEN_IFLD_RESERVED
192
 , CGEN_IFLD_SIGN_OPT, CGEN_IFLD_SIGNED, CGEN_IFLD_END_BOOLS, CGEN_IFLD_START_NBOOLS = 31
193
 , CGEN_IFLD_MACH, CGEN_IFLD_END_NBOOLS
194
} CGEN_IFLD_ATTR;
195
 
196
/* Number of non-boolean elements in cgen_ifld_attr.  */
197
#define CGEN_IFLD_NBOOL_ATTRS (CGEN_IFLD_END_NBOOLS - CGEN_IFLD_START_NBOOLS - 1)
198
 
199
/* cgen_ifld attribute accessor macros.  */
200
#define CGEN_ATTR_CGEN_IFLD_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_IFLD_MACH-CGEN_IFLD_START_NBOOLS-1].nonbitset)
201
#define CGEN_ATTR_CGEN_IFLD_VIRTUAL_VALUE(attrs) (((attrs)->bool & (1 << CGEN_IFLD_VIRTUAL)) != 0)
202
#define CGEN_ATTR_CGEN_IFLD_PCREL_ADDR_VALUE(attrs) (((attrs)->bool & (1 << CGEN_IFLD_PCREL_ADDR)) != 0)
203
#define CGEN_ATTR_CGEN_IFLD_ABS_ADDR_VALUE(attrs) (((attrs)->bool & (1 << CGEN_IFLD_ABS_ADDR)) != 0)
204
#define CGEN_ATTR_CGEN_IFLD_RESERVED_VALUE(attrs) (((attrs)->bool & (1 << CGEN_IFLD_RESERVED)) != 0)
205
#define CGEN_ATTR_CGEN_IFLD_SIGN_OPT_VALUE(attrs) (((attrs)->bool & (1 << CGEN_IFLD_SIGN_OPT)) != 0)
206
#define CGEN_ATTR_CGEN_IFLD_SIGNED_VALUE(attrs) (((attrs)->bool & (1 << CGEN_IFLD_SIGNED)) != 0)
207
 
208
/* Enum declaration for iq2000 ifield types.  */
209
typedef enum ifield_type {
210
  IQ2000_F_NIL, IQ2000_F_ANYOF, IQ2000_F_OPCODE, IQ2000_F_RS
211
 , IQ2000_F_RT, IQ2000_F_RD, IQ2000_F_SHAMT, IQ2000_F_CP_OP
212
 , IQ2000_F_CP_OP_10, IQ2000_F_CP_GRP, IQ2000_F_FUNC, IQ2000_F_IMM
213
 , IQ2000_F_RD_RS, IQ2000_F_RD_RT, IQ2000_F_RT_RS, IQ2000_F_JTARG
214
 , IQ2000_F_JTARGQ10, IQ2000_F_OFFSET, IQ2000_F_COUNT, IQ2000_F_BYTECOUNT
215
 , IQ2000_F_INDEX, IQ2000_F_MASK, IQ2000_F_MASKQ10, IQ2000_F_MASKL
216
 , IQ2000_F_EXCODE, IQ2000_F_RSRVD, IQ2000_F_10_11, IQ2000_F_24_19
217
 , IQ2000_F_5, IQ2000_F_10, IQ2000_F_25, IQ2000_F_CAM_Z
218
 , IQ2000_F_CAM_Y, IQ2000_F_CM_3FUNC, IQ2000_F_CM_4FUNC, IQ2000_F_CM_3Z
219
 , IQ2000_F_CM_4Z, IQ2000_F_MAX
220
} IFIELD_TYPE;
221
 
222
#define MAX_IFLD ((int) IQ2000_F_MAX)
223
 
224
/* Hardware attribute indices.  */
225
 
226
/* Enum declaration for cgen_hw attrs.  */
227
typedef enum cgen_hw_attr {
228
  CGEN_HW_VIRTUAL, CGEN_HW_CACHE_ADDR, CGEN_HW_PC, CGEN_HW_PROFILE
229
 , CGEN_HW_END_BOOLS, CGEN_HW_START_NBOOLS = 31, CGEN_HW_MACH, CGEN_HW_END_NBOOLS
230
} CGEN_HW_ATTR;
231
 
232
/* Number of non-boolean elements in cgen_hw_attr.  */
233
#define CGEN_HW_NBOOL_ATTRS (CGEN_HW_END_NBOOLS - CGEN_HW_START_NBOOLS - 1)
234
 
235
/* cgen_hw attribute accessor macros.  */
236
#define CGEN_ATTR_CGEN_HW_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_HW_MACH-CGEN_HW_START_NBOOLS-1].nonbitset)
237
#define CGEN_ATTR_CGEN_HW_VIRTUAL_VALUE(attrs) (((attrs)->bool & (1 << CGEN_HW_VIRTUAL)) != 0)
238
#define CGEN_ATTR_CGEN_HW_CACHE_ADDR_VALUE(attrs) (((attrs)->bool & (1 << CGEN_HW_CACHE_ADDR)) != 0)
239
#define CGEN_ATTR_CGEN_HW_PC_VALUE(attrs) (((attrs)->bool & (1 << CGEN_HW_PC)) != 0)
240
#define CGEN_ATTR_CGEN_HW_PROFILE_VALUE(attrs) (((attrs)->bool & (1 << CGEN_HW_PROFILE)) != 0)
241
 
242
/* Enum declaration for iq2000 hardware types.  */
243
typedef enum cgen_hw_type {
244
  HW_H_MEMORY, HW_H_SINT, HW_H_UINT, HW_H_ADDR
245
 , HW_H_IADDR, HW_H_PC, HW_H_GR, HW_MAX
246
} CGEN_HW_TYPE;
247
 
248
#define MAX_HW ((int) HW_MAX)
249
 
250
/* Operand attribute indices.  */
251
 
252
/* Enum declaration for cgen_operand attrs.  */
253
typedef enum cgen_operand_attr {
254
  CGEN_OPERAND_VIRTUAL, CGEN_OPERAND_PCREL_ADDR, CGEN_OPERAND_ABS_ADDR, CGEN_OPERAND_SIGN_OPT
255
 , CGEN_OPERAND_SIGNED, CGEN_OPERAND_NEGATIVE, CGEN_OPERAND_RELAX, CGEN_OPERAND_SEM_ONLY
256
 , CGEN_OPERAND_END_BOOLS, CGEN_OPERAND_START_NBOOLS = 31, CGEN_OPERAND_MACH, CGEN_OPERAND_END_NBOOLS
257
} CGEN_OPERAND_ATTR;
258
 
259
/* Number of non-boolean elements in cgen_operand_attr.  */
260
#define CGEN_OPERAND_NBOOL_ATTRS (CGEN_OPERAND_END_NBOOLS - CGEN_OPERAND_START_NBOOLS - 1)
261
 
262
/* cgen_operand attribute accessor macros.  */
263
#define CGEN_ATTR_CGEN_OPERAND_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_OPERAND_MACH-CGEN_OPERAND_START_NBOOLS-1].nonbitset)
264
#define CGEN_ATTR_CGEN_OPERAND_VIRTUAL_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_VIRTUAL)) != 0)
265
#define CGEN_ATTR_CGEN_OPERAND_PCREL_ADDR_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_PCREL_ADDR)) != 0)
266
#define CGEN_ATTR_CGEN_OPERAND_ABS_ADDR_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_ABS_ADDR)) != 0)
267
#define CGEN_ATTR_CGEN_OPERAND_SIGN_OPT_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_SIGN_OPT)) != 0)
268
#define CGEN_ATTR_CGEN_OPERAND_SIGNED_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_SIGNED)) != 0)
269
#define CGEN_ATTR_CGEN_OPERAND_NEGATIVE_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_NEGATIVE)) != 0)
270
#define CGEN_ATTR_CGEN_OPERAND_RELAX_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_RELAX)) != 0)
271
#define CGEN_ATTR_CGEN_OPERAND_SEM_ONLY_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_SEM_ONLY)) != 0)
272
 
273
/* Enum declaration for iq2000 operand types.  */
274
typedef enum cgen_operand_type {
275
  IQ2000_OPERAND_PC, IQ2000_OPERAND_RS, IQ2000_OPERAND_RT, IQ2000_OPERAND_RD
276
 , IQ2000_OPERAND_RD_RS, IQ2000_OPERAND_RD_RT, IQ2000_OPERAND_RT_RS, IQ2000_OPERAND_SHAMT
277
 , IQ2000_OPERAND_IMM, IQ2000_OPERAND_OFFSET, IQ2000_OPERAND_BASEOFF, IQ2000_OPERAND_JMPTARG
278
 , IQ2000_OPERAND_MASK, IQ2000_OPERAND_MASKQ10, IQ2000_OPERAND_MASKL, IQ2000_OPERAND_COUNT
279
 , IQ2000_OPERAND__INDEX, IQ2000_OPERAND_EXECODE, IQ2000_OPERAND_BYTECOUNT, IQ2000_OPERAND_CAM_Y
280
 , IQ2000_OPERAND_CAM_Z, IQ2000_OPERAND_CM_3FUNC, IQ2000_OPERAND_CM_4FUNC, IQ2000_OPERAND_CM_3Z
281
 , IQ2000_OPERAND_CM_4Z, IQ2000_OPERAND_BASE, IQ2000_OPERAND_MASKR, IQ2000_OPERAND_BITNUM
282
 , IQ2000_OPERAND_HI16, IQ2000_OPERAND_LO16, IQ2000_OPERAND_MLO16, IQ2000_OPERAND_JMPTARGQ10
283
 , IQ2000_OPERAND_MAX
284
} CGEN_OPERAND_TYPE;
285
 
286
/* Number of operands types.  */
287
#define MAX_OPERANDS 32
288
 
289
/* Maximum number of operands referenced by any insn.  */
290
#define MAX_OPERAND_INSTANCES 8
291
 
292
/* Insn attribute indices.  */
293
 
294
/* Enum declaration for cgen_insn attrs.  */
295
typedef enum cgen_insn_attr {
296
  CGEN_INSN_ALIAS, CGEN_INSN_VIRTUAL, CGEN_INSN_UNCOND_CTI, CGEN_INSN_COND_CTI
297
 , CGEN_INSN_SKIP_CTI, CGEN_INSN_DELAY_SLOT, CGEN_INSN_RELAXABLE, CGEN_INSN_RELAXED
298
 , CGEN_INSN_NO_DIS, CGEN_INSN_PBB, CGEN_INSN_YIELD_INSN, CGEN_INSN_LOAD_DELAY
299
 , CGEN_INSN_EVEN_REG_NUM, CGEN_INSN_UNSUPPORTED, CGEN_INSN_USES_RD, CGEN_INSN_USES_RS
300
 , CGEN_INSN_USES_RT, CGEN_INSN_USES_R31, CGEN_INSN_END_BOOLS, CGEN_INSN_START_NBOOLS = 31
301
 , CGEN_INSN_MACH, CGEN_INSN_END_NBOOLS
302
} CGEN_INSN_ATTR;
303
 
304
/* Number of non-boolean elements in cgen_insn_attr.  */
305
#define CGEN_INSN_NBOOL_ATTRS (CGEN_INSN_END_NBOOLS - CGEN_INSN_START_NBOOLS - 1)
306
 
307
/* cgen_insn attribute accessor macros.  */
308
#define CGEN_ATTR_CGEN_INSN_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_INSN_MACH-CGEN_INSN_START_NBOOLS-1].nonbitset)
309
#define CGEN_ATTR_CGEN_INSN_ALIAS_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_ALIAS)) != 0)
310
#define CGEN_ATTR_CGEN_INSN_VIRTUAL_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_VIRTUAL)) != 0)
311
#define CGEN_ATTR_CGEN_INSN_UNCOND_CTI_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_UNCOND_CTI)) != 0)
312
#define CGEN_ATTR_CGEN_INSN_COND_CTI_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_COND_CTI)) != 0)
313
#define CGEN_ATTR_CGEN_INSN_SKIP_CTI_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_SKIP_CTI)) != 0)
314
#define CGEN_ATTR_CGEN_INSN_DELAY_SLOT_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_DELAY_SLOT)) != 0)
315
#define CGEN_ATTR_CGEN_INSN_RELAXABLE_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_RELAXABLE)) != 0)
316
#define CGEN_ATTR_CGEN_INSN_RELAXED_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_RELAXED)) != 0)
317
#define CGEN_ATTR_CGEN_INSN_NO_DIS_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_NO_DIS)) != 0)
318
#define CGEN_ATTR_CGEN_INSN_PBB_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_PBB)) != 0)
319
#define CGEN_ATTR_CGEN_INSN_YIELD_INSN_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_YIELD_INSN)) != 0)
320
#define CGEN_ATTR_CGEN_INSN_LOAD_DELAY_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_LOAD_DELAY)) != 0)
321
#define CGEN_ATTR_CGEN_INSN_EVEN_REG_NUM_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_EVEN_REG_NUM)) != 0)
322
#define CGEN_ATTR_CGEN_INSN_UNSUPPORTED_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_UNSUPPORTED)) != 0)
323
#define CGEN_ATTR_CGEN_INSN_USES_RD_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_USES_RD)) != 0)
324
#define CGEN_ATTR_CGEN_INSN_USES_RS_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_USES_RS)) != 0)
325
#define CGEN_ATTR_CGEN_INSN_USES_RT_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_USES_RT)) != 0)
326
#define CGEN_ATTR_CGEN_INSN_USES_R31_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_USES_R31)) != 0)
327
 
328
/* cgen.h uses things we just defined.  */
329
#include "opcode/cgen.h"
330
 
331
extern const struct cgen_ifld iq2000_cgen_ifld_table[];
332
 
333
/* Attributes.  */
334
extern const CGEN_ATTR_TABLE iq2000_cgen_hardware_attr_table[];
335
extern const CGEN_ATTR_TABLE iq2000_cgen_ifield_attr_table[];
336
extern const CGEN_ATTR_TABLE iq2000_cgen_operand_attr_table[];
337
extern const CGEN_ATTR_TABLE iq2000_cgen_insn_attr_table[];
338
 
339
/* Hardware decls.  */
340
 
341
extern CGEN_KEYWORD iq2000_cgen_opval_gr_names;
342
 
343
extern const CGEN_HW_ENTRY iq2000_cgen_hw_table[];
344
 
345
 
346
 
347
#endif /* IQ2000_CPU_H */

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