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/* Disassembler interface for targets using CGEN. -*- C -*-

   CGEN: Cpu tools GENerator

   THIS FILE IS MACHINE GENERATED WITH CGEN.

   - the resultant file is machine generated, cgen-dis.in isn't

   Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2005, 2007,

   2008, 2010  Free Software Foundation, Inc.

   This file is part of libopcodes.

   This library is free software; you can redistribute it and/or modify

   it under the terms of the GNU General Public License as published by

   the Free Software Foundation; either version 3, or (at your option)

   any later version.

   It is distributed in the hope that it will be useful, but WITHOUT

   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY

   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public

   License for more details.

   You should have received a copy of the GNU General Public License

   along with this program; if not, write to the Free Software Foundation, Inc.,

   51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.  */

/* ??? Eventually more and more of this stuff can go to cpu-independent files.

   Keep that in mind.  */

#include "sysdep.h"

#include <stdio.h>

#include "ansidecl.h"

#include "dis-asm.h"

#include "bfd.h"

#include "symcat.h"

#include "libiberty.h"

#include "mep-desc.h"

#include "mep-opc.h"

#include "opintl.h"

/* Default text to print if an instruction isn't recognized.  */

#define UNKNOWN_INSN_MSG _("*unknown*")

static void print_normal

  (CGEN_CPU_DESC, void *, long, unsigned int, bfd_vma, int);

static void print_address

  (CGEN_CPU_DESC, void *, bfd_vma, unsigned int, bfd_vma, int) ATTRIBUTE_UNUSED;

static void print_keyword

  (CGEN_CPU_DESC, void *, CGEN_KEYWORD *, long, unsigned int) ATTRIBUTE_UNUSED;

static void print_insn_normal

  (CGEN_CPU_DESC, void *, const CGEN_INSN *, CGEN_FIELDS *, bfd_vma, int);

static int print_insn

  (CGEN_CPU_DESC, bfd_vma,  disassemble_info *, bfd_byte *, unsigned);

static int default_print_insn

  (CGEN_CPU_DESC, bfd_vma, disassemble_info *) ATTRIBUTE_UNUSED;

static int read_insn

  (CGEN_CPU_DESC, bfd_vma, disassemble_info *, bfd_byte *, int, CGEN_EXTRACT_INFO *,

   unsigned long *);

/* -- disassembler routines inserted here.  */

/* -- dis.c */

#include "elf/mep.h"

#include "elf-bfd.h"

#define CGEN_VALIDATE_INSN_SUPPORTED

static void print_tpreg (CGEN_CPU_DESC, PTR, CGEN_KEYWORD *, long, unsigned int);

static void print_spreg (CGEN_CPU_DESC, PTR, CGEN_KEYWORD *, long, unsigned int);

static void

print_tpreg (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, PTR dis_info,

             CGEN_KEYWORD *table ATTRIBUTE_UNUSED, long val ATTRIBUTE_UNUSED,

             unsigned int flags ATTRIBUTE_UNUSED)

{

  disassemble_info *info = (disassemble_info *) dis_info;

  (*info->fprintf_func) (info->stream, "$tp");

}

static void

print_spreg (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, PTR dis_info,

             CGEN_KEYWORD *table ATTRIBUTE_UNUSED, long val ATTRIBUTE_UNUSED,

             unsigned int flags ATTRIBUTE_UNUSED)

{

  disassemble_info *info = (disassemble_info *) dis_info;

  (*info->fprintf_func) (info->stream, "$sp");

}

/* begin-cop-ip-print-handlers */

static void

print_ivc2_cr (CGEN_CPU_DESC,

        void *,

        CGEN_KEYWORD *,

        long,

        unsigned int) ATTRIBUTE_UNUSED;

static void

print_ivc2_cr (CGEN_CPU_DESC cd,

        void *dis_info,

        CGEN_KEYWORD *keyword_table ATTRIBUTE_UNUSED,

        long value,

        unsigned int attrs)

{

  print_keyword (cd, dis_info, & mep_cgen_opval_h_cr_ivc2, value, attrs);

}

static void

print_ivc2_ccr (CGEN_CPU_DESC,

        void *,

        CGEN_KEYWORD *,

        long,

        unsigned int) ATTRIBUTE_UNUSED;

static void

print_ivc2_ccr (CGEN_CPU_DESC cd,

        void *dis_info,

        CGEN_KEYWORD *keyword_table ATTRIBUTE_UNUSED,

        long value,

        unsigned int attrs)

{

  print_keyword (cd, dis_info, & mep_cgen_opval_h_ccr_ivc2, value, attrs);

}

/* end-cop-ip-print-handlers */

/************************************************************\

*********************** Experimental *************************

\************************************************************/

#undef  CGEN_PRINT_INSN

#define CGEN_PRINT_INSN mep_print_insn

static int

mep_print_vliw_insns (CGEN_CPU_DESC cd, bfd_vma pc, disassemble_info *info,

                      bfd_byte *buf, int corelength, int copro1length,

                      int copro2length ATTRIBUTE_UNUSED)

{

  int i;

  int status = 0;

  /* char insnbuf[CGEN_MAX_INSN_SIZE]; */

  bfd_byte insnbuf[64];

  /* If corelength > 0 then there is a core insn present. It

     will be at the beginning of the buffer.  After printing

     the core insn, we need to print the + on the next line.  */

  if (corelength > 0)

    {

      int my_status = 0;

      for (i = 0; i < corelength; i++ )

        insnbuf[i] = buf[i];

      cd->isas = & MEP_CORE_ISA;

      my_status = print_insn (cd, pc, info, insnbuf, corelength);

      if (my_status != corelength)

        {

          (*info->fprintf_func) (info->stream, UNKNOWN_INSN_MSG);

          my_status = corelength;

        }

      status += my_status;

      /* Print the + to indicate that the following copro insn is   */

      /* part of a vliw group.                                      */

      if (copro1length > 0)

        (*info->fprintf_func) (info->stream, " + ");

    }

  /* Now all that is left to be processed is the coprocessor insns

     In vliw mode, there will always be one.  Its positioning will

     be from byte corelength to byte corelength+copro1length -1.

     No need to check for existence.   Also, the first vliw insn,

     will, as spec'd, always be at least as long as the core insn

     so we don't need to flush the buffer.  */

  if (copro1length > 0)

    {

      int my_status = 0;

      for (i = corelength; i < corelength + copro1length; i++ )

        insnbuf[i - corelength] = buf[i];

      switch (copro1length)

        {

        case 0:

          break;

        case 2:

          cd->isas = & MEP_COP16_ISA;

          break;

        case 4:

          cd->isas = & MEP_COP32_ISA;

          break;

        case 6:

          cd->isas = & MEP_COP48_ISA;

          break;

        case 8:

          cd->isas = & MEP_COP64_ISA;

          break;

        default:

          /* Shouldn't be anything but 16,32,48,64.  */

          break;

        }

      my_status = print_insn (cd, pc, info, insnbuf, copro1length);

      if (my_status != copro1length)

        {

          (*info->fprintf_func) (info->stream, UNKNOWN_INSN_MSG);

          my_status = copro1length;

        }

      status += my_status;

    }

#if 0

  /* Now we need to process the second copro insn if it exists. We

     have no guarantee that the second copro insn will be longer

     than the first, so we have to flush the buffer if we are have

     a second copro insn to process.  If present, this insn will

     be in the position from byte corelength+copro1length to byte

     corelength+copro1length+copro2length-1 (which better equal 8

     or else we're in big trouble.  */

  if (copro2length > 0)

    {

      int my_status = 0;

      for (i = 0; i < 64 ; i++)

        insnbuf[i] = 0;

      for (i = corelength + copro1length; i < 64; i++)

        insnbuf[i - (corelength + copro1length)] = buf[i];

      switch (copro2length)

        {

        case 2:

          cd->isas = 1 << ISA_EXT_COP1_16;

          break;

        case 4:

          cd->isas = 1 << ISA_EXT_COP1_32;

          break;

        case 6:

          cd->isas = 1 << ISA_EXT_COP1_48;

          break;

        case 8:

          cd->isas = 1 << ISA_EXT_COP1_64;

          break;

        default:

          /* Shouldn't be anything but 16,32,48,64.  */

          break;

        }

      my_status = print_insn (cd, pc, info, insnbuf, copro2length);

      if (my_status != copro2length)

        {

          (*info->fprintf_func) (info->stream, UNKNOWN_INSN_MSG);

          my_status = copro2length;

        }

      status += my_status;

    }

#endif

  /* Status should now be the number of bytes that were printed

     which should be 4 for VLIW32 mode and 64 for VLIW64 mode.  */

  if ((!MEP_VLIW64 && (status != 4)) || (MEP_VLIW64 && (status != 8)))

    return -1;

  else

    return status;

}

/* The two functions mep_examine_vliw[32,64]_insns are used find out

   which vliw combinaion (16 bit core with 48 bit copro, 32 bit core

   with 32 bit copro, etc.) is present.  Later on, when internally

   parallel coprocessors are handled, only these functions should

   need to be changed.

   At this time only the following combinations are supported:

   VLIW32 Mode:

   16 bit core insn (core) and 16 bit coprocessor insn (cop1)

   32 bit core insn (core)

   32 bit coprocessor insn (cop1)

   Note: As of this time, I do not believe we have enough information

         to distinguish a 32 bit core insn from a 32 bit cop insn. Also,

         no 16 bit coprocessor insns have been specified.

   VLIW64 Mode:

   16 bit core insn (core) and 48 bit coprocessor insn (cop1)

   32 bit core insn (core) and 32 bit coprocessor insn (cop1)

   64 bit coprocessor insn (cop1)

   The framework for an internally parallel coprocessor is also

   present (2nd coprocessor insn is cop2), but at this time it

   is not used.  This only appears to be valid in VLIW64 mode.  */

static int

mep_examine_vliw32_insns (CGEN_CPU_DESC cd, bfd_vma pc, disassemble_info *info)

{

  int status;

  int buflength;

  int corebuflength;

  int cop1buflength;

  int cop2buflength;

  bfd_byte buf[CGEN_MAX_INSN_SIZE];

  char indicator16[1];

  char indicatorcop32[2];

  /* At this time we're not supporting internally parallel coprocessors,

     so cop2buflength will always be 0.  */

  cop2buflength = 0;

  /* Read in 32 bits.  */

  buflength = 4; /* VLIW insn spans 4 bytes.  */

  status = (*info->read_memory_func) (pc, buf, buflength, info);

  if (status != 0)

    {

      (*info->memory_error_func) (status, pc, info);

      return -1;

    }

  /* Put the big endian representation of the bytes to be examined

     in the temporary buffers for examination.  */

  if (info->endian == BFD_ENDIAN_BIG)

    {

      indicator16[0] = buf[0];

      indicatorcop32[0] = buf[0];

      indicatorcop32[1] = buf[1];

    }

  else

    {

      indicator16[0] = buf[1];

      indicatorcop32[0] = buf[1];

      indicatorcop32[1] = buf[0];

    }

  /* If the two high order bits are 00, 01 or 10, we have a 16 bit

     core insn and a 48 bit copro insn.  */

  if ((indicator16[0] & 0x80) && (indicator16[0] & 0x40))

    {

      if ((indicatorcop32[0] & 0xf0) == 0xf0 && (indicatorcop32[1] & 0x07) == 0x07)

        {

          /* We have a 32 bit copro insn.  */

          corebuflength = 0;

          /* All 4 4ytes are one copro insn. */

          cop1buflength = 4;

        }

      else

        {

          /* We have a 32 bit core.  */

          corebuflength = 4;

          cop1buflength = 0;

        }

    }

  else

    {

      /* We have a 16 bit core insn and a 16 bit copro insn.  */

      corebuflength = 2;

      cop1buflength = 2;

    }

  /* Now we have the distrubution set.  Print them out.  */

  status = mep_print_vliw_insns (cd, pc, info, buf, corebuflength,

                                 cop1buflength, cop2buflength);

  return status;

}

static int

mep_examine_vliw64_insns (CGEN_CPU_DESC cd, bfd_vma pc, disassemble_info *info)

{

  int status;

  int buflength;

  int corebuflength;

  int cop1buflength;

  int cop2buflength;

  bfd_byte buf[CGEN_MAX_INSN_SIZE];

  char indicator16[1];

  char indicator64[4];

  /* At this time we're not supporting internally parallel

     coprocessors, so cop2buflength will always be 0.  */

  cop2buflength = 0;

  /* Read in 64 bits.  */

  buflength = 8; /* VLIW insn spans 8 bytes.  */

  status = (*info->read_memory_func) (pc, buf, buflength, info);

  if (status != 0)

    {

      (*info->memory_error_func) (status, pc, info);

      return -1;

    }

  /* We have all 64 bits in the buffer now.  We have to figure out

     what combination of instruction sizes are present.  The two

     high order bits will indicate whether or not we have a 16 bit

     core insn or not.  If not, then we have to look at the 7,8th

     bytes to tell whether we have 64 bit copro insn or a 32 bit

     core insn with a 32 bit copro insn.  Endianness will make a

     difference here.  */

  /* Put the big endian representation of the bytes to be examined

     in the temporary buffers for examination.  */

  /* indicator16[0] = buf[0];  */

  if (info->endian == BFD_ENDIAN_BIG)

    {

      indicator16[0] = buf[0];

      indicator64[0] = buf[0];

      indicator64[1] = buf[1];

      indicator64[2] = buf[2];

      indicator64[3] = buf[3];

    }

  else

    {

      indicator16[0] = buf[1];

      indicator64[0] = buf[1];

      indicator64[1] = buf[0];

      indicator64[2] = buf[3];

      indicator64[3] = buf[2];

    }

  /* If the two high order bits are 00, 01 or 10, we have a 16 bit

     core insn and a 48 bit copro insn.  */

  if ((indicator16[0] & 0x80) && (indicator16[0] & 0x40))

    {

      if ((indicator64[0] & 0xf0) == 0xf0 && (indicator64[1] & 0x07) == 0x07

          && ((indicator64[2] & 0xfe) != 0xf0 || (indicator64[3] & 0xf4) != 0))

        {

          /* We have a 64 bit copro insn.  */

          corebuflength = 0;

          /* All 8 bytes are one copro insn.  */

          cop1buflength = 8;

        }

      else

        {

          /* We have a 32 bit core insn and a 32 bit copro insn.  */

          corebuflength = 4;

          cop1buflength = 4;

        }

    }

  else

    {

      /* We have a 16 bit core insn and a 48 bit copro insn.  */

      corebuflength = 2;

      cop1buflength = 6;

    }

  /* Now we have the distrubution set.  Print them out. */

  status = mep_print_vliw_insns (cd, pc, info, buf, corebuflength,

                                 cop1buflength, cop2buflength);

  return status;

}

#ifdef MEP_IVC2_SUPPORTED

static int

print_slot_insn (CGEN_CPU_DESC cd,

                 bfd_vma pc,

                 disassemble_info *info,

                 SLOTS_ATTR slot,

                 bfd_byte *buf)

{

  const CGEN_INSN_LIST *insn_list;

  CGEN_INSN_INT insn_value;

  CGEN_EXTRACT_INFO ex_info;

  insn_value = cgen_get_insn_value (cd, buf, 32);

  /* Fill in ex_info fields like read_insn would.  Don't actually call

     read_insn, since the incoming buffer is already read (and possibly

     modified a la m32r).  */

  ex_info.valid = (1 << 8) - 1;

  ex_info.dis_info = info;

  ex_info.insn_bytes = buf;

  /* The instructions are stored in hash lists.

     Pick the first one and keep trying until we find the right one.  */

  insn_list = CGEN_DIS_LOOKUP_INSN (cd, (char *) buf, insn_value);

  while (insn_list != NULL)

    {

      const CGEN_INSN *insn = insn_list->insn;

      CGEN_FIELDS fields;

      int length;

      if ((CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_CONFIG)

           && CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_CONFIG) != MEP_CONFIG)

          || ! (CGEN_ATTR_CGEN_INSN_SLOTS_VALUE (CGEN_INSN_ATTRS (insn)) & (1 << slot)))

        {

          insn_list = CGEN_DIS_NEXT_INSN (insn_list);

          continue;

        }

      if ((insn_value & CGEN_INSN_BASE_MASK (insn))

          == CGEN_INSN_BASE_VALUE (insn))

        {

          /* Printing is handled in two passes.  The first pass parses the

             machine insn and extracts the fields.  The second pass prints

             them.  */

          length = CGEN_EXTRACT_FN (cd, insn)

            (cd, insn, &ex_info, insn_value, &fields, pc);

          /* Length < 0 -> error.  */

          if (length < 0)

            return length;

          if (length > 0)

            {

              CGEN_PRINT_FN (cd, insn) (cd, info, insn, &fields, pc, length);

              /* Length is in bits, result is in bytes.  */

              return length / 8;

            }

        }

      insn_list = CGEN_DIS_NEXT_INSN (insn_list);

    }

  if (slot == SLOTS_P0S)

    (*info->fprintf_func) (info->stream, "*unknown-p0s*");

  else if (slot == SLOTS_P0)

    (*info->fprintf_func) (info->stream, "*unknown-p0*");

  else if (slot == SLOTS_P1)

    (*info->fprintf_func) (info->stream, "*unknown-p1*");

  else if (slot == SLOTS_C3)

    (*info->fprintf_func) (info->stream, "*unknown-c3*");

  return 0;

}

static int

mep_examine_ivc2_insns (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, bfd_vma pc ATTRIBUTE_UNUSED, disassemble_info *info ATTRIBUTE_UNUSED)

{

  int status;

  int buflength;

  bfd_byte buf[8];

  bfd_byte insn[8];

  int e;

  /* Read in 64 bits.  */

  buflength = 8; /* VLIW insn spans 8 bytes.  */

  status = (*info->read_memory_func) (pc, buf, buflength, info);

  if (status != 0)

    {

      (*info->memory_error_func) (status, pc, info);

      return -1;

    }

  if (info->endian == BFD_ENDIAN_LITTLE)

    e = 1;

  else

    e = 0;

  if (((unsigned char)buf[0^e] & 0xf0) < 0xc0)

    {

      /*      <--00--><--11--><--22--><--33--><--44--><--55--><--66--><--77--> */

      /* V1   [-----core-----][--------p0s-------][------------p1------------] */

      print_insn (cd, pc, info, buf, 2);

      insn[0^e] = 0;

      insn[1^e] = buf[2^e];

      insn[2^e] = buf[3^e];

      insn[3^e] = buf[4^e] & 0xf0;

      (*info->fprintf_func) (info->stream, " + ");

      print_slot_insn (cd, pc, info, SLOTS_P0S, insn);

      insn[0^e] = buf[4^e] << 4 | buf[5^e] >> 4;

      insn[1^e] = buf[5^e] << 4 | buf[6^e] >> 4;

      insn[2^e] = buf[6^e] << 4 | buf[7^e] >> 4;

      insn[3^e] = buf[7^e] << 4;

      (*info->fprintf_func) (info->stream, " + ");

      print_slot_insn (cd, pc, info, SLOTS_P1, insn);

    }

  else if ((buf[0^e] & 0xf0) == 0xf0 && (buf[1^e] & 0x0f) == 0x07)

    {

      /*      <--00--><--11--><--22--><--33--><--44--><--55--><--66--><--77--> */

      /* V3   1111[--p0--]0111[--------p0--------][------------p1------------] */

      /*                                          00000000111111112222222233333333 */

      insn[0^e] = buf[0^e] << 4 | buf[1^e] >> 4;

      insn[1^e] = buf[2^e];

      insn[2^e] = buf[3^e];

      insn[3^e] = buf[4^e] & 0xf0;

      print_slot_insn (cd, pc, info, SLOTS_P0, insn);

      insn[0^e] = buf[4^e] << 4 | buf[5^e] >> 4;

      insn[1^e] = buf[5^e] << 4 | buf[6^e] >> 4;

      insn[2^e] = buf[6^e] << 4 | buf[7^e] >> 4;

      insn[3^e] = buf[7^e] << 4;

      (*info->fprintf_func) (info->stream, " + ");

      print_slot_insn (cd, pc, info, SLOTS_P1, insn);

    }

  else

    {

      /*      <--00--><--11--><--22--><--33--><--44--><--55--><--66--><--77--> */

      /* V2   [-------------core-------------]xxxx[------------p1------------] */

      print_insn (cd, pc, info, buf, 4);

      insn[0^e] = buf[4^e] << 4 | buf[5^e] >> 4;

      insn[1^e] = buf[5^e] << 4 | buf[6^e] >> 4;

      insn[2^e] = buf[6^e] << 4 | buf[7^e] >> 4;

      insn[3^e] = buf[7^e] << 4;

      (*info->fprintf_func) (info->stream, " + ");

      print_slot_insn (cd, pc, info, SLOTS_P1, insn);

    }

  return 8;

}

#endif /* MEP_IVC2_SUPPORTED */

/* This is a hack.  SID calls this to update the disassembler as the

   CPU changes modes.  */

static int mep_ivc2_disassemble_p = 0;

static int mep_ivc2_vliw_disassemble_p = 0;

void

mep_print_insn_set_ivc2_mode (int ivc2_p, int vliw_p, int cfg_idx);

void

mep_print_insn_set_ivc2_mode (int ivc2_p, int vliw_p, int cfg_idx)

{

  mep_ivc2_disassemble_p = ivc2_p;

  mep_ivc2_vliw_disassemble_p = vliw_p;

  mep_config_index = cfg_idx;

}

static int

mep_print_insn (CGEN_CPU_DESC cd, bfd_vma pc, disassemble_info *info)

{

  int status;

  int cop_type;

  int ivc2 = 0;

  static CGEN_ATTR_VALUE_BITSET_TYPE *ivc2_core_isa = NULL;

  if (ivc2_core_isa == NULL)

    {

      /* IVC2 has some core-only coprocessor instructions.  We

         use COP32 to flag those, and COP64 for the VLIW ones,

         since they have the same names.  */

      ivc2_core_isa = cgen_bitset_create (MAX_ISAS);

    }

  /* Extract and adapt to configuration number, if available. */

  if (info->section && info->section->owner)

    {

      bfd *abfd = info->section->owner;

      mep_config_index = abfd->tdata.elf_obj_data->elf_header->e_flags & EF_MEP_INDEX_MASK;

      /* This instantly redefines MEP_CONFIG, MEP_OMASK, .... MEP_VLIW64 */

      cop_type = abfd->tdata.elf_obj_data->elf_header->e_flags & EF_MEP_COP_MASK;

      if (cop_type == EF_MEP_COP_IVC2)

        ivc2 = 1;

    }