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[/] [openrisc/] [trunk/] [gnu-stable/] [gdb-7.2/] [opcodes/] [xstormy16-desc.c] - Blame information for rev 841

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1 330 jeremybenn
/* CPU data for xstormy16.
2
 
3
THIS FILE IS MACHINE GENERATED WITH CGEN.
4
 
5
Copyright 1996-2010 Free Software Foundation, Inc.
6
 
7
This file is part of the GNU Binutils and/or GDB, the GNU debugger.
8
 
9
   This file is free software; you can redistribute it and/or modify
10
   it under the terms of the GNU General Public License as published by
11
   the Free Software Foundation; either version 3, or (at your option)
12
   any later version.
13
 
14
   It is distributed in the hope that it will be useful, but WITHOUT
15
   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
16
   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
17
   License for more details.
18
 
19
   You should have received a copy of the GNU General Public License along
20
   with this program; if not, write to the Free Software Foundation, Inc.,
21
   51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
22
 
23
*/
24
 
25
#include "sysdep.h"
26
#include <stdio.h>
27
#include <stdarg.h>
28
#include "ansidecl.h"
29
#include "bfd.h"
30
#include "symcat.h"
31
#include "xstormy16-desc.h"
32
#include "xstormy16-opc.h"
33
#include "opintl.h"
34
#include "libiberty.h"
35
#include "xregex.h"
36
 
37
/* Attributes.  */
38
 
39
static const CGEN_ATTR_ENTRY bool_attr[] =
40
{
41
  { "#f", 0 },
42
  { "#t", 1 },
43
  { 0, 0 }
44
};
45
 
46
static const CGEN_ATTR_ENTRY MACH_attr[] ATTRIBUTE_UNUSED =
47
{
48
  { "base", MACH_BASE },
49
  { "xstormy16", MACH_XSTORMY16 },
50
  { "max", MACH_MAX },
51
  { 0, 0 }
52
};
53
 
54
static const CGEN_ATTR_ENTRY ISA_attr[] ATTRIBUTE_UNUSED =
55
{
56
  { "xstormy16", ISA_XSTORMY16 },
57
  { "max", ISA_MAX },
58
  { 0, 0 }
59
};
60
 
61
const CGEN_ATTR_TABLE xstormy16_cgen_ifield_attr_table[] =
62
{
63
  { "MACH", & MACH_attr[0], & MACH_attr[0] },
64
  { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
65
  { "PCREL-ADDR", &bool_attr[0], &bool_attr[0] },
66
  { "ABS-ADDR", &bool_attr[0], &bool_attr[0] },
67
  { "RESERVED", &bool_attr[0], &bool_attr[0] },
68
  { "SIGN-OPT", &bool_attr[0], &bool_attr[0] },
69
  { "SIGNED", &bool_attr[0], &bool_attr[0] },
70
  { 0, 0, 0 }
71
};
72
 
73
const CGEN_ATTR_TABLE xstormy16_cgen_hardware_attr_table[] =
74
{
75
  { "MACH", & MACH_attr[0], & MACH_attr[0] },
76
  { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
77
  { "CACHE-ADDR", &bool_attr[0], &bool_attr[0] },
78
  { "PC", &bool_attr[0], &bool_attr[0] },
79
  { "PROFILE", &bool_attr[0], &bool_attr[0] },
80
  { 0, 0, 0 }
81
};
82
 
83
const CGEN_ATTR_TABLE xstormy16_cgen_operand_attr_table[] =
84
{
85
  { "MACH", & MACH_attr[0], & MACH_attr[0] },
86
  { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
87
  { "PCREL-ADDR", &bool_attr[0], &bool_attr[0] },
88
  { "ABS-ADDR", &bool_attr[0], &bool_attr[0] },
89
  { "SIGN-OPT", &bool_attr[0], &bool_attr[0] },
90
  { "SIGNED", &bool_attr[0], &bool_attr[0] },
91
  { "NEGATIVE", &bool_attr[0], &bool_attr[0] },
92
  { "RELAX", &bool_attr[0], &bool_attr[0] },
93
  { "SEM-ONLY", &bool_attr[0], &bool_attr[0] },
94
  { 0, 0, 0 }
95
};
96
 
97
const CGEN_ATTR_TABLE xstormy16_cgen_insn_attr_table[] =
98
{
99
  { "MACH", & MACH_attr[0], & MACH_attr[0] },
100
  { "ALIAS", &bool_attr[0], &bool_attr[0] },
101
  { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
102
  { "UNCOND-CTI", &bool_attr[0], &bool_attr[0] },
103
  { "COND-CTI", &bool_attr[0], &bool_attr[0] },
104
  { "SKIP-CTI", &bool_attr[0], &bool_attr[0] },
105
  { "DELAY-SLOT", &bool_attr[0], &bool_attr[0] },
106
  { "RELAXABLE", &bool_attr[0], &bool_attr[0] },
107
  { "RELAXED", &bool_attr[0], &bool_attr[0] },
108
  { "NO-DIS", &bool_attr[0], &bool_attr[0] },
109
  { "PBB", &bool_attr[0], &bool_attr[0] },
110
  { 0, 0, 0 }
111
};
112
 
113
/* Instruction set variants.  */
114
 
115
static const CGEN_ISA xstormy16_cgen_isa_table[] = {
116
  { "xstormy16", 32, 32, 16, 32 },
117
  { 0, 0, 0, 0, 0 }
118
};
119
 
120
/* Machine variants.  */
121
 
122
static const CGEN_MACH xstormy16_cgen_mach_table[] = {
123
  { "xstormy16", "xstormy16", MACH_XSTORMY16, 16 },
124
  { 0, 0, 0, 0 }
125
};
126
 
127
static CGEN_KEYWORD_ENTRY xstormy16_cgen_opval_gr_names_entries[] =
128
{
129
  { "r0", 0, {0, {{{0, 0}}}}, 0, 0 },
130
  { "r1", 1, {0, {{{0, 0}}}}, 0, 0 },
131
  { "r2", 2, {0, {{{0, 0}}}}, 0, 0 },
132
  { "r3", 3, {0, {{{0, 0}}}}, 0, 0 },
133
  { "r4", 4, {0, {{{0, 0}}}}, 0, 0 },
134
  { "r5", 5, {0, {{{0, 0}}}}, 0, 0 },
135
  { "r6", 6, {0, {{{0, 0}}}}, 0, 0 },
136
  { "r7", 7, {0, {{{0, 0}}}}, 0, 0 },
137
  { "r8", 8, {0, {{{0, 0}}}}, 0, 0 },
138
  { "r9", 9, {0, {{{0, 0}}}}, 0, 0 },
139
  { "r10", 10, {0, {{{0, 0}}}}, 0, 0 },
140
  { "r11", 11, {0, {{{0, 0}}}}, 0, 0 },
141
  { "r12", 12, {0, {{{0, 0}}}}, 0, 0 },
142
  { "r13", 13, {0, {{{0, 0}}}}, 0, 0 },
143
  { "r14", 14, {0, {{{0, 0}}}}, 0, 0 },
144
  { "r15", 15, {0, {{{0, 0}}}}, 0, 0 },
145
  { "psw", 14, {0, {{{0, 0}}}}, 0, 0 },
146
  { "sp", 15, {0, {{{0, 0}}}}, 0, 0 }
147
};
148
 
149
CGEN_KEYWORD xstormy16_cgen_opval_gr_names =
150
{
151
  & xstormy16_cgen_opval_gr_names_entries[0],
152
  18,
153
  0, 0, 0, 0, ""
154
};
155
 
156
static CGEN_KEYWORD_ENTRY xstormy16_cgen_opval_gr_Rb_names_entries[] =
157
{
158
  { "r8", 0, {0, {{{0, 0}}}}, 0, 0 },
159
  { "r9", 1, {0, {{{0, 0}}}}, 0, 0 },
160
  { "r10", 2, {0, {{{0, 0}}}}, 0, 0 },
161
  { "r11", 3, {0, {{{0, 0}}}}, 0, 0 },
162
  { "r12", 4, {0, {{{0, 0}}}}, 0, 0 },
163
  { "r13", 5, {0, {{{0, 0}}}}, 0, 0 },
164
  { "r14", 6, {0, {{{0, 0}}}}, 0, 0 },
165
  { "r15", 7, {0, {{{0, 0}}}}, 0, 0 },
166
  { "psw", 6, {0, {{{0, 0}}}}, 0, 0 },
167
  { "sp", 7, {0, {{{0, 0}}}}, 0, 0 }
168
};
169
 
170
CGEN_KEYWORD xstormy16_cgen_opval_gr_Rb_names =
171
{
172
  & xstormy16_cgen_opval_gr_Rb_names_entries[0],
173
  10,
174
  0, 0, 0, 0, ""
175
};
176
 
177
static CGEN_KEYWORD_ENTRY xstormy16_cgen_opval_h_branchcond_entries[] =
178
{
179
  { "ge", 0, {0, {{{0, 0}}}}, 0, 0 },
180
  { "nc", 1, {0, {{{0, 0}}}}, 0, 0 },
181
  { "lt", 2, {0, {{{0, 0}}}}, 0, 0 },
182
  { "c", 3, {0, {{{0, 0}}}}, 0, 0 },
183
  { "gt", 4, {0, {{{0, 0}}}}, 0, 0 },
184
  { "hi", 5, {0, {{{0, 0}}}}, 0, 0 },
185
  { "le", 6, {0, {{{0, 0}}}}, 0, 0 },
186
  { "ls", 7, {0, {{{0, 0}}}}, 0, 0 },
187
  { "pl", 8, {0, {{{0, 0}}}}, 0, 0 },
188
  { "nv", 9, {0, {{{0, 0}}}}, 0, 0 },
189
  { "mi", 10, {0, {{{0, 0}}}}, 0, 0 },
190
  { "v", 11, {0, {{{0, 0}}}}, 0, 0 },
191
  { "nz.b", 12, {0, {{{0, 0}}}}, 0, 0 },
192
  { "nz", 13, {0, {{{0, 0}}}}, 0, 0 },
193
  { "z.b", 14, {0, {{{0, 0}}}}, 0, 0 },
194
  { "z", 15, {0, {{{0, 0}}}}, 0, 0 }
195
};
196
 
197
CGEN_KEYWORD xstormy16_cgen_opval_h_branchcond =
198
{
199
  & xstormy16_cgen_opval_h_branchcond_entries[0],
200
  16,
201
  0, 0, 0, 0, ""
202
};
203
 
204
static CGEN_KEYWORD_ENTRY xstormy16_cgen_opval_h_wordsize_entries[] =
205
{
206
  { ".b", 0, {0, {{{0, 0}}}}, 0, 0 },
207
  { ".w", 1, {0, {{{0, 0}}}}, 0, 0 },
208
  { "", 1, {0, {{{0, 0}}}}, 0, 0 }
209
};
210
 
211
CGEN_KEYWORD xstormy16_cgen_opval_h_wordsize =
212
{
213
  & xstormy16_cgen_opval_h_wordsize_entries[0],
214
  3,
215
  0, 0, 0, 0, ""
216
};
217
 
218
 
219
/* The hardware table.  */
220
 
221
#define A(a) (1 << CGEN_HW_##a)
222
 
223
const CGEN_HW_ENTRY xstormy16_cgen_hw_table[] =
224
{
225
  { "h-memory", HW_H_MEMORY, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
226
  { "h-sint", HW_H_SINT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
227
  { "h-uint", HW_H_UINT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
228
  { "h-addr", HW_H_ADDR, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
229
  { "h-iaddr", HW_H_IADDR, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
230
  { "h-pc", HW_H_PC, CGEN_ASM_NONE, 0, { 0|A(PC), { { { (1<<MACH_BASE), 0 } } } } },
231
  { "h-gr", HW_H_GR, CGEN_ASM_KEYWORD, (PTR) & xstormy16_cgen_opval_gr_names, { 0, { { { (1<<MACH_BASE), 0 } } } } },
232
  { "h-Rb", HW_H_RB, CGEN_ASM_KEYWORD, (PTR) & xstormy16_cgen_opval_gr_Rb_names, { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } },
233
  { "h-Rbj", HW_H_RBJ, CGEN_ASM_KEYWORD, (PTR) & xstormy16_cgen_opval_gr_Rb_names, { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } },
234
  { "h-Rpsw", HW_H_RPSW, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } },
235
  { "h-z8", HW_H_Z8, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } },
236
  { "h-z16", HW_H_Z16, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } },
237
  { "h-cy", HW_H_CY, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } },
238
  { "h-hc", HW_H_HC, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } },
239
  { "h-ov", HW_H_OV, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } },
240
  { "h-pt", HW_H_PT, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } },
241
  { "h-s", HW_H_S, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } },
242
  { "h-branchcond", HW_H_BRANCHCOND, CGEN_ASM_KEYWORD, (PTR) & xstormy16_cgen_opval_h_branchcond, { 0, { { { (1<<MACH_BASE), 0 } } } } },
243
  { "h-wordsize", HW_H_WORDSIZE, CGEN_ASM_KEYWORD, (PTR) & xstormy16_cgen_opval_h_wordsize, { 0, { { { (1<<MACH_BASE), 0 } } } } },
244
  { 0, 0, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }
245
};
246
 
247
#undef A
248
 
249
 
250
/* The instruction field table.  */
251
 
252
#define A(a) (1 << CGEN_IFLD_##a)
253
 
254
const CGEN_IFLD xstormy16_cgen_ifld_table[] =
255
{
256
  { XSTORMY16_F_NIL, "f-nil", 0, 0, 0, 0, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
257
  { XSTORMY16_F_ANYOF, "f-anyof", 0, 0, 0, 0, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
258
  { XSTORMY16_F_RD, "f-Rd", 0, 32, 12, 4, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
259
  { XSTORMY16_F_RDM, "f-Rdm", 0, 32, 13, 3, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
260
  { XSTORMY16_F_RM, "f-Rm", 0, 32, 4, 3, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
261
  { XSTORMY16_F_RS, "f-Rs", 0, 32, 8, 4, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
262
  { XSTORMY16_F_RB, "f-Rb", 0, 32, 17, 3, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
263
  { XSTORMY16_F_RBJ, "f-Rbj", 0, 32, 11, 1, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
264
  { XSTORMY16_F_OP1, "f-op1", 0, 32, 0, 4, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
265
  { XSTORMY16_F_OP2, "f-op2", 0, 32, 4, 4, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
266
  { XSTORMY16_F_OP2A, "f-op2a", 0, 32, 4, 3, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
267
  { XSTORMY16_F_OP2M, "f-op2m", 0, 32, 7, 1, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
268
  { XSTORMY16_F_OP3, "f-op3", 0, 32, 8, 4, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
269
  { XSTORMY16_F_OP3A, "f-op3a", 0, 32, 8, 2, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
270
  { XSTORMY16_F_OP3B, "f-op3b", 0, 32, 8, 3, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
271
  { XSTORMY16_F_OP4, "f-op4", 0, 32, 12, 4, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
272
  { XSTORMY16_F_OP4M, "f-op4m", 0, 32, 12, 1, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
273
  { XSTORMY16_F_OP4B, "f-op4b", 0, 32, 15, 1, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
274
  { XSTORMY16_F_OP5, "f-op5", 0, 32, 16, 4, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
275
  { XSTORMY16_F_OP5A, "f-op5a", 0, 32, 16, 1, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
276
  { XSTORMY16_F_OP, "f-op", 0, 32, 0, 16, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
277
  { XSTORMY16_F_IMM2, "f-imm2", 0, 32, 10, 2, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
278
  { XSTORMY16_F_IMM3, "f-imm3", 0, 32, 4, 3, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
279
  { XSTORMY16_F_IMM3B, "f-imm3b", 0, 32, 17, 3, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
280
  { XSTORMY16_F_IMM4, "f-imm4", 0, 32, 8, 4, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
281
  { XSTORMY16_F_IMM8, "f-imm8", 0, 32, 8, 8, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
282
  { XSTORMY16_F_IMM12, "f-imm12", 0, 32, 20, 12, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
283
  { XSTORMY16_F_IMM16, "f-imm16", 0, 32, 16, 16, { 0|A(SIGN_OPT), { { { (1<<MACH_BASE), 0 } } } }  },
284
  { XSTORMY16_F_LMEM8, "f-lmem8", 0, 32, 8, 8, { 0|A(ABS_ADDR), { { { (1<<MACH_BASE), 0 } } } }  },
285
  { XSTORMY16_F_HMEM8, "f-hmem8", 0, 32, 8, 8, { 0|A(ABS_ADDR), { { { (1<<MACH_BASE), 0 } } } }  },
286
  { XSTORMY16_F_REL8_2, "f-rel8-2", 0, 32, 8, 8, { 0|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } } } }  },
287
  { XSTORMY16_F_REL8_4, "f-rel8-4", 0, 32, 8, 8, { 0|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } } } }  },
288
  { XSTORMY16_F_REL12, "f-rel12", 0, 32, 20, 12, { 0|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } } } }  },
289
  { XSTORMY16_F_REL12A, "f-rel12a", 0, 32, 4, 11, { 0|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } } } }  },
290
  { XSTORMY16_F_ABS24_1, "f-abs24-1", 0, 32, 8, 8, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
291
  { XSTORMY16_F_ABS24_2, "f-abs24-2", 0, 32, 16, 16, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
292
  { XSTORMY16_F_ABS24, "f-abs24", 0, 0, 0, 0,{ 0|A(ABS_ADDR)|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } }  },
293
  { 0, 0, 0, 0, 0, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }
294
};
295
 
296
#undef A
297
 
298
 
299
 
300
/* multi ifield declarations */
301
 
302
const CGEN_MAYBE_MULTI_IFLD XSTORMY16_F_ABS24_MULTI_IFIELD [];
303
 
304
 
305
/* multi ifield definitions */
306
 
307
const CGEN_MAYBE_MULTI_IFLD XSTORMY16_F_ABS24_MULTI_IFIELD [] =
308
{
309
    { 0, { (const PTR) &xstormy16_cgen_ifld_table[XSTORMY16_F_ABS24_1] } },
310
    { 0, { (const PTR) &xstormy16_cgen_ifld_table[XSTORMY16_F_ABS24_2] } },
311
    { 0, { (const PTR) 0 } }
312
};
313
 
314
/* The operand table.  */
315
 
316
#define A(a) (1 << CGEN_OPERAND_##a)
317
#define OPERAND(op) XSTORMY16_OPERAND_##op
318
 
319
const CGEN_OPERAND xstormy16_cgen_operand_table[] =
320
{
321
/* pc: program counter */
322
  { "pc", XSTORMY16_OPERAND_PC, HW_H_PC, 0, 0,
323
    { 0, { (const PTR) &xstormy16_cgen_ifld_table[XSTORMY16_F_NIL] } },
324
    { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } }  },
325
/* psw-z8:  */
326
  { "psw-z8", XSTORMY16_OPERAND_PSW_Z8, HW_H_Z8, 0, 0,
327
    { 0, { (const PTR) 0 } },
328
    { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } }  },
329
/* psw-z16:  */
330
  { "psw-z16", XSTORMY16_OPERAND_PSW_Z16, HW_H_Z16, 0, 0,
331
    { 0, { (const PTR) 0 } },
332
    { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } }  },
333
/* psw-cy:  */
334
  { "psw-cy", XSTORMY16_OPERAND_PSW_CY, HW_H_CY, 0, 0,
335
    { 0, { (const PTR) 0 } },
336
    { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } }  },
337
/* psw-hc:  */
338
  { "psw-hc", XSTORMY16_OPERAND_PSW_HC, HW_H_HC, 0, 0,
339
    { 0, { (const PTR) 0 } },
340
    { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } }  },
341
/* psw-ov:  */
342
  { "psw-ov", XSTORMY16_OPERAND_PSW_OV, HW_H_OV, 0, 0,
343
    { 0, { (const PTR) 0 } },
344
    { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } }  },
345
/* psw-pt:  */
346
  { "psw-pt", XSTORMY16_OPERAND_PSW_PT, HW_H_PT, 0, 0,
347
    { 0, { (const PTR) 0 } },
348
    { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } }  },
349
/* psw-s:  */
350
  { "psw-s", XSTORMY16_OPERAND_PSW_S, HW_H_S, 0, 0,
351
    { 0, { (const PTR) 0 } },
352
    { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } }  },
353
/* Rd: general register destination */
354
  { "Rd", XSTORMY16_OPERAND_RD, HW_H_GR, 12, 4,
355
    { 0, { (const PTR) &xstormy16_cgen_ifld_table[XSTORMY16_F_RD] } },
356
    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
357
/* Rdm: general register destination */
358
  { "Rdm", XSTORMY16_OPERAND_RDM, HW_H_GR, 13, 3,
359
    { 0, { (const PTR) &xstormy16_cgen_ifld_table[XSTORMY16_F_RDM] } },
360
    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
361
/* Rm: general register for memory */
362
  { "Rm", XSTORMY16_OPERAND_RM, HW_H_GR, 4, 3,
363
    { 0, { (const PTR) &xstormy16_cgen_ifld_table[XSTORMY16_F_RM] } },
364
    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
365
/* Rs: general register source */
366
  { "Rs", XSTORMY16_OPERAND_RS, HW_H_GR, 8, 4,
367
    { 0, { (const PTR) &xstormy16_cgen_ifld_table[XSTORMY16_F_RS] } },
368
    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
369
/* Rb: base register */
370
  { "Rb", XSTORMY16_OPERAND_RB, HW_H_RB, 17, 3,
371
    { 0, { (const PTR) &xstormy16_cgen_ifld_table[XSTORMY16_F_RB] } },
372
    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
373
/* Rbj: base register for jump */
374
  { "Rbj", XSTORMY16_OPERAND_RBJ, HW_H_RBJ, 11, 1,
375
    { 0, { (const PTR) &xstormy16_cgen_ifld_table[XSTORMY16_F_RBJ] } },
376
    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
377
/* bcond2: branch condition opcode */
378
  { "bcond2", XSTORMY16_OPERAND_BCOND2, HW_H_BRANCHCOND, 4, 4,
379
    { 0, { (const PTR) &xstormy16_cgen_ifld_table[XSTORMY16_F_OP2] } },
380
    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
381
/* ws2: word size opcode */
382
  { "ws2", XSTORMY16_OPERAND_WS2, HW_H_WORDSIZE, 7, 1,
383
    { 0, { (const PTR) &xstormy16_cgen_ifld_table[XSTORMY16_F_OP2M] } },
384
    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
385
/* bcond5: branch condition opcode */
386
  { "bcond5", XSTORMY16_OPERAND_BCOND5, HW_H_BRANCHCOND, 16, 4,
387
    { 0, { (const PTR) &xstormy16_cgen_ifld_table[XSTORMY16_F_OP5] } },
388
    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
389
/* imm2: 2 bit unsigned immediate */
390
  { "imm2", XSTORMY16_OPERAND_IMM2, HW_H_UINT, 10, 2,
391
    { 0, { (const PTR) &xstormy16_cgen_ifld_table[XSTORMY16_F_IMM2] } },
392
    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
393
/* imm3: 3 bit unsigned immediate */
394
  { "imm3", XSTORMY16_OPERAND_IMM3, HW_H_UINT, 4, 3,
395
    { 0, { (const PTR) &xstormy16_cgen_ifld_table[XSTORMY16_F_IMM3] } },
396
    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
397
/* imm3b: 3 bit unsigned immediate for bit tests */
398
  { "imm3b", XSTORMY16_OPERAND_IMM3B, HW_H_UINT, 17, 3,
399
    { 0, { (const PTR) &xstormy16_cgen_ifld_table[XSTORMY16_F_IMM3B] } },
400
    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
401
/* imm4: 4 bit unsigned immediate */
402
  { "imm4", XSTORMY16_OPERAND_IMM4, HW_H_UINT, 8, 4,
403
    { 0, { (const PTR) &xstormy16_cgen_ifld_table[XSTORMY16_F_IMM4] } },
404
    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
405
/* imm8: 8 bit unsigned immediate */
406
  { "imm8", XSTORMY16_OPERAND_IMM8, HW_H_UINT, 8, 8,
407
    { 0, { (const PTR) &xstormy16_cgen_ifld_table[XSTORMY16_F_IMM8] } },
408
    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
409
/* imm8small: 8 bit unsigned immediate */
410
  { "imm8small", XSTORMY16_OPERAND_IMM8SMALL, HW_H_UINT, 8, 8,
411
    { 0, { (const PTR) &xstormy16_cgen_ifld_table[XSTORMY16_F_IMM8] } },
412
    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
413
/* imm12: 12 bit signed immediate */
414
  { "imm12", XSTORMY16_OPERAND_IMM12, HW_H_SINT, 20, 12,
415
    { 0, { (const PTR) &xstormy16_cgen_ifld_table[XSTORMY16_F_IMM12] } },
416
    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
417
/* imm16: 16 bit immediate */
418
  { "imm16", XSTORMY16_OPERAND_IMM16, HW_H_UINT, 16, 16,
419
    { 0, { (const PTR) &xstormy16_cgen_ifld_table[XSTORMY16_F_IMM16] } },
420
    { 0|A(SIGN_OPT), { { { (1<<MACH_BASE), 0 } } } }  },
421
/* lmem8: 8 bit unsigned immediate low memory */
422
  { "lmem8", XSTORMY16_OPERAND_LMEM8, HW_H_UINT, 8, 8,
423
    { 0, { (const PTR) &xstormy16_cgen_ifld_table[XSTORMY16_F_LMEM8] } },
424
    { 0|A(ABS_ADDR), { { { (1<<MACH_BASE), 0 } } } }  },
425
/* hmem8: 8 bit unsigned immediate high memory */
426
  { "hmem8", XSTORMY16_OPERAND_HMEM8, HW_H_UINT, 8, 8,
427
    { 0, { (const PTR) &xstormy16_cgen_ifld_table[XSTORMY16_F_HMEM8] } },
428
    { 0|A(ABS_ADDR), { { { (1<<MACH_BASE), 0 } } } }  },
429
/* rel8-2: 8 bit relative address */
430
  { "rel8-2", XSTORMY16_OPERAND_REL8_2, HW_H_UINT, 8, 8,
431
    { 0, { (const PTR) &xstormy16_cgen_ifld_table[XSTORMY16_F_REL8_2] } },
432
    { 0|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } } } }  },
433
/* rel8-4: 8 bit relative address */
434
  { "rel8-4", XSTORMY16_OPERAND_REL8_4, HW_H_UINT, 8, 8,
435
    { 0, { (const PTR) &xstormy16_cgen_ifld_table[XSTORMY16_F_REL8_4] } },
436
    { 0|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } } } }  },
437
/* rel12: 12 bit relative address */
438
  { "rel12", XSTORMY16_OPERAND_REL12, HW_H_UINT, 20, 12,
439
    { 0, { (const PTR) &xstormy16_cgen_ifld_table[XSTORMY16_F_REL12] } },
440
    { 0|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } } } }  },
441
/* rel12a: 12 bit relative address */
442
  { "rel12a", XSTORMY16_OPERAND_REL12A, HW_H_UINT, 4, 11,
443
    { 0, { (const PTR) &xstormy16_cgen_ifld_table[XSTORMY16_F_REL12A] } },
444
    { 0|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } } } }  },
445
/* abs24: 24 bit absolute address */
446
  { "abs24", XSTORMY16_OPERAND_ABS24, HW_H_UINT, 8, 24,
447
    { 2, { (const PTR) &XSTORMY16_F_ABS24_MULTI_IFIELD[0] } },
448
    { 0|A(ABS_ADDR)|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } }  },
449
/* psw: program status word */
450
  { "psw", XSTORMY16_OPERAND_PSW, HW_H_GR, 0, 0,
451
    { 0, { (const PTR) 0 } },
452
    { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } }  },
453
/* Rpsw: N0-N3 of the program status word */
454
  { "Rpsw", XSTORMY16_OPERAND_RPSW, HW_H_RPSW, 0, 0,
455
    { 0, { (const PTR) 0 } },
456
    { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } }  },
457
/* sp: stack pointer */
458
  { "sp", XSTORMY16_OPERAND_SP, HW_H_GR, 0, 0,
459
    { 0, { (const PTR) 0 } },
460
    { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } }  },
461
/* R0: R0 */
462
  { "R0", XSTORMY16_OPERAND_R0, HW_H_GR, 0, 0,
463
    { 0, { (const PTR) 0 } },
464
    { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } }  },
465
/* R1: R1 */
466
  { "R1", XSTORMY16_OPERAND_R1, HW_H_GR, 0, 0,
467
    { 0, { (const PTR) 0 } },
468
    { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } }  },
469
/* R2: R2 */
470
  { "R2", XSTORMY16_OPERAND_R2, HW_H_GR, 0, 0,
471
    { 0, { (const PTR) 0 } },
472
    { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } }  },
473
/* R8: R8 */
474
  { "R8", XSTORMY16_OPERAND_R8, HW_H_GR, 0, 0,
475
    { 0, { (const PTR) 0 } },
476
    { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } }  },
477
/* sentinel */
478
  { 0, 0, 0, 0, 0,
479
    { 0, { (const PTR) 0 } },
480
    { 0, { { { (1<<MACH_BASE), 0 } } } } }
481
};
482
 
483
#undef A
484
 
485
 
486
/* The instruction table.  */
487
 
488
#define OP(field) CGEN_SYNTAX_MAKE_FIELD (OPERAND (field))
489
#define A(a) (1 << CGEN_INSN_##a)
490
 
491
static const CGEN_IBASE xstormy16_cgen_insn_table[MAX_INSNS] =
492
{
493
  /* Special null first entry.
494
     A `num' value of zero is thus invalid.
495
     Also, the special `invalid' insn resides here.  */
496
  { 0, 0, 0, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
497
/* mov$ws2 $lmem8,#$imm16 */
498
  {
499
    XSTORMY16_INSN_MOVLMEMIMM, "movlmemimm", "mov", 32,
500
    { 0, { { { (1<<MACH_BASE), 0 } } } }
501
  },
502
/* mov$ws2 $hmem8,#$imm16 */
503
  {
504
    XSTORMY16_INSN_MOVHMEMIMM, "movhmemimm", "mov", 32,
505
    { 0, { { { (1<<MACH_BASE), 0 } } } }
506
  },
507
/* mov$ws2 $Rm,$lmem8 */
508
  {
509
    XSTORMY16_INSN_MOVLGRMEM, "movlgrmem", "mov", 16,
510
    { 0, { { { (1<<MACH_BASE), 0 } } } }
511
  },
512
/* mov$ws2 $Rm,$hmem8 */
513
  {
514
    XSTORMY16_INSN_MOVHGRMEM, "movhgrmem", "mov", 16,
515
    { 0, { { { (1<<MACH_BASE), 0 } } } }
516
  },
517
/* mov$ws2 $lmem8,$Rm */
518
  {
519
    XSTORMY16_INSN_MOVLMEMGR, "movlmemgr", "mov", 16,
520
    { 0, { { { (1<<MACH_BASE), 0 } } } }
521
  },
522
/* mov$ws2 $hmem8,$Rm */
523
  {
524
    XSTORMY16_INSN_MOVHMEMGR, "movhmemgr", "mov", 16,
525
    { 0, { { { (1<<MACH_BASE), 0 } } } }
526
  },
527
/* mov$ws2 $Rdm,($Rs) */
528
  {
529
    XSTORMY16_INSN_MOVGRGRI, "movgrgri", "mov", 16,
530
    { 0, { { { (1<<MACH_BASE), 0 } } } }
531
  },
532
/* mov$ws2 $Rdm,($Rs++) */
533
  {
534
    XSTORMY16_INSN_MOVGRGRIPOSTINC, "movgrgripostinc", "mov", 16,
535
    { 0, { { { (1<<MACH_BASE), 0 } } } }
536
  },
537
/* mov$ws2 $Rdm,(--$Rs) */
538
  {
539
    XSTORMY16_INSN_MOVGRGRIPREDEC, "movgrgripredec", "mov", 16,
540
    { 0, { { { (1<<MACH_BASE), 0 } } } }
541
  },
542
/* mov$ws2 ($Rs),$Rdm */
543
  {
544
    XSTORMY16_INSN_MOVGRIGR, "movgrigr", "mov", 16,
545
    { 0, { { { (1<<MACH_BASE), 0 } } } }
546
  },
547
/* mov$ws2 ($Rs++),$Rdm */
548
  {
549
    XSTORMY16_INSN_MOVGRIPOSTINCGR, "movgripostincgr", "mov", 16,
550
    { 0, { { { (1<<MACH_BASE), 0 } } } }
551
  },
552
/* mov$ws2 (--$Rs),$Rdm */
553
  {
554
    XSTORMY16_INSN_MOVGRIPREDECGR, "movgripredecgr", "mov", 16,
555
    { 0, { { { (1<<MACH_BASE), 0 } } } }
556
  },
557
/* mov$ws2 $Rdm,($Rs,$imm12) */
558
  {
559
    XSTORMY16_INSN_MOVGRGRII, "movgrgrii", "mov", 32,
560
    { 0, { { { (1<<MACH_BASE), 0 } } } }
561
  },
562
/* mov$ws2 $Rdm,($Rs++,$imm12) */
563
  {
564
    XSTORMY16_INSN_MOVGRGRIIPOSTINC, "movgrgriipostinc", "mov", 32,
565
    { 0, { { { (1<<MACH_BASE), 0 } } } }
566
  },
567
/* mov$ws2 $Rdm,(--$Rs,$imm12) */
568
  {
569
    XSTORMY16_INSN_MOVGRGRIIPREDEC, "movgrgriipredec", "mov", 32,
570
    { 0, { { { (1<<MACH_BASE), 0 } } } }
571
  },
572
/* mov$ws2 ($Rs,$imm12),$Rdm */
573
  {
574
    XSTORMY16_INSN_MOVGRIIGR, "movgriigr", "mov", 32,
575
    { 0, { { { (1<<MACH_BASE), 0 } } } }
576
  },
577
/* mov$ws2 ($Rs++,$imm12),$Rdm */
578
  {
579
    XSTORMY16_INSN_MOVGRIIPOSTINCGR, "movgriipostincgr", "mov", 32,
580
    { 0, { { { (1<<MACH_BASE), 0 } } } }
581
  },
582
/* mov$ws2 (--$Rs,$imm12),$Rdm */
583
  {
584
    XSTORMY16_INSN_MOVGRIIPREDECGR, "movgriipredecgr", "mov", 32,
585
    { 0, { { { (1<<MACH_BASE), 0 } } } }
586
  },
587
/* mov $Rd,$Rs */
588
  {
589
    XSTORMY16_INSN_MOVGRGR, "movgrgr", "mov", 16,
590
    { 0, { { { (1<<MACH_BASE), 0 } } } }
591
  },
592
/* mov.w Rx,#$imm8 */
593
  {
594
    XSTORMY16_INSN_MOVWIMM8, "movwimm8", "mov.w", 16,
595
    { 0, { { { (1<<MACH_BASE), 0 } } } }
596
  },
597
/* mov.w $Rm,#$imm8small */
598
  {
599
    XSTORMY16_INSN_MOVWGRIMM8, "movwgrimm8", "mov.w", 16,
600
    { 0, { { { (1<<MACH_BASE), 0 } } } }
601
  },
602
/* mov.w $Rd,#$imm16 */
603
  {
604
    XSTORMY16_INSN_MOVWGRIMM16, "movwgrimm16", "mov.w", 32,
605
    { 0, { { { (1<<MACH_BASE), 0 } } } }
606
  },
607
/* mov.b $Rd,RxL */
608
  {
609
    XSTORMY16_INSN_MOVLOWGR, "movlowgr", "mov.b", 16,
610
    { 0, { { { (1<<MACH_BASE), 0 } } } }
611
  },
612
/* mov.b $Rd,RxH */
613
  {
614
    XSTORMY16_INSN_MOVHIGHGR, "movhighgr", "mov.b", 16,
615
    { 0, { { { (1<<MACH_BASE), 0 } } } }
616
  },
617
/* movf$ws2 $Rdm,($Rs) */
618
  {
619
    XSTORMY16_INSN_MOVFGRGRI, "movfgrgri", "movf", 16,
620
    { 0, { { { (1<<MACH_BASE), 0 } } } }
621
  },
622
/* movf$ws2 $Rdm,($Rs++) */
623
  {
624
    XSTORMY16_INSN_MOVFGRGRIPOSTINC, "movfgrgripostinc", "movf", 16,
625
    { 0, { { { (1<<MACH_BASE), 0 } } } }
626
  },
627
/* movf$ws2 $Rdm,(--$Rs) */
628
  {
629
    XSTORMY16_INSN_MOVFGRGRIPREDEC, "movfgrgripredec", "movf", 16,
630
    { 0, { { { (1<<MACH_BASE), 0 } } } }
631
  },
632
/* movf$ws2 ($Rs),$Rdm */
633
  {
634
    XSTORMY16_INSN_MOVFGRIGR, "movfgrigr", "movf", 16,
635
    { 0, { { { (1<<MACH_BASE), 0 } } } }
636
  },
637
/* movf$ws2 ($Rs++),$Rdm */
638
  {
639
    XSTORMY16_INSN_MOVFGRIPOSTINCGR, "movfgripostincgr", "movf", 16,
640
    { 0, { { { (1<<MACH_BASE), 0 } } } }
641
  },
642
/* movf$ws2 (--$Rs),$Rdm */
643
  {
644
    XSTORMY16_INSN_MOVFGRIPREDECGR, "movfgripredecgr", "movf", 16,
645
    { 0, { { { (1<<MACH_BASE), 0 } } } }
646
  },
647
/* movf$ws2 $Rdm,($Rb,$Rs,$imm12) */
648
  {
649
    XSTORMY16_INSN_MOVFGRGRII, "movfgrgrii", "movf", 32,
650
    { 0, { { { (1<<MACH_BASE), 0 } } } }
651
  },
652
/* movf$ws2 $Rdm,($Rb,$Rs++,$imm12) */
653
  {
654
    XSTORMY16_INSN_MOVFGRGRIIPOSTINC, "movfgrgriipostinc", "movf", 32,
655
    { 0, { { { (1<<MACH_BASE), 0 } } } }
656
  },
657
/* movf$ws2 $Rdm,($Rb,--$Rs,$imm12) */
658
  {
659
    XSTORMY16_INSN_MOVFGRGRIIPREDEC, "movfgrgriipredec", "movf", 32,
660
    { 0, { { { (1<<MACH_BASE), 0 } } } }
661
  },
662
/* movf$ws2 ($Rb,$Rs,$imm12),$Rdm */
663
  {
664
    XSTORMY16_INSN_MOVFGRIIGR, "movfgriigr", "movf", 32,
665
    { 0, { { { (1<<MACH_BASE), 0 } } } }
666
  },
667
/* movf$ws2 ($Rb,$Rs++,$imm12),$Rdm */
668
  {
669
    XSTORMY16_INSN_MOVFGRIIPOSTINCGR, "movfgriipostincgr", "movf", 32,
670
    { 0, { { { (1<<MACH_BASE), 0 } } } }
671
  },
672
/* movf$ws2 ($Rb,--$Rs,$imm12),$Rdm */
673
  {
674
    XSTORMY16_INSN_MOVFGRIIPREDECGR, "movfgriipredecgr", "movf", 32,
675
    { 0, { { { (1<<MACH_BASE), 0 } } } }
676
  },
677
/* mask $Rd,$Rs */
678
  {
679
    XSTORMY16_INSN_MASKGRGR, "maskgrgr", "mask", 16,
680
    { 0, { { { (1<<MACH_BASE), 0 } } } }
681
  },
682
/* mask $Rd,#$imm16 */
683
  {
684
    XSTORMY16_INSN_MASKGRIMM16, "maskgrimm16", "mask", 32,
685
    { 0, { { { (1<<MACH_BASE), 0 } } } }
686
  },
687
/* push $Rd */
688
  {
689
    XSTORMY16_INSN_PUSHGR, "pushgr", "push", 16,
690
    { 0, { { { (1<<MACH_BASE), 0 } } } }
691
  },
692
/* pop $Rd */
693
  {
694
    XSTORMY16_INSN_POPGR, "popgr", "pop", 16,
695
    { 0, { { { (1<<MACH_BASE), 0 } } } }
696
  },
697
/* swpn $Rd */
698
  {
699
    XSTORMY16_INSN_SWPN, "swpn", "swpn", 16,
700
    { 0, { { { (1<<MACH_BASE), 0 } } } }
701
  },
702
/* swpb $Rd */
703
  {
704
    XSTORMY16_INSN_SWPB, "swpb", "swpb", 16,
705
    { 0, { { { (1<<MACH_BASE), 0 } } } }
706
  },
707
/* swpw $Rd,$Rs */
708
  {
709
    XSTORMY16_INSN_SWPW, "swpw", "swpw", 16,
710
    { 0, { { { (1<<MACH_BASE), 0 } } } }
711
  },
712
/* and $Rd,$Rs */
713
  {
714
    XSTORMY16_INSN_ANDGRGR, "andgrgr", "and", 16,
715
    { 0, { { { (1<<MACH_BASE), 0 } } } }
716
  },
717
/* and Rx,#$imm8 */
718
  {
719
    XSTORMY16_INSN_ANDIMM8, "andimm8", "and", 16,
720
    { 0, { { { (1<<MACH_BASE), 0 } } } }
721
  },
722
/* and $Rd,#$imm16 */
723
  {
724
    XSTORMY16_INSN_ANDGRIMM16, "andgrimm16", "and", 32,
725
    { 0, { { { (1<<MACH_BASE), 0 } } } }
726
  },
727
/* or $Rd,$Rs */
728
  {
729
    XSTORMY16_INSN_ORGRGR, "orgrgr", "or", 16,
730
    { 0, { { { (1<<MACH_BASE), 0 } } } }
731
  },
732
/* or Rx,#$imm8 */
733
  {
734
    XSTORMY16_INSN_ORIMM8, "orimm8", "or", 16,
735
    { 0, { { { (1<<MACH_BASE), 0 } } } }
736
  },
737
/* or $Rd,#$imm16 */
738
  {
739
    XSTORMY16_INSN_ORGRIMM16, "orgrimm16", "or", 32,
740
    { 0, { { { (1<<MACH_BASE), 0 } } } }
741
  },
742
/* xor $Rd,$Rs */
743
  {
744
    XSTORMY16_INSN_XORGRGR, "xorgrgr", "xor", 16,
745
    { 0, { { { (1<<MACH_BASE), 0 } } } }
746
  },
747
/* xor Rx,#$imm8 */
748
  {
749
    XSTORMY16_INSN_XORIMM8, "xorimm8", "xor", 16,
750
    { 0, { { { (1<<MACH_BASE), 0 } } } }
751
  },
752
/* xor $Rd,#$imm16 */
753
  {
754
    XSTORMY16_INSN_XORGRIMM16, "xorgrimm16", "xor", 32,
755
    { 0, { { { (1<<MACH_BASE), 0 } } } }
756
  },
757
/* not $Rd */
758
  {
759
    XSTORMY16_INSN_NOTGR, "notgr", "not", 16,
760
    { 0, { { { (1<<MACH_BASE), 0 } } } }
761
  },
762
/* add $Rd,$Rs */
763
  {
764
    XSTORMY16_INSN_ADDGRGR, "addgrgr", "add", 16,
765
    { 0, { { { (1<<MACH_BASE), 0 } } } }
766
  },
767
/* add $Rd,#$imm4 */
768
  {
769
    XSTORMY16_INSN_ADDGRIMM4, "addgrimm4", "add", 16,
770
    { 0, { { { (1<<MACH_BASE), 0 } } } }
771
  },
772
/* add Rx,#$imm8 */
773
  {
774
    XSTORMY16_INSN_ADDIMM8, "addimm8", "add", 16,
775
    { 0, { { { (1<<MACH_BASE), 0 } } } }
776
  },
777
/* add $Rd,#$imm16 */
778
  {
779
    XSTORMY16_INSN_ADDGRIMM16, "addgrimm16", "add", 32,
780
    { 0, { { { (1<<MACH_BASE), 0 } } } }
781
  },
782
/* adc $Rd,$Rs */
783
  {
784
    XSTORMY16_INSN_ADCGRGR, "adcgrgr", "adc", 16,
785
    { 0, { { { (1<<MACH_BASE), 0 } } } }
786
  },
787
/* adc $Rd,#$imm4 */
788
  {
789
    XSTORMY16_INSN_ADCGRIMM4, "adcgrimm4", "adc", 16,
790
    { 0, { { { (1<<MACH_BASE), 0 } } } }
791
  },
792
/* adc Rx,#$imm8 */
793
  {
794
    XSTORMY16_INSN_ADCIMM8, "adcimm8", "adc", 16,
795
    { 0, { { { (1<<MACH_BASE), 0 } } } }
796
  },
797
/* adc $Rd,#$imm16 */
798
  {
799
    XSTORMY16_INSN_ADCGRIMM16, "adcgrimm16", "adc", 32,
800
    { 0, { { { (1<<MACH_BASE), 0 } } } }
801
  },
802
/* sub $Rd,$Rs */
803
  {
804
    XSTORMY16_INSN_SUBGRGR, "subgrgr", "sub", 16,
805
    { 0, { { { (1<<MACH_BASE), 0 } } } }
806
  },
807
/* sub $Rd,#$imm4 */
808
  {
809
    XSTORMY16_INSN_SUBGRIMM4, "subgrimm4", "sub", 16,
810
    { 0, { { { (1<<MACH_BASE), 0 } } } }
811
  },
812
/* sub Rx,#$imm8 */
813
  {
814
    XSTORMY16_INSN_SUBIMM8, "subimm8", "sub", 16,
815
    { 0, { { { (1<<MACH_BASE), 0 } } } }
816
  },
817
/* sub $Rd,#$imm16 */
818
  {
819
    XSTORMY16_INSN_SUBGRIMM16, "subgrimm16", "sub", 32,
820
    { 0, { { { (1<<MACH_BASE), 0 } } } }
821
  },
822
/* sbc $Rd,$Rs */
823
  {
824
    XSTORMY16_INSN_SBCGRGR, "sbcgrgr", "sbc", 16,
825
    { 0, { { { (1<<MACH_BASE), 0 } } } }
826
  },
827
/* sbc $Rd,#$imm4 */
828
  {
829
    XSTORMY16_INSN_SBCGRIMM4, "sbcgrimm4", "sbc", 16,
830
    { 0, { { { (1<<MACH_BASE), 0 } } } }
831
  },
832
/* sbc Rx,#$imm8 */
833
  {
834
    XSTORMY16_INSN_SBCGRIMM8, "sbcgrimm8", "sbc", 16,
835
    { 0, { { { (1<<MACH_BASE), 0 } } } }
836
  },
837
/* sbc $Rd,#$imm16 */
838
  {
839
    XSTORMY16_INSN_SBCGRIMM16, "sbcgrimm16", "sbc", 32,
840
    { 0, { { { (1<<MACH_BASE), 0 } } } }
841
  },
842
/* inc $Rd,#$imm2 */
843
  {
844
    XSTORMY16_INSN_INCGRIMM2, "incgrimm2", "inc", 16,
845
    { 0, { { { (1<<MACH_BASE), 0 } } } }
846
  },
847
/* dec $Rd,#$imm2 */
848
  {
849
    XSTORMY16_INSN_DECGRIMM2, "decgrimm2", "dec", 16,
850
    { 0, { { { (1<<MACH_BASE), 0 } } } }
851
  },
852
/* rrc $Rd,$Rs */
853
  {
854
    XSTORMY16_INSN_RRCGRGR, "rrcgrgr", "rrc", 16,
855
    { 0, { { { (1<<MACH_BASE), 0 } } } }
856
  },
857
/* rrc $Rd,#$imm4 */
858
  {
859
    XSTORMY16_INSN_RRCGRIMM4, "rrcgrimm4", "rrc", 16,
860
    { 0, { { { (1<<MACH_BASE), 0 } } } }
861
  },
862
/* rlc $Rd,$Rs */
863
  {
864
    XSTORMY16_INSN_RLCGRGR, "rlcgrgr", "rlc", 16,
865
    { 0, { { { (1<<MACH_BASE), 0 } } } }
866
  },
867
/* rlc $Rd,#$imm4 */
868
  {
869
    XSTORMY16_INSN_RLCGRIMM4, "rlcgrimm4", "rlc", 16,
870
    { 0, { { { (1<<MACH_BASE), 0 } } } }
871
  },
872
/* shr $Rd,$Rs */
873
  {
874
    XSTORMY16_INSN_SHRGRGR, "shrgrgr", "shr", 16,
875
    { 0, { { { (1<<MACH_BASE), 0 } } } }
876
  },
877
/* shr $Rd,#$imm4 */
878
  {
879
    XSTORMY16_INSN_SHRGRIMM, "shrgrimm", "shr", 16,
880
    { 0, { { { (1<<MACH_BASE), 0 } } } }
881
  },
882
/* shl $Rd,$Rs */
883
  {
884
    XSTORMY16_INSN_SHLGRGR, "shlgrgr", "shl", 16,
885
    { 0, { { { (1<<MACH_BASE), 0 } } } }
886
  },
887
/* shl $Rd,#$imm4 */
888
  {
889
    XSTORMY16_INSN_SHLGRIMM, "shlgrimm", "shl", 16,
890
    { 0, { { { (1<<MACH_BASE), 0 } } } }
891
  },
892
/* asr $Rd,$Rs */
893
  {
894
    XSTORMY16_INSN_ASRGRGR, "asrgrgr", "asr", 16,
895
    { 0, { { { (1<<MACH_BASE), 0 } } } }
896
  },
897
/* asr $Rd,#$imm4 */
898
  {
899
    XSTORMY16_INSN_ASRGRIMM, "asrgrimm", "asr", 16,
900
    { 0, { { { (1<<MACH_BASE), 0 } } } }
901
  },
902
/* set1 $Rd,#$imm4 */
903
  {
904
    XSTORMY16_INSN_SET1GRIMM, "set1grimm", "set1", 16,
905
    { 0, { { { (1<<MACH_BASE), 0 } } } }
906
  },
907
/* set1 $Rd,$Rs */
908
  {
909
    XSTORMY16_INSN_SET1GRGR, "set1grgr", "set1", 16,
910
    { 0, { { { (1<<MACH_BASE), 0 } } } }
911
  },
912
/* set1 $lmem8,#$imm3 */
913
  {
914
    XSTORMY16_INSN_SET1LMEMIMM, "set1lmemimm", "set1", 16,
915
    { 0, { { { (1<<MACH_BASE), 0 } } } }
916
  },
917
/* set1 $hmem8,#$imm3 */
918
  {
919
    XSTORMY16_INSN_SET1HMEMIMM, "set1hmemimm", "set1", 16,
920
    { 0, { { { (1<<MACH_BASE), 0 } } } }
921
  },
922
/* clr1 $Rd,#$imm4 */
923
  {
924
    XSTORMY16_INSN_CLR1GRIMM, "clr1grimm", "clr1", 16,
925
    { 0, { { { (1<<MACH_BASE), 0 } } } }
926
  },
927
/* clr1 $Rd,$Rs */
928
  {
929
    XSTORMY16_INSN_CLR1GRGR, "clr1grgr", "clr1", 16,
930
    { 0, { { { (1<<MACH_BASE), 0 } } } }
931
  },
932
/* clr1 $lmem8,#$imm3 */
933
  {
934
    XSTORMY16_INSN_CLR1LMEMIMM, "clr1lmemimm", "clr1", 16,
935
    { 0, { { { (1<<MACH_BASE), 0 } } } }
936
  },
937
/* clr1 $hmem8,#$imm3 */
938
  {
939
    XSTORMY16_INSN_CLR1HMEMIMM, "clr1hmemimm", "clr1", 16,
940
    { 0, { { { (1<<MACH_BASE), 0 } } } }
941
  },
942
/* cbw $Rd */
943
  {
944
    XSTORMY16_INSN_CBWGR, "cbwgr", "cbw", 16,
945
    { 0, { { { (1<<MACH_BASE), 0 } } } }
946
  },
947
/* rev $Rd */
948
  {
949
    XSTORMY16_INSN_REVGR, "revgr", "rev", 16,
950
    { 0, { { { (1<<MACH_BASE), 0 } } } }
951
  },
952
/* b$bcond5 $Rd,$Rs,$rel12 */
953
  {
954
    XSTORMY16_INSN_BCCGRGR, "bccgrgr", "b", 32,
955
    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
956
  },
957
/* b$bcond5 $Rm,#$imm8,$rel12 */
958
  {
959
    XSTORMY16_INSN_BCCGRIMM8, "bccgrimm8", "b", 32,
960
    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
961
  },
962
/* b$bcond2 Rx,#$imm16,${rel8-4} */
963
  {
964
    XSTORMY16_INSN_BCCIMM16, "bccimm16", "b", 32,
965
    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
966
  },
967
/* bn $Rd,#$imm4,$rel12 */
968
  {
969
    XSTORMY16_INSN_BNGRIMM4, "bngrimm4", "bn", 32,
970
    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
971
  },
972
/* bn $Rd,$Rs,$rel12 */
973
  {
974
    XSTORMY16_INSN_BNGRGR, "bngrgr", "bn", 32,
975
    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
976
  },
977
/* bn $lmem8,#$imm3b,$rel12 */
978
  {
979
    XSTORMY16_INSN_BNLMEMIMM, "bnlmemimm", "bn", 32,
980
    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
981
  },
982
/* bn $hmem8,#$imm3b,$rel12 */
983
  {
984
    XSTORMY16_INSN_BNHMEMIMM, "bnhmemimm", "bn", 32,
985
    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
986
  },
987
/* bp $Rd,#$imm4,$rel12 */
988
  {
989
    XSTORMY16_INSN_BPGRIMM4, "bpgrimm4", "bp", 32,
990
    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
991
  },
992
/* bp $Rd,$Rs,$rel12 */
993
  {
994
    XSTORMY16_INSN_BPGRGR, "bpgrgr", "bp", 32,
995
    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
996
  },
997
/* bp $lmem8,#$imm3b,$rel12 */
998
  {
999
    XSTORMY16_INSN_BPLMEMIMM, "bplmemimm", "bp", 32,
1000
    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1001
  },
1002
/* bp $hmem8,#$imm3b,$rel12 */
1003
  {
1004
    XSTORMY16_INSN_BPHMEMIMM, "bphmemimm", "bp", 32,
1005
    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1006
  },
1007
/* b$bcond2 ${rel8-2} */
1008
  {
1009
    XSTORMY16_INSN_BCC, "bcc", "b", 16,
1010
    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1011
  },
1012
/* br $Rd */
1013
  {
1014
    XSTORMY16_INSN_BGR, "bgr", "br", 16,
1015
    { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1016
  },
1017
/* br $rel12a */
1018
  {
1019
    XSTORMY16_INSN_BR, "br", "br", 16,
1020
    { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1021
  },
1022
/* jmp $Rbj,$Rd */
1023
  {
1024
    XSTORMY16_INSN_JMP, "jmp", "jmp", 16,
1025
    { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1026
  },
1027
/* jmpf $abs24 */
1028
  {
1029
    XSTORMY16_INSN_JMPF, "jmpf", "jmpf", 32,
1030
    { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1031
  },
1032
/* callr $Rd */
1033
  {
1034
    XSTORMY16_INSN_CALLRGR, "callrgr", "callr", 16,
1035
    { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1036
  },
1037
/* callr $rel12a */
1038
  {
1039
    XSTORMY16_INSN_CALLRIMM, "callrimm", "callr", 16,
1040
    { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1041
  },
1042
/* call $Rbj,$Rd */
1043
  {
1044
    XSTORMY16_INSN_CALLGR, "callgr", "call", 16,
1045
    { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1046
  },
1047
/* callf $abs24 */
1048
  {
1049
    XSTORMY16_INSN_CALLFIMM, "callfimm", "callf", 32,
1050
    { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1051
  },
1052
/* icallr $Rd */
1053
  {
1054
    XSTORMY16_INSN_ICALLRGR, "icallrgr", "icallr", 16,
1055
    { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1056
  },
1057
/* icall $Rbj,$Rd */
1058
  {
1059
    XSTORMY16_INSN_ICALLGR, "icallgr", "icall", 16,
1060
    { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1061
  },
1062
/* icallf $abs24 */
1063
  {
1064
    XSTORMY16_INSN_ICALLFIMM, "icallfimm", "icallf", 32,
1065
    { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1066
  },
1067
/* iret */
1068
  {
1069
    XSTORMY16_INSN_IRET, "iret", "iret", 16,
1070
    { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1071
  },
1072
/* ret */
1073
  {
1074
    XSTORMY16_INSN_RET, "ret", "ret", 16,
1075
    { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1076
  },
1077
/* mul */
1078
  {
1079
    XSTORMY16_INSN_MUL, "mul", "mul", 16,
1080
    { 0, { { { (1<<MACH_BASE), 0 } } } }
1081
  },
1082
/* div */
1083
  {
1084
    XSTORMY16_INSN_DIV, "div", "div", 16,
1085
    { 0, { { { (1<<MACH_BASE), 0 } } } }
1086
  },
1087
/* sdiv */
1088
  {
1089
    XSTORMY16_INSN_SDIV, "sdiv", "sdiv", 16,
1090
    { 0, { { { (1<<MACH_BASE), 0 } } } }
1091
  },
1092
/* sdivlh */
1093
  {
1094
    XSTORMY16_INSN_SDIVLH, "sdivlh", "sdivlh", 16,
1095
    { 0, { { { (1<<MACH_BASE), 0 } } } }
1096
  },
1097
/* divlh */
1098
  {
1099
    XSTORMY16_INSN_DIVLH, "divlh", "divlh", 16,
1100
    { 0, { { { (1<<MACH_BASE), 0 } } } }
1101
  },
1102
/* reset */
1103
  {
1104
    XSTORMY16_INSN_RESET, "reset", "reset", 16,
1105
    { 0, { { { (1<<MACH_BASE), 0 } } } }
1106
  },
1107
/* nop */
1108
  {
1109
    XSTORMY16_INSN_NOP, "nop", "nop", 16,
1110
    { 0, { { { (1<<MACH_BASE), 0 } } } }
1111
  },
1112
/* halt */
1113
  {
1114
    XSTORMY16_INSN_HALT, "halt", "halt", 16,
1115
    { 0, { { { (1<<MACH_BASE), 0 } } } }
1116
  },
1117
/* hold */
1118
  {
1119
    XSTORMY16_INSN_HOLD, "hold", "hold", 16,
1120
    { 0, { { { (1<<MACH_BASE), 0 } } } }
1121
  },
1122
/* holdx */
1123
  {
1124
    XSTORMY16_INSN_HOLDX, "holdx", "holdx", 16,
1125
    { 0, { { { (1<<MACH_BASE), 0 } } } }
1126
  },
1127
/* brk */
1128
  {
1129
    XSTORMY16_INSN_BRK, "brk", "brk", 16,
1130
    { 0, { { { (1<<MACH_BASE), 0 } } } }
1131
  },
1132
/* --unused-- */
1133
  {
1134
    XSTORMY16_INSN_SYSCALL, "syscall", "--unused--", 16,
1135
    { 0, { { { (1<<MACH_BASE), 0 } } } }
1136
  },
1137
};
1138
 
1139
#undef OP
1140
#undef A
1141
 
1142
/* Initialize anything needed to be done once, before any cpu_open call.  */
1143
 
1144
static void
1145
init_tables (void)
1146
{
1147
}
1148
 
1149
static const CGEN_MACH * lookup_mach_via_bfd_name (const CGEN_MACH *, const char *);
1150
static void build_hw_table      (CGEN_CPU_TABLE *);
1151
static void build_ifield_table  (CGEN_CPU_TABLE *);
1152
static void build_operand_table (CGEN_CPU_TABLE *);
1153
static void build_insn_table    (CGEN_CPU_TABLE *);
1154
static void xstormy16_cgen_rebuild_tables (CGEN_CPU_TABLE *);
1155
 
1156
/* Subroutine of xstormy16_cgen_cpu_open to look up a mach via its bfd name.  */
1157
 
1158
static const CGEN_MACH *
1159
lookup_mach_via_bfd_name (const CGEN_MACH *table, const char *name)
1160
{
1161
  while (table->name)
1162
    {
1163
      if (strcmp (name, table->bfd_name) == 0)
1164
        return table;
1165
      ++table;
1166
    }
1167
  abort ();
1168
}
1169
 
1170
/* Subroutine of xstormy16_cgen_cpu_open to build the hardware table.  */
1171
 
1172
static void
1173
build_hw_table (CGEN_CPU_TABLE *cd)
1174
{
1175
  int i;
1176
  int machs = cd->machs;
1177
  const CGEN_HW_ENTRY *init = & xstormy16_cgen_hw_table[0];
1178
  /* MAX_HW is only an upper bound on the number of selected entries.
1179
     However each entry is indexed by it's enum so there can be holes in
1180
     the table.  */
1181
  const CGEN_HW_ENTRY **selected =
1182
    (const CGEN_HW_ENTRY **) xmalloc (MAX_HW * sizeof (CGEN_HW_ENTRY *));
1183
 
1184
  cd->hw_table.init_entries = init;
1185
  cd->hw_table.entry_size = sizeof (CGEN_HW_ENTRY);
1186
  memset (selected, 0, MAX_HW * sizeof (CGEN_HW_ENTRY *));
1187
  /* ??? For now we just use machs to determine which ones we want.  */
1188
  for (i = 0; init[i].name != NULL; ++i)
1189
    if (CGEN_HW_ATTR_VALUE (&init[i], CGEN_HW_MACH)
1190
        & machs)
1191
      selected[init[i].type] = &init[i];
1192
  cd->hw_table.entries = selected;
1193
  cd->hw_table.num_entries = MAX_HW;
1194
}
1195
 
1196
/* Subroutine of xstormy16_cgen_cpu_open to build the hardware table.  */
1197
 
1198
static void
1199
build_ifield_table (CGEN_CPU_TABLE *cd)
1200
{
1201
  cd->ifld_table = & xstormy16_cgen_ifld_table[0];
1202
}
1203
 
1204
/* Subroutine of xstormy16_cgen_cpu_open to build the hardware table.  */
1205
 
1206
static void
1207
build_operand_table (CGEN_CPU_TABLE *cd)
1208
{
1209
  int i;
1210
  int machs = cd->machs;
1211
  const CGEN_OPERAND *init = & xstormy16_cgen_operand_table[0];
1212
  /* MAX_OPERANDS is only an upper bound on the number of selected entries.
1213
     However each entry is indexed by it's enum so there can be holes in
1214
     the table.  */
1215
  const CGEN_OPERAND **selected = xmalloc (MAX_OPERANDS * sizeof (* selected));
1216
 
1217
  cd->operand_table.init_entries = init;
1218
  cd->operand_table.entry_size = sizeof (CGEN_OPERAND);
1219
  memset (selected, 0, MAX_OPERANDS * sizeof (CGEN_OPERAND *));
1220
  /* ??? For now we just use mach to determine which ones we want.  */
1221
  for (i = 0; init[i].name != NULL; ++i)
1222
    if (CGEN_OPERAND_ATTR_VALUE (&init[i], CGEN_OPERAND_MACH)
1223
        & machs)
1224
      selected[init[i].type] = &init[i];
1225
  cd->operand_table.entries = selected;
1226
  cd->operand_table.num_entries = MAX_OPERANDS;
1227
}
1228
 
1229
/* Subroutine of xstormy16_cgen_cpu_open to build the hardware table.
1230
   ??? This could leave out insns not supported by the specified mach/isa,
1231
   but that would cause errors like "foo only supported by bar" to become
1232
   "unknown insn", so for now we include all insns and require the app to
1233
   do the checking later.
1234
   ??? On the other hand, parsing of such insns may require their hardware or
1235
   operand elements to be in the table [which they mightn't be].  */
1236
 
1237
static void
1238
build_insn_table (CGEN_CPU_TABLE *cd)
1239
{
1240
  int i;
1241
  const CGEN_IBASE *ib = & xstormy16_cgen_insn_table[0];
1242
  CGEN_INSN *insns = xmalloc (MAX_INSNS * sizeof (CGEN_INSN));
1243
 
1244
  memset (insns, 0, MAX_INSNS * sizeof (CGEN_INSN));
1245
  for (i = 0; i < MAX_INSNS; ++i)
1246
    insns[i].base = &ib[i];
1247
  cd->insn_table.init_entries = insns;
1248
  cd->insn_table.entry_size = sizeof (CGEN_IBASE);
1249
  cd->insn_table.num_init_entries = MAX_INSNS;
1250
}
1251
 
1252
/* Subroutine of xstormy16_cgen_cpu_open to rebuild the tables.  */
1253
 
1254
static void
1255
xstormy16_cgen_rebuild_tables (CGEN_CPU_TABLE *cd)
1256
{
1257
  int i;
1258
  CGEN_BITSET *isas = cd->isas;
1259
  unsigned int machs = cd->machs;
1260
 
1261
  cd->int_insn_p = CGEN_INT_INSN_P;
1262
 
1263
  /* Data derived from the isa spec.  */
1264
#define UNSET (CGEN_SIZE_UNKNOWN + 1)
1265
  cd->default_insn_bitsize = UNSET;
1266
  cd->base_insn_bitsize = UNSET;
1267
  cd->min_insn_bitsize = 65535; /* Some ridiculously big number.  */
1268
  cd->max_insn_bitsize = 0;
1269
  for (i = 0; i < MAX_ISAS; ++i)
1270
    if (cgen_bitset_contains (isas, i))
1271
      {
1272
        const CGEN_ISA *isa = & xstormy16_cgen_isa_table[i];
1273
 
1274
        /* Default insn sizes of all selected isas must be
1275
           equal or we set the result to 0, meaning "unknown".  */
1276
        if (cd->default_insn_bitsize == UNSET)
1277
          cd->default_insn_bitsize = isa->default_insn_bitsize;
1278
        else if (isa->default_insn_bitsize == cd->default_insn_bitsize)
1279
          ; /* This is ok.  */
1280
        else
1281
          cd->default_insn_bitsize = CGEN_SIZE_UNKNOWN;
1282
 
1283
        /* Base insn sizes of all selected isas must be equal
1284
           or we set the result to 0, meaning "unknown".  */
1285
        if (cd->base_insn_bitsize == UNSET)
1286
          cd->base_insn_bitsize = isa->base_insn_bitsize;
1287
        else if (isa->base_insn_bitsize == cd->base_insn_bitsize)
1288
          ; /* This is ok.  */
1289
        else
1290
          cd->base_insn_bitsize = CGEN_SIZE_UNKNOWN;
1291
 
1292
        /* Set min,max insn sizes.  */
1293
        if (isa->min_insn_bitsize < cd->min_insn_bitsize)
1294
          cd->min_insn_bitsize = isa->min_insn_bitsize;
1295
        if (isa->max_insn_bitsize > cd->max_insn_bitsize)
1296
          cd->max_insn_bitsize = isa->max_insn_bitsize;
1297
      }
1298
 
1299
  /* Data derived from the mach spec.  */
1300
  for (i = 0; i < MAX_MACHS; ++i)
1301
    if (((1 << i) & machs) != 0)
1302
      {
1303
        const CGEN_MACH *mach = & xstormy16_cgen_mach_table[i];
1304
 
1305
        if (mach->insn_chunk_bitsize != 0)
1306
        {
1307
          if (cd->insn_chunk_bitsize != 0 && cd->insn_chunk_bitsize != mach->insn_chunk_bitsize)
1308
            {
1309
              fprintf (stderr, "xstormy16_cgen_rebuild_tables: conflicting insn-chunk-bitsize values: `%d' vs. `%d'\n",
1310
                       cd->insn_chunk_bitsize, mach->insn_chunk_bitsize);
1311
              abort ();
1312
            }
1313
 
1314
          cd->insn_chunk_bitsize = mach->insn_chunk_bitsize;
1315
        }
1316
      }
1317
 
1318
  /* Determine which hw elements are used by MACH.  */
1319
  build_hw_table (cd);
1320
 
1321
  /* Build the ifield table.  */
1322
  build_ifield_table (cd);
1323
 
1324
  /* Determine which operands are used by MACH/ISA.  */
1325
  build_operand_table (cd);
1326
 
1327
  /* Build the instruction table.  */
1328
  build_insn_table (cd);
1329
}
1330
 
1331
/* Initialize a cpu table and return a descriptor.
1332
   It's much like opening a file, and must be the first function called.
1333
   The arguments are a set of (type/value) pairs, terminated with
1334
   CGEN_CPU_OPEN_END.
1335
 
1336
   Currently supported values:
1337
   CGEN_CPU_OPEN_ISAS:    bitmap of values in enum isa_attr
1338
   CGEN_CPU_OPEN_MACHS:   bitmap of values in enum mach_attr
1339
   CGEN_CPU_OPEN_BFDMACH: specify 1 mach using bfd name
1340
   CGEN_CPU_OPEN_ENDIAN:  specify endian choice
1341
   CGEN_CPU_OPEN_END:     terminates arguments
1342
 
1343
   ??? Simultaneous multiple isas might not make sense, but it's not (yet)
1344
   precluded.  */
1345
 
1346
CGEN_CPU_DESC
1347
xstormy16_cgen_cpu_open (enum cgen_cpu_open_arg arg_type, ...)
1348
{
1349
  CGEN_CPU_TABLE *cd = (CGEN_CPU_TABLE *) xmalloc (sizeof (CGEN_CPU_TABLE));
1350
  static int init_p;
1351
  CGEN_BITSET *isas = 0;  /* 0 = "unspecified" */
1352
  unsigned int machs = 0; /* 0 = "unspecified" */
1353
  enum cgen_endian endian = CGEN_ENDIAN_UNKNOWN;
1354
  va_list ap;
1355
 
1356
  if (! init_p)
1357
    {
1358
      init_tables ();
1359
      init_p = 1;
1360
    }
1361
 
1362
  memset (cd, 0, sizeof (*cd));
1363
 
1364
  va_start (ap, arg_type);
1365
  while (arg_type != CGEN_CPU_OPEN_END)
1366
    {
1367
      switch (arg_type)
1368
        {
1369
        case CGEN_CPU_OPEN_ISAS :
1370
          isas = va_arg (ap, CGEN_BITSET *);
1371
          break;
1372
        case CGEN_CPU_OPEN_MACHS :
1373
          machs = va_arg (ap, unsigned int);
1374
          break;
1375
        case CGEN_CPU_OPEN_BFDMACH :
1376
          {
1377
            const char *name = va_arg (ap, const char *);
1378
            const CGEN_MACH *mach =
1379
              lookup_mach_via_bfd_name (xstormy16_cgen_mach_table, name);
1380
 
1381
            machs |= 1 << mach->num;
1382
            break;
1383
          }
1384
        case CGEN_CPU_OPEN_ENDIAN :
1385
          endian = va_arg (ap, enum cgen_endian);
1386
          break;
1387
        default :
1388
          fprintf (stderr, "xstormy16_cgen_cpu_open: unsupported argument `%d'\n",
1389
                   arg_type);
1390
          abort (); /* ??? return NULL? */
1391
        }
1392
      arg_type = va_arg (ap, enum cgen_cpu_open_arg);
1393
    }
1394
  va_end (ap);
1395
 
1396
  /* Mach unspecified means "all".  */
1397
  if (machs == 0)
1398
    machs = (1 << MAX_MACHS) - 1;
1399
  /* Base mach is always selected.  */
1400
  machs |= 1;
1401
  if (endian == CGEN_ENDIAN_UNKNOWN)
1402
    {
1403
      /* ??? If target has only one, could have a default.  */
1404
      fprintf (stderr, "xstormy16_cgen_cpu_open: no endianness specified\n");
1405
      abort ();
1406
    }
1407
 
1408
  cd->isas = cgen_bitset_copy (isas);
1409
  cd->machs = machs;
1410
  cd->endian = endian;
1411
  /* FIXME: for the sparc case we can determine insn-endianness statically.
1412
     The worry here is where both data and insn endian can be independently
1413
     chosen, in which case this function will need another argument.
1414
     Actually, will want to allow for more arguments in the future anyway.  */
1415
  cd->insn_endian = endian;
1416
 
1417
  /* Table (re)builder.  */
1418
  cd->rebuild_tables = xstormy16_cgen_rebuild_tables;
1419
  xstormy16_cgen_rebuild_tables (cd);
1420
 
1421
  /* Default to not allowing signed overflow.  */
1422
  cd->signed_overflow_ok_p = 0;
1423
 
1424
  return (CGEN_CPU_DESC) cd;
1425
}
1426
 
1427
/* Cover fn to xstormy16_cgen_cpu_open to handle the simple case of 1 isa, 1 mach.
1428
   MACH_NAME is the bfd name of the mach.  */
1429
 
1430
CGEN_CPU_DESC
1431
xstormy16_cgen_cpu_open_1 (const char *mach_name, enum cgen_endian endian)
1432
{
1433
  return xstormy16_cgen_cpu_open (CGEN_CPU_OPEN_BFDMACH, mach_name,
1434
                               CGEN_CPU_OPEN_ENDIAN, endian,
1435
                               CGEN_CPU_OPEN_END);
1436
}
1437
 
1438
/* Close a cpu table.
1439
   ??? This can live in a machine independent file, but there's currently
1440
   no place to put this file (there's no libcgen).  libopcodes is the wrong
1441
   place as some simulator ports use this but they don't use libopcodes.  */
1442
 
1443
void
1444
xstormy16_cgen_cpu_close (CGEN_CPU_DESC cd)
1445
{
1446
  unsigned int i;
1447
  const CGEN_INSN *insns;
1448
 
1449
  if (cd->macro_insn_table.init_entries)
1450
    {
1451
      insns = cd->macro_insn_table.init_entries;
1452
      for (i = 0; i < cd->macro_insn_table.num_init_entries; ++i, ++insns)
1453
        if (CGEN_INSN_RX ((insns)))
1454
          regfree (CGEN_INSN_RX (insns));
1455
    }
1456
 
1457
  if (cd->insn_table.init_entries)
1458
    {
1459
      insns = cd->insn_table.init_entries;
1460
      for (i = 0; i < cd->insn_table.num_init_entries; ++i, ++insns)
1461
        if (CGEN_INSN_RX (insns))
1462
          regfree (CGEN_INSN_RX (insns));
1463
    }
1464
 
1465
  if (cd->macro_insn_table.init_entries)
1466
    free ((CGEN_INSN *) cd->macro_insn_table.init_entries);
1467
 
1468
  if (cd->insn_table.init_entries)
1469
    free ((CGEN_INSN *) cd->insn_table.init_entries);
1470
 
1471
  if (cd->hw_table.entries)
1472
    free ((CGEN_HW_ENTRY *) cd->hw_table.entries);
1473
 
1474
  if (cd->operand_table.entries)
1475
    free ((CGEN_HW_ENTRY *) cd->operand_table.entries);
1476
 
1477
  free (cd);
1478
}
1479
 

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