OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [gnu-stable/] [gdb-7.2/] [sim/] [h8300/] [inst.h] - Blame information for rev 866

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 330 jeremybenn
#define DEBUG
2
 
3
/* These define the size of main memory for the simulator.
4
 
5
   Note the size of main memory for the H8/300H is only 256k.  Keeping it
6
   small makes the simulator run much faster and consume less memory.
7
 
8
   The linker knows about the limited size of the simulator's main memory
9
   on the H8/300H (via the h8300h.sc linker script).  So if you change
10
   H8300H_MSIZE, be sure to fix the linker script too.
11
 
12
   Also note that there's a separate "eightbit" area aside from main
13
   memory.  For simplicity, the simulator assumes any data memory reference
14
   outside of main memory refers to the eightbit area (in theory, this
15
   can only happen when simulating H8/300H programs).  We make no attempt
16
   to catch overlapping addresses, wrapped addresses, etc etc.  */
17
#define H8300_MSIZE (1 << 16)
18
 
19
/* avolkov:
20
   Next 2 macros are ugly for any workstation, but while they're work.
21
   Memory size MUST be configurable.  */
22
#define H8300H_MSIZE (1 << 18) 
23
#define H8300S_MSIZE (1 << 24) 
24
 
25
#define CSIZE 1000
26
 
27
/* Local register names */
28
typedef enum
29
{
30
  R0, R1, R2, R3, R4, R5, R6, R7,
31
  R_ZERO,
32
  R_PC,
33
  R_CCR,
34
  R_EXR,
35
  R_HARD_0,
36
  R_LAST,
37
} reg_type;
38
 
39
 
40
/* Structure used to describe addressing */
41
 
42
typedef struct
43
{
44
  int type;
45
  int reg;
46
  int literal;
47
} ea_type;
48
 
49
 
50
 
51
typedef struct
52
{
53
  ea_type src;
54
  ea_type dst;
55
  int opcode;
56
  int next_pc;
57
  int oldpc;
58
  int cycles;
59
#ifdef DEBUG
60
struct h8_opcode *op;
61
#endif
62
}
63
decoded_inst;
64
 
65
enum h8300_sim_state {
66
  SIM_STATE_RUNNING, SIM_STATE_EXITED, SIM_STATE_SIGNALLED, SIM_STATE_STOPPED
67
};
68
 
69
/* For Command Line.  */
70
char **ptr_command_line; /* Pointer to Command Line Arguments. */
71
 
72
typedef struct
73
{
74
  enum h8300_sim_state state;
75
  int exception;
76
  unsigned  int regs[9];
77
  int pc;
78
  int ccr;
79
  int exr;
80
 
81
  unsigned char *memory;
82
  unsigned char *eightbit;
83
  unsigned short *cache_idx;
84
  int cache_top;
85
  int maximum;
86
  int csize;
87
  int mask;
88
 
89
  decoded_inst *cache;
90
  int cycles;
91
  int insts;
92
  int ticks;
93
  int compiles;
94
#ifdef ADEBUG
95
  int stats[O_LAST];
96
#endif
97
}
98
cpu_state_type;

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.