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[/] [openrisc/] [trunk/] [gnu-stable/] [gdb-7.2/] [sim/] [m32r/] [traps.c] - Blame information for rev 330

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1 330 jeremybenn
/* m32r exception, interrupt, and trap (EIT) support
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   Copyright (C) 1998, 2003, 2007, 2008, 2009, 2010
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   Free Software Foundation, Inc.
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   Contributed by Cygnus Solutions.
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   This file is part of GDB, the GNU debugger.
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   This program is free software; you can redistribute it and/or modify
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   it under the terms of the GNU General Public License as published by
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   the Free Software Foundation; either version 3 of the License, or
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   (at your option) any later version.
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   This program is distributed in the hope that it will be useful,
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   but WITHOUT ANY WARRANTY; without even the implied warranty of
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   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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   GNU General Public License for more details.
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   You should have received a copy of the GNU General Public License
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   along with this program.  If not, see <http://www.gnu.org/licenses/>.  */
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#include "sim-main.h"
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#include "targ-vals.h"
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#define TRAP_FLUSH_CACHE 12
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/* The semantic code invokes this for invalid (unrecognized) instructions.  */
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SEM_PC
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sim_engine_invalid_insn (SIM_CPU *current_cpu, IADDR cia, SEM_PC pc)
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{
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  SIM_DESC sd = CPU_STATE (current_cpu);
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#if 0
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  if (STATE_ENVIRONMENT (sd) == OPERATING_ENVIRONMENT)
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    {
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      h_bsm_set (current_cpu, h_sm_get (current_cpu));
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      h_bie_set (current_cpu, h_ie_get (current_cpu));
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      h_bcond_set (current_cpu, h_cond_get (current_cpu));
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      /* sm not changed */
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      h_ie_set (current_cpu, 0);
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      h_cond_set (current_cpu, 0);
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      h_bpc_set (current_cpu, cia);
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      sim_engine_restart (CPU_STATE (current_cpu), current_cpu, NULL,
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                          EIT_RSVD_INSN_ADDR);
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    }
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  else
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#endif
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    sim_engine_halt (sd, current_cpu, NULL, cia, sim_stopped, SIM_SIGILL);
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  return pc;
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}
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/* Process an address exception.  */
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void
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m32r_core_signal (SIM_DESC sd, SIM_CPU *current_cpu, sim_cia cia,
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                  unsigned int map, int nr_bytes, address_word addr,
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                  transfer_type transfer, sim_core_signals sig)
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{
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  if (STATE_ENVIRONMENT (sd) == OPERATING_ENVIRONMENT)
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    {
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      m32rbf_h_cr_set (current_cpu, H_CR_BBPC,
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                       m32rbf_h_cr_get (current_cpu, H_CR_BPC));
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      switch (MACH_NUM (CPU_MACH (current_cpu)))
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        {
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        case MACH_M32R:
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          m32rbf_h_bpsw_set (current_cpu, m32rbf_h_psw_get (current_cpu));
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          /* sm not changed.  */
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          m32rbf_h_psw_set (current_cpu, m32rbf_h_psw_get (current_cpu) & 0x80);
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          break;
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        case MACH_M32RX:
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          m32rxf_h_bpsw_set (current_cpu, m32rxf_h_psw_get (current_cpu));
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          /* sm not changed.  */
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          m32rxf_h_psw_set (current_cpu, m32rxf_h_psw_get (current_cpu) & 0x80);
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          break;
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        case MACH_M32R2:
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          m32r2f_h_bpsw_set (current_cpu, m32r2f_h_psw_get (current_cpu));
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          /* sm not changed.  */
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          m32r2f_h_psw_set (current_cpu, m32r2f_h_psw_get (current_cpu) & 0x80);
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          break;
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        default:
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          abort ();
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        }
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      m32rbf_h_cr_set (current_cpu, H_CR_BPC, cia);
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      sim_engine_restart (CPU_STATE (current_cpu), current_cpu, NULL,
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                          EIT_ADDR_EXCP_ADDR);
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    }
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  else
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    sim_core_signal (sd, current_cpu, cia, map, nr_bytes, addr,
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                     transfer, sig);
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}
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/* Read/write functions for system call interface.  */
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static int
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syscall_read_mem (host_callback *cb, struct cb_syscall *sc,
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                  unsigned long taddr, char *buf, int bytes)
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{
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  SIM_DESC sd = (SIM_DESC) sc->p1;
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  SIM_CPU *cpu = (SIM_CPU *) sc->p2;
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  return sim_core_read_buffer (sd, cpu, read_map, buf, taddr, bytes);
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}
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static int
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syscall_write_mem (host_callback *cb, struct cb_syscall *sc,
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                   unsigned long taddr, const char *buf, int bytes)
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{
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  SIM_DESC sd = (SIM_DESC) sc->p1;
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  SIM_CPU *cpu = (SIM_CPU *) sc->p2;
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  return sim_core_write_buffer (sd, cpu, write_map, buf, taddr, bytes);
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}
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/* Trap support.
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   The result is the pc address to continue at.
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   Preprocessing like saving the various registers has already been done.  */
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USI
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m32r_trap (SIM_CPU *current_cpu, PCADDR pc, int num)
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{
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  SIM_DESC sd = CPU_STATE (current_cpu);
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  host_callback *cb = STATE_CALLBACK (sd);
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#ifdef SIM_HAVE_BREAKPOINTS
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  /* Check for breakpoints "owned" by the simulator first, regardless
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     of --environment.  */
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  if (num == TRAP_BREAKPOINT)
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    {
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      /* First try sim-break.c.  If it's a breakpoint the simulator "owns"
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         it doesn't return.  Otherwise it returns and let's us try.  */
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      sim_handle_breakpoint (sd, current_cpu, pc);
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      /* Fall through.  */
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    }
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#endif
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  if (STATE_ENVIRONMENT (sd) == OPERATING_ENVIRONMENT)
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    {
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      /* The new pc is the trap vector entry.
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         We assume there's a branch there to some handler.
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         Use cr5 as EVB (EIT Vector Base) register.  */
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      /* USI new_pc = EIT_TRAP_BASE_ADDR + num * 4; */
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      USI new_pc = m32rbf_h_cr_get (current_cpu, 5) + 0x40 + num * 4;
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      return new_pc;
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    }
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  switch (num)
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    {
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    case TRAP_SYSCALL :
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      {
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        CB_SYSCALL s;
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        CB_SYSCALL_INIT (&s);
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        s.func = m32rbf_h_gr_get (current_cpu, 0);
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        s.arg1 = m32rbf_h_gr_get (current_cpu, 1);
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        s.arg2 = m32rbf_h_gr_get (current_cpu, 2);
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        s.arg3 = m32rbf_h_gr_get (current_cpu, 3);
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        if (s.func == TARGET_SYS_exit)
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          {
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            sim_engine_halt (sd, current_cpu, NULL, pc, sim_exited, s.arg1);
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          }
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        s.p1 = (PTR) sd;
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        s.p2 = (PTR) current_cpu;
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        s.read_mem = syscall_read_mem;
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        s.write_mem = syscall_write_mem;
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        cb_syscall (cb, &s);
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        m32rbf_h_gr_set (current_cpu, 2, s.errcode);
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        m32rbf_h_gr_set (current_cpu, 0, s.result);
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        m32rbf_h_gr_set (current_cpu, 1, s.result2);
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        break;
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      }
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    case TRAP_BREAKPOINT:
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      sim_engine_halt (sd, current_cpu, NULL, pc,
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                       sim_stopped, SIM_SIGTRAP);
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      break;
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    case TRAP_FLUSH_CACHE:
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      /* Do nothing.  */
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      break;
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    default :
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      {
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        /* USI new_pc = EIT_TRAP_BASE_ADDR + num * 4; */
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        /* Use cr5 as EVB (EIT Vector Base) register.  */
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        USI new_pc = m32rbf_h_cr_get (current_cpu, 5) + 0x40 + num * 4;
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        return new_pc;
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      }
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    }
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  /* Fake an "rte" insn.  */
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  /* FIXME: Should duplicate all of rte processing.  */
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  return (pc & -4) + 4;
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}

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