OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [gnu-stable/] [gdb-7.2/] [sim/] [mips/] [m16run.c] - Blame information for rev 866

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 330 jeremybenn
/*  This file is part of the program psim.
2
 
3
    Copyright (C) 1998, Andrew Cagney <cagney@highland.com.au>
4
 
5
    This program is free software; you can redistribute it and/or modify
6
    it under the terms of the GNU General Public License as published by
7
    the Free Software Foundation; either version 2 of the License, or
8
    (at your option) any later version.
9
 
10
    This program is distributed in the hope that it will be useful,
11
    but WITHOUT ANY WARRANTY; without even the implied warranty of
12
    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
13
    GNU General Public License for more details.
14
 
15
    You should have received a copy of the GNU General Public License
16
    along with this program; if not, write to the Free Software
17
    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
18
 
19
    */
20
 
21
#include "sim-main.h"
22
#include "m16_idecode.h"
23
#include "m32_idecode.h"
24
#include "bfd.h"
25
 
26
 
27
#define SD sd
28
#define CPU cpu
29
 
30
void
31
sim_engine_run (SIM_DESC sd,
32
                int next_cpu_nr,
33
                int nr_cpus, /* ignore */
34
                int siggnal) /* ignore */
35
{
36
  sim_cpu *cpu = STATE_CPU (sd, next_cpu_nr);
37
  address_word cia = CIA_GET (cpu);
38
 
39
  while (1)
40
    {
41
      address_word nia;
42
 
43
#if defined (ENGINE_ISSUE_PREFIX_HOOK)
44
      ENGINE_ISSUE_PREFIX_HOOK ();
45
#endif
46
 
47
      if ((cia & 1))
48
        {
49
          m16_instruction_word instruction_0 = IMEM16 (cia);
50
          nia = m16_idecode_issue (sd, instruction_0, cia);
51
        }
52
      else
53
        {
54
          m32_instruction_word instruction_0 = IMEM32 (cia);
55
          nia = m32_idecode_issue (sd, instruction_0, cia);
56
        }
57
 
58
#if defined (ENGINE_ISSUE_POSTFIX_HOOK)
59
      ENGINE_ISSUE_POSTFIX_HOOK ();
60
#endif
61
 
62
      /* Update the instruction address */
63
      cia = nia;
64
 
65
      /* process any events */
66
      if (sim_events_tick (sd))
67
        {
68
          CIA_SET (CPU, cia);
69
          sim_events_process (sd);
70
          cia = CIA_GET (CPU);
71
        }
72
 
73
    }
74
}

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.