OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [gnu-stable/] [gdb-7.2/] [sim/] [moxie/] [sim-main.h] - Blame information for rev 853

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 330 jeremybenn
/* Moxie Simulator definition.
2
   Copyright (C) 2009, 2010 Free Software Foundation, Inc.
3
   Contributed by Anthony Green <green@moxielogic.com>
4
 
5
This file is part of GDB, the GNU debugger.
6
 
7
This program is free software; you can redistribute it and/or modify
8
it under the terms of the GNU General Public License as published by
9
the Free Software Foundation; either version 3 of the License, or
10
(at your option) any later version.
11
 
12
This program is distributed in the hope that it will be useful,
13
but WITHOUT ANY WARRANTY; without even the implied warranty of
14
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
15
GNU General Public License for more details.
16
 
17
You should have received a copy of the GNU General Public License
18
along with this program.  If not, see <http://www.gnu.org/licenses/>.  */
19
 
20
#ifndef SIM_MAIN_H
21
#define SIM_MAIN_H
22
 
23
#define SIM_HAVE_BIENDIAN
24
 
25
#include "sim-basics.h"
26
 
27
typedef address_word sim_cia;
28
 
29
#include "sim-base.h"
30
#include "bfd.h"
31
 
32
#define PCIDX 17
33
 
34
struct _sim_cpu {
35
 
36
  /* The following are internal simulator state variables: */
37
#define CIA_GET(CPU) ((CPU)->registers[PCIDX] + 0)
38
#define CIA_SET(CPU,CIA) ((CPU)->registers[PCIDX] = (CIA))
39
 
40
/* To keep this default simulator simple, and fast, we use a direct
41
   vector of registers. The internal simulator engine then uses
42
   manifests to access the correct slot. */
43
 
44
  unsigned_word registers[19];
45
 
46
  sim_cpu_base base;
47
};
48
 
49
struct sim_state {
50
 
51
  sim_cpu cpu[MAX_NR_PROCESSORS];
52
#if (WITH_SMP)
53
#define STATE_CPU(sd,n) (&(sd)->cpu[n])
54
#else
55
#define STATE_CPU(sd,n) (&(sd)->cpu[0])
56
#endif
57
 
58
  sim_state_base base;
59
};
60
 
61
#endif
62
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.