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[/] [openrisc/] [trunk/] [gnu-stable/] [gdb-7.2/] [sim/] [ppc/] [interrupts.h] - Blame information for rev 866

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1 330 jeremybenn
/*  This file is part of the program psim.
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    Copyright (C) 1994-1995, Andrew Cagney <cagney@highland.com.au>
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    This program is free software; you can redistribute it and/or modify
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    it under the terms of the GNU General Public License as published by
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    the Free Software Foundation; either version 2 of the License, or
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    (at your option) any later version.
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    This program is distributed in the hope that it will be useful,
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    but WITHOUT ANY WARRANTY; without even the implied warranty of
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    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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    GNU General Public License for more details.
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    You should have received a copy of the GNU General Public License
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    along with this program; if not, write to the Free Software
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    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
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    */
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#ifndef _INTERRUPTS_H_
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#define _INTERRUPTS_H_
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/* Interrupts:
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   The code below handles two different types of interrupts.
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   Synchronous and Asynchronous.
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   Synchronous:
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   Interrupts that must immediately force either an abort or restart
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   of a current instruction are implemented by forcing an instruction
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   restart. (or to put it another way, long jump).  In looking at the
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   code it may occure to you that, for some interrupts, they could
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   return instead of restarting the cpu (eg system_call).  While true
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   (it once was like that) I've decided to make the behavour of all
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   interrupt routines roughly identical.
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   Because, a cpu's recorded state (ie what is in the cpu structure)
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   is allowed to lag behind the cpu's true current state (eg PC not
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   updated) sycnronous interrupt handers are parameterized with the
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   the cpu being interrupted so that, as part of moddeling the
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   interrupt, the cpu's state can be updated.
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   Asynchronous:
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   Interrupts such as reset or external exception are delivered using
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   more normal (returning) functions.  It is assumed that these
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   functions are called out side of the normal processor execution
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   cycle. */
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/* Software generated interrupts.
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   The below are generated by software driven events.  For instance,
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   an invalid instruction or access (virtual or physical) to an
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   invalid address */
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typedef enum {
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  direct_store_storage_interrupt,
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  hash_table_miss_storage_interrupt,
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  protection_violation_storage_interrupt,
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  earwax_violation_storage_interrupt,
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  segment_table_miss_storage_interrupt,
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  earwax_disabled_storage_interrupt,
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  vea_storage_interrupt,
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} storage_interrupt_reasons;
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INLINE_INTERRUPTS\
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(void) data_storage_interrupt
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(cpu *processor,
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 unsigned_word cia,
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 unsigned_word ea,
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 storage_interrupt_reasons reason,
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 int is_store);
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INLINE_INTERRUPTS\
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(void) instruction_storage_interrupt
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(cpu *processor,
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 unsigned_word cia,
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 storage_interrupt_reasons reason);
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INLINE_INTERRUPTS\
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(void) alignment_interrupt
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(cpu *processor,
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 unsigned_word cia,
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 unsigned_word ra);
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typedef enum {
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  floating_point_enabled_program_interrupt,
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  illegal_instruction_program_interrupt,
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  privileged_instruction_program_interrupt,
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  trap_program_interrupt,
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  optional_instruction_program_interrupt, /* subset of illegal instruction */
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  mpc860c0_instruction_program_interrupt, /* fwd br, taken but not predicted, near EO page */
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  nr_program_interrupt_reasons
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} program_interrupt_reasons;
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INLINE_INTERRUPTS\
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(void) program_interrupt
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(cpu *processor,
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 unsigned_word cia,
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 program_interrupt_reasons reason);
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INLINE_INTERRUPTS\
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(void) floating_point_unavailable_interrupt
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(cpu *processor,
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 unsigned_word cia);
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INLINE_INTERRUPTS\
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(void) system_call_interrupt
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(cpu *processor,
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 unsigned_word cia);
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INLINE_INTERRUPTS\
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(void) floating_point_assist_interrupt
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(cpu *processor,
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 unsigned_word cia);
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INLINE_INTERRUPTS\
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(void) machine_check_interrupt
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(cpu *processor,
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 unsigned_word cia);
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/* Hardware generated interrupts:
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   These asynchronous hardware generated interrupts may be called at
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   any time.  It is the responsibility of this (the interrupts) module
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   to ensure that interrupts are delivered correctly (when possible).
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   The delivery of these interrupts is controlled by the MSR's
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   external interrupt enable bit.  When ever the MSR's value is
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   changed, the processor must call the check_masked_interrupts()
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   function in case delivery has been made possible.
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   decrementer_interrupt is `edge' sensitive.  Multiple edges arriving
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   before the first edge has been delivered result in only one
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   interrupt.
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   external_interrupt is `level' sensitive.  An external interrupt
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   will only be delivered when the external interrupt port is
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   `asserted'. While interrupts are disabled, the external interrupt
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   can be asserted and then de-asserted without an interrupt
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   eventually being delivered. */
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enum {
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  external_interrupt_pending = 1,
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  decrementer_interrupt_pending = 2,
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};
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typedef struct _interrupts {
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  event_entry_tag delivery_scheduled;
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  int pending_interrupts;
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} interrupts;
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INLINE_INTERRUPTS\
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(void) check_masked_interrupts
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(cpu *processor);
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INLINE_INTERRUPTS\
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(void) decrementer_interrupt
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(cpu *processor);
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INLINE_INTERRUPTS\
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(void) external_interrupt
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(cpu *processor,
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 int is_asserted);
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#endif /* _INTERRUPTS_H_ */

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