OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [gnu-stable/] [gdb-7.2/] [sim/] [ppc/] [ld-cache.h] - Blame information for rev 866

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 330 jeremybenn
/*  This file is part of the program psim.
2
 
3
    Copyright 1994, 1995, 1996, 1997, 2003, Andrew Cagney
4
 
5
    This program is free software; you can redistribute it and/or modify
6
    it under the terms of the GNU General Public License as published by
7
    the Free Software Foundation; either version 2 of the License, or
8
    (at your option) any later version.
9
 
10
    This program is distributed in the hope that it will be useful,
11
    but WITHOUT ANY WARRANTY; without even the implied warranty of
12
    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
13
    GNU General Public License for more details.
14
 
15
    You should have received a copy of the GNU General Public License
16
    along with this program; if not, write to the Free Software
17
    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
18
 
19
    */
20
 
21
/* Instruction unpacking:
22
 
23
   Once the instruction has been decoded, the register (and other)
24
   fields within the instruction need to be extracted.
25
 
26
   The table that follows determines how each field should be treated.
27
   Importantly it considers the case where the extracted field is to
28
   be used immediatly or stored in an instruction cache.
29
 
30
   <type>
31
 
32
   Indicates what to do with the cache entry.  If a cache is to be
33
   used.  SCRATCH and CACHE values are defined when a cache entry is
34
   being filled while CACHE and COMPUTE values are defined in the
35
   semantic code.
36
 
37
   Zero marks the end of the table.  More importantly 1. indicates
38
   that the entry is valid and can be cached. 2. indicates that that
39
   the entry is valid but can not be cached.
40
 
41
   <field_name>
42
 
43
   The field name as given in the instruction spec.
44
 
45
   <derived_name>
46
 
47
   A new name for <field_name> once it has been extracted from the
48
   instruction (and possibly stored in the instruction cache).
49
 
50
   <type>
51
 
52
   String specifying the storage type for <new_name> (the extracted
53
   field>.
54
 
55
   <expression>
56
 
57
   Specifies how to get <new_name> from <old_name>.  If null, old and
58
   new name had better be the same. */
59
 
60
 
61
typedef enum {
62
  scratch_value,
63
  cache_value,
64
  compute_value,
65
} cache_rule_type;
66
 
67
typedef struct _cache_table cache_table;
68
struct _cache_table {
69
  cache_rule_type type;
70
  char *field_name;
71
  char *derived_name;
72
  char *type_def;
73
  char *expression;
74
  table_entry *file_entry;
75
  cache_table *next;
76
};
77
 
78
 
79
extern cache_table *load_cache_table
80
(char *file_name,
81
 int hi_bit_nr);
82
 
83
extern void append_cache_rule
84
(cache_table **table,
85
 char *type,
86
 char *field_name,
87
 char *derived_name,
88
 char *type_def,
89
 char *expression,
90
 table_entry *file_entry);
91
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.