OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [gnu-stable/] [gdb-7.2/] [sim/] [ppc/] [words.h] - Blame information for rev 841

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 330 jeremybenn
/* This file is part of psim (model of the PowerPC(tm) architecture)
2
 
3
   Copyright (C) 1994-1995, Andrew Cagney <cagney@highland.com.au>
4
 
5
   This library is free software; you can redistribute it and/or
6
   modify it under the terms of the GNU Library General Public License
7
   as published by the Free Software Foundation; either version 2 of
8
   the License, or (at your option) any later version.
9
 
10
   This library is distributed in the hope that it will be useful, but
11
   WITHOUT ANY WARRANTY; without even the implied warranty of
12
   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
13
   Library General Public License for more details.
14
 
15
   You should have received a copy of the GNU Library General Public
16
   License along with this library; if not, write to the Free Software
17
   Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
18
 
19
   --
20
 
21
   PowerPC is a trademark of International Business Machines Corporation. */
22
 
23
 
24
/* Basic type sizes for the PowerPC */
25
 
26
#ifndef _WORDS_H_
27
#define _WORDS_H_
28
 
29
/* TYPES:
30
 
31
     natural*   sign determined by host
32
     signed*    signed type of the given size
33
     unsigned*  The corresponding insigned type
34
 
35
   SIZES
36
 
37
     *NN        Size based on the number of bits
38
     *_NN       Size according to the number of bytes
39
     *_word     Size based on the target architecture's word
40
                word size (32/64 bits)
41
     *_cell     Size based on the target architecture's
42
                IEEE 1275 cell size (almost always 32 bits)
43
 
44
*/
45
 
46
 
47
#ifdef HAVE_CONFIG_H
48
#include "config.h"
49
#endif
50
 
51
/* bit based */
52
typedef char natural8;
53
typedef short natural16;
54
typedef int natural32;
55
 
56
typedef signed char signed8;
57
typedef signed short signed16;
58
typedef signed int signed32;
59
 
60
typedef unsigned char unsigned8;
61
typedef unsigned short unsigned16;
62
typedef unsigned int unsigned32;
63
 
64
#ifdef __GNUC__
65
typedef long long natural64;
66
typedef signed long long signed64;
67
typedef unsigned long long unsigned64;
68
#endif
69
 
70
#ifdef _MSC_VER
71
typedef __int64 natural64;
72
typedef signed __int64 signed64;
73
typedef unsigned __int64 unsigned64;
74
#endif 
75
 
76
 
77
/* byte based */
78
typedef natural8 natural_1;
79
typedef natural16 natural_2;
80
typedef natural32 natural_4;
81
typedef natural64 natural_8;
82
 
83
typedef signed8 signed_1;
84
typedef signed16 signed_2;
85
typedef signed32 signed_4;
86
typedef signed64 signed_8;
87
 
88
typedef unsigned8 unsigned_1;
89
typedef unsigned16 unsigned_2;
90
typedef unsigned32 unsigned_4;
91
typedef unsigned64 unsigned_8;
92
 
93
 
94
/* for general work, the following are defined */
95
/* unsigned: >= 32 bits */
96
/* signed:   >= 32 bits */
97
/* long:     >= 32 bits, sign undefined */
98
/* int:      small indicator */
99
 
100
/* target architecture based */
101
#if (WITH_TARGET_WORD_BITSIZE == 64)
102
typedef natural64 natural_word;
103
typedef unsigned64 unsigned_word;
104
typedef signed64 signed_word;
105
#else
106
typedef natural32 natural_word;
107
typedef unsigned32 unsigned_word;
108
typedef signed32 signed_word;
109
#endif
110
 
111
 
112
/* Other instructions */
113
typedef unsigned32 instruction_word;
114
 
115
/* IEEE 1275 cell size - only support 32bit mode at present */
116
typedef natural32 natural_cell;
117
typedef unsigned32 unsigned_cell;
118
typedef signed32 signed_cell;
119
 
120
#endif /* _WORDS_H_ */

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.