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jeremybenn |
/* collection of junk waiting time to sort out
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Copyright (C) 2000, 2006, 2008, 2009, 2010 Free Software Foundation, Inc.
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Contributed by Red Hat, Inc.
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This file is part of the GNU Simulators.
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <http://www.gnu.org/licenses/>. */
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#ifndef SH64_SIM_H
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#define SH64_SIM_H
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#define GETTWI GETTSI
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#define SETTWI SETTSI
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enum {
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ISM_COMPACT, ISM_MEDIA
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};
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/* Hardware/device support. */
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extern device sh5_devices;
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/* FIXME: Temporary, until device support ready. */
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struct _device { int foo; };
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extern IDESC * sh64_idesc_media;
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extern IDESC * sh64_idesc_compact;
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/* Function prototypes from sh64.c. */
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BI sh64_endian (SIM_CPU *);
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VOID sh64_break (SIM_CPU *, PCADDR);
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SI sh64_movua (SIM_CPU *, PCADDR, SI);
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VOID sh64_trapa (SIM_CPU *, DI, PCADDR);
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VOID sh64_compact_trapa (SIM_CPU *, UQI, PCADDR);
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SF sh64_fldi0 (SIM_CPU *);
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SF sh64_fldi1 (SIM_CPU *);
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DF sh64_fcnvsd (SIM_CPU *, SF);
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SF sh64_fcnvds (SIM_CPU *, DF);
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DF sh64_fabsd (SIM_CPU *, DF);
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SF sh64_fabss (SIM_CPU *, SF);
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DF sh64_faddd (SIM_CPU *, DF, DF);
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SF sh64_fadds (SIM_CPU *, SF, SF);
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DF sh64_fdivd (SIM_CPU *, DF, DF);
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SF sh64_fdivs (SIM_CPU *, SF, SF);
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DF sh64_floatld (SIM_CPU *, SF);
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SF sh64_floatls (SIM_CPU *, SF);
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DF sh64_floatqd (SIM_CPU *, DF);
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SF sh64_floatqs (SIM_CPU *, DF);
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SF sh64_fmacs(SIM_CPU *, SF, SF, SF);
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DF sh64_fmuld (SIM_CPU *, DF, DF);
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SF sh64_fmuls (SIM_CPU *, SF, SF);
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DF sh64_fnegd (SIM_CPU *, DF);
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SF sh64_fnegs (SIM_CPU *, SF);
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DF sh64_fsqrtd (SIM_CPU *, DF);
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SF sh64_fsqrts (SIM_CPU *, SF);
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DF sh64_fsubd (SIM_CPU *, DF, DF);
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SF sh64_fsubs (SIM_CPU *, SF, SF);
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SF sh64_ftrcdl (SIM_CPU *, DF);
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DF sh64_ftrcdq (SIM_CPU *, DF);
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SF sh64_ftrcsl (SIM_CPU *, SF);
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DF sh64_ftrcsq (SIM_CPU *, SF);
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VOID sh64_ftrvs (SIM_CPU *, unsigned, unsigned, unsigned);
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VOID sh64_fipr (SIM_CPU *cpu, unsigned m, unsigned n);
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SF sh64_fiprs (SIM_CPU *cpu, unsigned g, unsigned h);
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VOID sh64_fldp (SIM_CPU *cpu, PCADDR pc, DI rm, DI rn, unsigned f);
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VOID sh64_fstp (SIM_CPU *cpu, PCADDR pc, DI rm, DI rn, unsigned f);
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VOID sh64_ftrv (SIM_CPU *cpu, UINT ignored);
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VOID sh64_pref (SIM_CPU *cpu, SI addr);
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BI sh64_fcmpeqs (SIM_CPU *, SF, SF);
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BI sh64_fcmpeqd (SIM_CPU *, DF, DF);
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BI sh64_fcmpges (SIM_CPU *, SF, SF);
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BI sh64_fcmpged (SIM_CPU *, DF, DF);
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BI sh64_fcmpgts (SIM_CPU *, SF, SF);
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BI sh64_fcmpgtd (SIM_CPU *, DF, DF);
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BI sh64_fcmpund (SIM_CPU *, DF, DF);
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BI sh64_fcmpuns (SIM_CPU *, SF, SF);
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DI sh64_nsb (SIM_CPU *, DI);
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#endif /* SH64_SIM_H */
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