OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [gnu-stable/] [gdb-7.2/] [sim/] [testsuite/] [d10v-elf/] [t-ae-st2w-is.s] - Blame information for rev 861

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 330 jeremybenn
.include "t-macros.i"
2
 
3
        start
4
 
5
        PSW_BITS = 0
6
        point_dmap_at_imem
7
        check_interrupt (VEC_AE&DMAP_MASK)+DMAP_BASE PSW_BITS test_st2w
8
 
9
        ldi sp, #0x4004
10
        st2w r8, @-SP
11
 
12
        ldi sp, #0x4005
13
test_st2w:
14
        st2w r8,@-SP
15
        nop
16
        exit47

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.