OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [gnu-stable/] [gdb-7.2/] [sim/] [testsuite/] [sim/] [fr30/] [ldm0.cgs] - Blame information for rev 841

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 330 jeremybenn
# fr30 testcase for ldm0 ($reglist_low)
2
# mach(): fr30
3
 
4
        .include "testutils.inc"
5
 
6
        START
7
 
8
        .text
9
        .global ldm0
10
ldm0:
11
        ; Test ldm0 ($reglist_low)
12
        mvr_h_gr        sp,r9           ; save stack pointer permanently
13
        inci_h_gr       -4,sp
14
        mvi_h_mem       3,sp
15
        inci_h_gr       -4,sp
16
        mvi_h_mem       2,sp
17
        inci_h_gr       -4,sp
18
        mvi_h_mem       1,sp
19
        inci_h_gr       -4,sp
20
        mvi_h_mem       0,sp
21
 
22
        set_cc          0x0f            ; Condition codes should not change
23
        ldm0            (r0,r2,r4,r6)
24
        test_cc         1 1 1 1
25
        testr_h_gr      sp,r9
26
        test_h_gr       0,r0
27
        test_h_gr       1,r2
28
        test_h_gr       2,r4
29
        test_h_gr       3,r6
30
 
31
        inci_h_gr       -16,sp
32
        set_cc          0x0f            ; Condition codes should not change
33
        ldm0            (r1,r3,r5,r7)
34
        test_cc         1 1 1 1
35
        testr_h_gr      sp,r9
36
        test_h_gr       0,r1
37
        test_h_gr       1,r3
38
        test_h_gr       2,r5
39
        test_h_gr       3,r7
40
 
41
        inci_h_gr       -16,sp
42
        set_cc          0x0f            ; Condition codes should not change
43
        ldm0            (r1,r5,r7,r3)   ; Order speficied should not matter
44
        test_cc         1 1 1 1
45
        testr_h_gr      sp,r9
46
        test_h_gr       0,r1
47
        test_h_gr       1,r3
48
        test_h_gr       2,r5
49
        test_h_gr       3,r7
50
 
51
        set_cc          0x0f            ; Condition codes should not change
52
        ldm0            ()              ; Nothing should happen
53
        test_cc         1 1 1 1
54
        testr_h_gr      sp,r9
55
        test_h_gr       0,r1
56
        test_h_gr       1,r3
57
        test_h_gr       2,r5
58
        test_h_gr       3,r7
59
 
60
        pass

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.